* [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC [not found] <CGME20250213004402epcas2p34923dcba3635ceed9b712a24f354d6f0@epcas2p3.samsung.com> @ 2025-02-13 0:41 ` Sangwook Shin 2025-02-13 2:03 ` Guenter Roeck 2025-02-13 4:55 ` Alim Akhtar 0 siblings, 2 replies; 3+ messages in thread From: Sangwook Shin @ 2025-02-13 0:41 UTC (permalink / raw) To: krzk, alim.akhtar, wim, linux Cc: linux-arm-kernel, linux-samsung-soc, linux-watchdog, linux-kernel, Kyunghwan Seo, Sangwook Shin From: Kyunghwan Seo <khwan.seo@samsung.com> Fix the PMU register bits for the ExynosAutoV920 SoC. This SoC has different bit information compared to its previous version, ExynosAutoV9, and we have made the necessary adjustments. rst_stat_bit: - ExynosAutoV920 cl0 : 0 - ExynosAutoV920 cl1 : 1 cnt_en_bit: - ExynosAutoV920 cl0 : 8 - ExynosAutoV920 cl1 : 8 Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com> Signed-off-by: Sangwook Shin <sw617.shin@samsung.com> --- drivers/watchdog/s3c2410_wdt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 30450e99e5e9..bdd81d8074b2 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -72,6 +72,8 @@ #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 +#define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT 0 +#define EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT 1 #define GS_CLUSTER0_NONCPU_OUT 0x1220 #define GS_CLUSTER1_NONCPU_OUT 0x1420 @@ -312,9 +314,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = { .mask_bit = 2, .mask_reset_inv = true, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, - .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT, + .rst_stat_bit = EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT, .cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT, - .cnt_en_bit = 7, + .cnt_en_bit = 8, .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_DBGACK_BIT, @@ -325,9 +327,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = { .mask_bit = 2, .mask_reset_inv = true, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, - .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT, + .rst_stat_bit = EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT, .cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT, - .cnt_en_bit = 7, + .cnt_en_bit = 8, .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_DBGACK_BIT, -- 2.40.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC 2025-02-13 0:41 ` [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC Sangwook Shin @ 2025-02-13 2:03 ` Guenter Roeck 2025-02-13 4:55 ` Alim Akhtar 1 sibling, 0 replies; 3+ messages in thread From: Guenter Roeck @ 2025-02-13 2:03 UTC (permalink / raw) To: Sangwook Shin, krzk, alim.akhtar, wim Cc: linux-arm-kernel, linux-samsung-soc, linux-watchdog, linux-kernel, Kyunghwan Seo On 2/12/25 16:41, Sangwook Shin wrote: > From: Kyunghwan Seo <khwan.seo@samsung.com> > > Fix the PMU register bits for the ExynosAutoV920 SoC. > This SoC has different bit information compared to its previous > version, ExynosAutoV9, and we have made the necessary adjustments. > > rst_stat_bit: > - ExynosAutoV920 cl0 : 0 > - ExynosAutoV920 cl1 : 1 > > cnt_en_bit: > - ExynosAutoV920 cl0 : 8 > - ExynosAutoV920 cl1 : 8 > > Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com> > Signed-off-by: Sangwook Shin <sw617.shin@samsung.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> ^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC 2025-02-13 0:41 ` [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC Sangwook Shin 2025-02-13 2:03 ` Guenter Roeck @ 2025-02-13 4:55 ` Alim Akhtar 1 sibling, 0 replies; 3+ messages in thread From: Alim Akhtar @ 2025-02-13 4:55 UTC (permalink / raw) To: 'Sangwook Shin', krzk, wim, linux Cc: linux-arm-kernel, linux-samsung-soc, linux-watchdog, linux-kernel, 'Kyunghwan Seo' Hello Sangwook > -----Original Message----- > From: Sangwook Shin <sw617.shin@samsung.com> > Sent: Thursday, February 13, 2025 6:11 AM > To: krzk@kernel.org; alim.akhtar@samsung.com; wim@linux-watchdog.org; > linux@roeck-us.net > Cc: linux-arm-kernel@lists.infradead.org; linux-samsung- > soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux- > kernel@vger.kernel.org; Kyunghwan Seo <khwan.seo@samsung.com>; > Sangwook Shin <sw617.shin@samsung.com> > Subject: [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for > ExynosAutoV920 SoC > > From: Kyunghwan Seo <khwan.seo@samsung.com> > > Fix the PMU register bits for the ExynosAutoV920 SoC. > This SoC has different bit information compared to its previous version, > ExynosAutoV9, and we have made the necessary adjustments. > > rst_stat_bit: > - ExynosAutoV920 cl0 : 0 > - ExynosAutoV920 cl1 : 1 > > cnt_en_bit: > - ExynosAutoV920 cl0 : 8 > - ExynosAutoV920 cl1 : 8 > > Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com> > Signed-off-by: Sangwook Shin <sw617.shin@samsung.com> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-02-13 0:41 ` [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC Sangwook Shin
2025-02-13 2:03 ` Guenter Roeck
2025-02-13 4:55 ` Alim Akhtar
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