[PATCH] net: wan: fsl_ucc_hdlc: allocate enough MURAM for HDLC PRAM

[PATCH] net: wan: fsl_ucc_hdlc: allocate enough MURAM for HDLC PRAM

[Matevz Langus]

More MURAM needs to be allocated than just sizeof(struct ucc_hdlc_param).
We have noticed MURAM corruption outside of struct ucc_hdlc_param. It was
caused by QE UCC HDLC microcode. NXP QEIWRM.pdf Rev.9 05/2018 chapter
14.2.2.1 HDLC Parameter RAM says 0x6c-0x100 Reserved.
Even looking into QE UCC HDLC microcode source code reveals it actually
stores data beyond 0x6c.

Tested on LS1043A, T1040 and MPC8569 boards running UCC in HDLC mode on kernel 6.12.

Signed-off-by: Matevz Langus <matevz.langus@borea.si>
---
 drivers/net/wan/fsl_ucc_hdlc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
index 71d5ad0a7b98..e170d3ac9116 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.h
+++ b/drivers/net/wan/fsl_ucc_hdlc.h
@@ -60,6 +60,7 @@ struct ucc_hdlc_param {
  __be16 haddr4;
  __be16 ts_tmp;
  __be16 tmp_mb;
+ __u8 reserved[148];
 };
   struct ucc_hdlc_private {
--  2.34.1

Re: [PATCH] net: wan: fsl_ucc_hdlc: allocate enough MURAM for HDLC PRAM

[Christophe Leroy (CS GROUP)]

Le 03/08/2026 à 14:58, Matevz Langus a écrit :
> [Vous ne recevez pas souvent de courriers de matevz.langus@borea.si. D?couvrez pourquoi ceci est important ? https://aka.ms/LearnAboutSenderIdentification ]
> 
> More MURAM needs to be allocated than just sizeof(struct ucc_hdlc_param).
> We have noticed MURAM corruption outside of struct ucc_hdlc_param. It was
> caused by QE UCC HDLC microcode. NXP QEIWRM.pdf Rev.9 05/2018 chapter
> 14.2.2.1 HDLC Parameter RAM says 0x6c-0x100 Reserved.
> Even looking into QE UCC HDLC microcode source code reveals it actually
> stores data beyond 0x6c.
> 
> Tested on LS1043A, T1040 and MPC8569 boards running UCC in HDLC mode on kernel 6.12.
> 
> Signed-off-by: Matevz Langus <matevz.langus@borea.si>

Same in MPC8323 reference manual, it is marked "reserved" until offset 0x100

Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>



> ---
>   drivers/net/wan/fsl_ucc_hdlc.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
> index 71d5ad0a7b98..e170d3ac9116 100644
> --- a/drivers/net/wan/fsl_ucc_hdlc.h
> +++ b/drivers/net/wan/fsl_ucc_hdlc.h
> @@ -60,6 +60,7 @@ struct ucc_hdlc_param {
>    __be16 haddr4;
>    __be16 ts_tmp;
>    __be16 tmp_mb;
> + __u8 reserved[148];
>   };
>     struct ucc_hdlc_private {
> --  2.34.1
> 
> 

Re: [PATCH] net: wan: fsl_ucc_hdlc: allocate enough MURAM for HDLC PRAM

[Matevz Langus]

Yes, this patch is for all devices with QE / QuiccEngine.
In reality also for CPM based devices like MPC8260 even MPC860 on all cases 256 Bytes should be reserved for PRAM.


> On 3 Aug 2026, at 16:18, Christophe Leroy (CS GROUP) <chleroy@kernel.org> wrote:
> 
> 
> 
> Le 03/08/2026 à 14:58, Matevz Langus a écrit :
>> [Vous ne recevez pas souvent de courriers de matevz.langus@borea.si. D?couvrez pourquoi ceci est important ? https://aka.ms/LearnAboutSenderIdentification ]
>> More MURAM needs to be allocated than just sizeof(struct ucc_hdlc_param).
>> We have noticed MURAM corruption outside of struct ucc_hdlc_param. It was
>> caused by QE UCC HDLC microcode. NXP QEIWRM.pdf Rev.9 05/2018 chapter
>> 14.2.2.1 HDLC Parameter RAM says 0x6c-0x100 Reserved.
>> Even looking into QE UCC HDLC microcode source code reveals it actually
>> stores data beyond 0x6c.
>> Tested on LS1043A, T1040 and MPC8569 boards running UCC in HDLC mode on kernel 6.12.
>> Signed-off-by: Matevz Langus <matevz.langus@borea.si>
> 
> Same in MPC8323 reference manual, it is marked "reserved" until offset 0x100
> 
> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> 
> 
> 
>> ---
>>  drivers/net/wan/fsl_ucc_hdlc.h | 1 +
>>  1 file changed, 1 insertion(+)
>> diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
>> index 71d5ad0a7b98..e170d3ac9116 100644
>> --- a/drivers/net/wan/fsl_ucc_hdlc.h
>> +++ b/drivers/net/wan/fsl_ucc_hdlc.h
>> @@ -60,6 +60,7 @@ struct ucc_hdlc_param {
>>   __be16 haddr4;
>>   __be16 ts_tmp;
>>   __be16 tmp_mb;
>> + __u8 reserved[148];
>>  };
>>    struct ucc_hdlc_private {
>> --  2.34.1
> 

Re: [PATCH] net: wan: fsl_ucc_hdlc: allocate enough MURAM for HDLC PRAM

[Christophe Leroy (CS GROUP)]

Le 03/08/2026 à 16:42, Matevz Langus a écrit :
> [Vous ne recevez pas souvent de courriers de matevz.langus@borea.si. Découvrez pourquoi ceci est important à https://aka.ms/LearnAboutSenderIdentification ]
> 
> Yes, this patch is for all devices with QE / QuiccEngine.
> In reality also for CPM based devices like MPC8260 even MPC860 on all cases 256 Bytes should be reserved for PRAM.

Please don't top-post

For MPC8260 I don't know, but but MPC860 it is not right, on MPC860 PRAM 
is fixed and you have another PRAM at offset 0x80 so the SCC PRAM is 128 
bytes max, except when using it for QMC.

Christophe


> 
> 
>> On 3 Aug 2026, at 16:18, Christophe Leroy (CS GROUP) <chleroy@kernel.org> wrote:
>>
>>
>>
>> Le 03/08/2026 à 14:58, Matevz Langus a écrit :
>>> [Vous ne recevez pas souvent de courriers de matevz.langus@borea.si. D?couvrez pourquoi ceci est important ? https://aka.ms/LearnAboutSenderIdentification ]
>>> More MURAM needs to be allocated than just sizeof(struct ucc_hdlc_param).
>>> We have noticed MURAM corruption outside of struct ucc_hdlc_param. It was
>>> caused by QE UCC HDLC microcode. NXP QEIWRM.pdf Rev.9 05/2018 chapter
>>> 14.2.2.1 HDLC Parameter RAM says 0x6c-0x100 Reserved.
>>> Even looking into QE UCC HDLC microcode source code reveals it actually
>>> stores data beyond 0x6c.
>>> Tested on LS1043A, T1040 and MPC8569 boards running UCC in HDLC mode on kernel 6.12.
>>> Signed-off-by: Matevz Langus <matevz.langus@borea.si>
>>
>> Same in MPC8323 reference manual, it is marked "reserved" until offset 0x100
>>
>> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
>>
>>
>>
>>> ---
>>>   drivers/net/wan/fsl_ucc_hdlc.h | 1 +
>>>   1 file changed, 1 insertion(+)
>>> diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
>>> index 71d5ad0a7b98..e170d3ac9116 100644
>>> --- a/drivers/net/wan/fsl_ucc_hdlc.h
>>> +++ b/drivers/net/wan/fsl_ucc_hdlc.h
>>> @@ -60,6 +60,7 @@ struct ucc_hdlc_param {
>>>    __be16 haddr4;
>>>    __be16 ts_tmp;
>>>    __be16 tmp_mb;
>>> + __u8 reserved[148];
>>>   };
>>>     struct ucc_hdlc_private {
>>> --  2.34.1
>>
>