Re: [RESEND PATCH v4 01/15] x86/resctrl: Support Privilege Level Zero Association (PLZA)

[Babu Moger <babu.moger@amd.com>]

On 7/7/26 16:50, Babu Moger wrote:
> Customers have identified an issue while using the QoS resource control
> feature. If memory bandwidth associated with a CLOSID is aggressively
> throttled, and a task with that CLOSID moves into kernel mode, the kernel
> operations are also aggressively throttled. This can stall forward progress
> and eventually degrade overall system performance.
> 
> AMD hardware supports a feature Privilege Level Zero Association (PLZA),
> which allows the CPU's CLOSID association to be changed during the
> transition from user mode to kernel mode. This allows the kernel to run
> using a different CLOSID than user space, which can improve system
> performance in certain scenarios.
> 
> The feature is detected via CPUID_Fn80000020_EBX_x00 [Bit 9]:
> Privilege Level Zero Association (PLZA).
> 
> The PLZA feature details are documented in [1] available from [2].
> 
> [1] AMD64 Zen6 Platform Quality of Service (PQOS) Extensions:
>      Publication # 69193 Revision: 1.00, Issue Date: March 2026
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> v4: Split the patch into 2. This patch only handles x86 changes.
>      Re-wrote the changelog along the ABMC changes.
> 
> v3: Code did not change. Patch order changed.
>      Added documentation link.
> 
> v2: Rebased on top of the latest tip.
> ---
>   arch/x86/include/asm/cpufeatures.h | 1 +
>   arch/x86/kernel/cpu/scattered.c    | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 1b4a48bff18f..bf6fc71f87fa 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -517,6 +517,7 @@
>   						      * and purposes if CLEAR_CPU_BUF_VM is set).
>   						      */
>   #define X86_FEATURE_X2AVIC_EXT		(21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */
> +#define X86_FEATURE_PLZA		(21*32+21) /* Privilege Level Zero Association */
>   
>   /*
>    * BUG word(s)
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 937129ce6a96..1fa4d5aef17e 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -61,6 +61,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>   	{ X86_FEATURE_BMEC,			CPUID_EBX,  3, 0x80000020, 0 },
>   	{ X86_FEATURE_ABMC,			CPUID_EBX,  5, 0x80000020, 0 },
>   	{ X86_FEATURE_SDCIAE,			CPUID_EBX,  6, 0x80000020, 0 },
> +	{ X86_FEATURE_PLZA,			CPUID_EBX,  9, 0x80000020, 0 },
>   	{ X86_FEATURE_TSA_SQ_NO,		CPUID_ECX,  1, 0x80000021, 0 },
>   	{ X86_FEATURE_TSA_L1_NO,		CPUID_ECX,  2, 0x80000021, 0 },
>   	{ X86_FEATURE_AMD_WORKLOAD_CLASS,	CPUID_EAX, 22, 0x80000021, 0 },

Sashiko reported:

--- Patch [1]: [RESEND PATCH v4 01/15] x86/resctrl: Support Privilege 
Level Zero Association (PLZA) ---
commit 0f2aa093b81d7a2e0dc203ce3466562f708898df
Author: Babu Moger <babu.moger@amd.com>
x86/resctrl: Support Privilege Level Zero Association (PLZA)
This commit adds support for AMD's Privilege Level Zero Association (PLZA)
feature. It detects the feature via CPUID_Fn80000020_EBX_x00 [Bit 9] and
adds the corresponding feature flag to the x86 cpufeatures array.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
 > diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
 > index 1b4a48bff18f7..bf6fc71f87fab 100644
 > --- a/arch/x86/include/asm/cpufeatures.h
 > +++ b/arch/x86/include/asm/cpufeatures.h
 > @@ -517,6 +517,7 @@
 >  						      * and purposes if CLEAR_CPU_BUF_VM is set).
 >  						      */
 >  #define X86_FEATURE_X2AVIC_EXT		(21*32+20) /* AMD SVM x2AVIC support 
for 4k vCPUs */
 > +#define X86_FEATURE_PLZA		(21*32+21) /* Privilege Level Zero 
Association */
Should this addition also be mirrored in the tools directory copies of
cpufeatures.h and kcpuid.csv?
If tools/arch/x86/include/asm/cpufeatures.h is not updated to match, 
tools like
perf can generate build warnings during check-headers.sh verification. Also,
without updating tools/arch/x86/kcpuid/cpuid.csv, the kcpuid tool will be
unaware of the new PLZA feature bit when users query CPU capabilities.


I thought tools/arch/x86/include/asm/cpufeatures.h would be synced after 
the changes to arch/x86/include/asm/cpufeatures.h are merged. Has that 
process changed?

If the expectation is to update tools/arch/x86/include/asm/cpufeatures.h 
as part of this patch, I can add those changes as well.

Thanks,
Babu