Re: [RESEND PATCH v4 03/15] x86/resctrl: Add data structures and definitions for PLZA configuration

[Babu Moger <babu.moger@amd.com>]

On 7/7/26 16:50, Babu Moger wrote:
> Privilege Level Zero Association (PLZA) allows the kernel to use a
> different CLOSID (and optionally RMID) than user mode on entry to kernel
> mode. The CLOSID/RMID association is programmed per CPU via
> MSR_IA32_PQR_PLZA_ASSOC (0xc00003fc), using RMID/CLOSID values and their
> respective enable bits.
> 
> Add the MSR definition and union msr_pqr_plza_assoc to represent the MSR
> bitfield layout used by subsequent PLZA programming.
> 
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> v4: Re-wrote the changelog and code comment.
> 
> v3: No code changes. Patch order changed. Improved changelog.
> 
> v2: No changes. Just rebasing on top of the latest tip branch.
> ---
>   arch/x86/include/asm/msr-index.h       |  1 +
>   arch/x86/kernel/cpu/resctrl/internal.h | 37 ++++++++++++++++++++++++++
>   2 files changed, 38 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 18c4be75e927..2503451a95fe 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -1292,6 +1292,7 @@
>   /* - AMD: */
>   #define MSR_IA32_MBA_BW_BASE		0xc0000200
>   #define MSR_IA32_SMBA_BW_BASE		0xc0000280
> +#define MSR_IA32_PQR_PLZA_ASSOC		0xc00003fc
>   #define MSR_IA32_L3_QOS_ABMC_CFG	0xc00003fd
>   #define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff
>   #define MSR_IA32_EVT_CFG_BASE		0xc0000400
> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
> index e3cfa0c10e92..020ebc2c8a1f 100644
> --- a/arch/x86/kernel/cpu/resctrl/internal.h
> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
> @@ -222,6 +222,43 @@ union l3_qos_abmc_cfg {
>   	unsigned long full;
>   };
>   
> +/*
> + * Privilege Level Zero Association (PLZA) is configured by writing to
> + * MSR_IA32_PQR_PLZA_ASSOC. The MSR must be programmed on every CPU in
> + * the QoS domain. Each domain supports only one PLZA CLOSID and/or RMID
> + * association. All fields other than PLZA_EN must hold the same value
> + * across the domain for consistent operation.
> + *
> + * When PLZA_EN is set, the CLOSID/RMID association used at CPL 0 is
> + * taken from MSR_IA32_PQR_PLZA_ASSOC instead of MSR_IA32_PQR_ASSOC.
> + *
> + * @rmid		: RMID associated with PLZA.
> + * @reserved1		: Reserved.
> + * @rmid_en		: Enable RMID association for PLZA.
> + * @closid		: CLOSID associated with PLZA.
> + * @reserved2		: Reserved.
> + * @closid_en		: Enable CLOSID association for PLZA.
> + * @reserved3		: Reserved.
> + * @plza_en		: Enable PLZA. When enabled, PLZA applies to the
> + *			  given CPU. When PLZA is disabled for a CPU, the
> + *			  CLOSID and RMID association defined in the
> + *			  PQR_ASSOC MSR applies, regardless of the CPU's
> + *			  privilege level.
> + */
> +union msr_pqr_plza_assoc {
> +	struct {
> +		unsigned long rmid	:12,
> +			      reserved1	:19,
> +			      rmid_en	: 1,
> +			      closid	: 4,
> +			      reserved2	:11,
> +			      closid_en	: 1,
> +			      reserved3	:15,
> +			      plza_en	: 1;
> +	} split;
> +	unsigned long full;
> +};
> +

Sashiko reported:

https://sashiko.dev/#/patchset/cover.1783461016.git.babu.moger%40amd.com?part=3

 > This is a pre-existing issue, but does this union truncate data on 
32-> bit x86 builds? On 32-bit kernels, unsigned long is 32 bits, but the
 > bitfields sum to  64 bits.

Will change the union to use 'u64' type for 'unsigned long'.

It also reported problem with "l3_qos_abmc_cfg".

Will fix that as well.

thanks
Babu