From: Zenghui Yu <zenghui.yu@linux.dev>
To: Jinqian Yang <yangjinqian1@huawei.com>
Cc: catalin.marinas@arm.com, will@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, wangzhou1@hisilicon.com,
shenjian15@huawei.com, linuxarm@huawei.com
Subject: Re: [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation
Date: Sun, 28 Dec 2025 22:27:48 +0800 [thread overview]
Message-ID: <0c9456b1-d7c8-4a90-ac21-fa2e5ee4a170@linux.dev> (raw)
In-Reply-To: <20251227092448.732059-1-yangjinqian1@huawei.com>
On 2025/12/27 17:24, Jinqian Yang wrote:
> The TSV110 processor is vulnerable to the Spectre-BHB (Branch History
> Buffer) attack, which can be exploited to leak information through
> branch prediction side channels. This commit adds the MIDR of TSV110
> to the list for software mitigation.
>
> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com>
> ---
> arch/arm64/kernel/proton-pack.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
> index 80a580e019c5..b3801f532b10 100644
> --- a/arch/arm64/kernel/proton-pack.c
> +++ b/arch/arm64/kernel/proton-pack.c
> @@ -887,6 +887,7 @@ static u8 spectre_bhb_loop_affected(void)
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
> + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
> {},
> };
> static const struct midr_range spectre_bhb_k24_list[] = {
Looks good, thanks!
Reviewed-by: Zenghui Yu <zenghui.yu@linux.dev>
Zenghui
next prev parent reply other threads:[~2025-12-28 14:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-27 9:24 [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation Jinqian Yang
2025-12-28 14:27 ` Zenghui Yu [this message]
2026-01-05 22:58 ` Will Deacon
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