* [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation
@ 2025-12-27 9:24 Jinqian Yang
2025-12-28 14:27 ` Zenghui Yu
2026-01-05 22:58 ` Will Deacon
0 siblings, 2 replies; 3+ messages in thread
From: Jinqian Yang @ 2025-12-27 9:24 UTC (permalink / raw)
To: catalin.marinas, will
Cc: linux-arm-kernel, linux-kernel, wangzhou1, shenjian15, linuxarm,
Jinqian Yang
The TSV110 processor is vulnerable to the Spectre-BHB (Branch History
Buffer) attack, which can be exploited to leak information through
branch prediction side channels. This commit adds the MIDR of TSV110
to the list for software mitigation.
Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com>
---
arch/arm64/kernel/proton-pack.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
index 80a580e019c5..b3801f532b10 100644
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@ -887,6 +887,7 @@ static u8 spectre_bhb_loop_affected(void)
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+ MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
{},
};
static const struct midr_range spectre_bhb_k24_list[] = {
--
2.33.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation
2025-12-27 9:24 [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation Jinqian Yang
@ 2025-12-28 14:27 ` Zenghui Yu
2026-01-05 22:58 ` Will Deacon
1 sibling, 0 replies; 3+ messages in thread
From: Zenghui Yu @ 2025-12-28 14:27 UTC (permalink / raw)
To: Jinqian Yang
Cc: catalin.marinas, will, linux-arm-kernel, linux-kernel, wangzhou1,
shenjian15, linuxarm
On 2025/12/27 17:24, Jinqian Yang wrote:
> The TSV110 processor is vulnerable to the Spectre-BHB (Branch History
> Buffer) attack, which can be exploited to leak information through
> branch prediction side channels. This commit adds the MIDR of TSV110
> to the list for software mitigation.
>
> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com>
> ---
> arch/arm64/kernel/proton-pack.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
> index 80a580e019c5..b3801f532b10 100644
> --- a/arch/arm64/kernel/proton-pack.c
> +++ b/arch/arm64/kernel/proton-pack.c
> @@ -887,6 +887,7 @@ static u8 spectre_bhb_loop_affected(void)
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
> + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
> {},
> };
> static const struct midr_range spectre_bhb_k24_list[] = {
Looks good, thanks!
Reviewed-by: Zenghui Yu <zenghui.yu@linux.dev>
Zenghui
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation
2025-12-27 9:24 [PATCH] arm64: Add support for TSV110 Spectre-BHB mitigation Jinqian Yang
2025-12-28 14:27 ` Zenghui Yu
@ 2026-01-05 22:58 ` Will Deacon
1 sibling, 0 replies; 3+ messages in thread
From: Will Deacon @ 2026-01-05 22:58 UTC (permalink / raw)
To: catalin.marinas, Jinqian Yang
Cc: kernel-team, Will Deacon, linux-arm-kernel, linux-kernel,
wangzhou1, shenjian15, linuxarm
On Sat, 27 Dec 2025 17:24:48 +0800, Jinqian Yang wrote:
> The TSV110 processor is vulnerable to the Spectre-BHB (Branch History
> Buffer) attack, which can be exploited to leak information through
> branch prediction side channels. This commit adds the MIDR of TSV110
> to the list for software mitigation.
>
>
Applied to arm64 (for-next/cpufeature), thanks!
[1/1] arm64: Add support for TSV110 Spectre-BHB mitigation
https://git.kernel.org/arm64/c/e3baa5d4b361
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-12-28 14:27 ` Zenghui Yu
2026-01-05 22:58 ` Will Deacon
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