From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Krzysztof Halasa <khc@pm.waw.pl>
Cc: linux-kernel@vger.kernel.org, Jeff Garzik <jeff@garzik.org>
Subject: Re: 2.6.18-rc5 + pata-drivers on MSI K9N Ultra report, AMD64
Date: Mon, 04 Sep 2006 12:16:35 +0100 [thread overview]
Message-ID: <1157368595.30801.23.camel@localhost.localdomain> (raw)
In-Reply-To: <m3lkp1anwf.fsf@defiant.localdomain>
Ar Sul, 2006-09-03 am 00:45 +0200, ysgrifennodd Krzysztof Halasa:
> Hmmm... is it that 0x62, isn't it?
>
> static struct pci_bits amd_enable_bits[] = {
> { 0x40, 1, 0x02, 0x02 },
> { 0x40, 1, 0x01, 0x01 }
> };
The Nvidia ones have the register base at 0x50. Looking at the code I
think its just a case of adding an 0x50 based enable_bits test to
nv_pre_reset, and I'll fold that in now.
--
VGER BF report: U 0.474419
next prev parent reply other threads:[~2006-09-04 10:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-02 20:14 2.6.18-rc5 + pata-drivers on MSI K9N Ultra report, AMD64 Krzysztof Halasa
2006-09-02 22:09 ` Alan Cox
2006-09-02 22:45 ` Krzysztof Halasa
2006-09-04 11:16 ` Alan Cox [this message]
2006-09-04 12:18 ` Krzysztof Halasa
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