From: Krzysztof Kozlowski <krzk@kernel.org>
To: Kevin Chen <kevin_chen@aspeedtech.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
joel@jms.id.au, andrew@codeconstruct.com.au, tglx@linutronix.de,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, quic_bjorande@quicinc.com,
geert+renesas@glider.be, dmitry.baryshkov@linaro.org,
konradybcio@kernel.org, neil.armstrong@linaro.org,
johan+linaro@kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
soc@lists.linux.dev
Subject: Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
Date: Fri, 13 Dec 2024 08:58:48 +0100 [thread overview]
Message-ID: <11ad5a97-b066-4bea-8829-50e0416cea9d@kernel.org> (raw)
In-Reply-To: <20241212155237.848336-3-kevin_chen@aspeedtech.com>
On 12/12/2024 16:52, Kevin Chen wrote:
> 1. Because size-cells is no need to use 2, modify to 1 for use.
???
> 2. Add minItems to 1 for interrupts for intc1.
???
> 3. Add 1 interrupt of intc1 example into yaml file.
> 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
What is all this?
BTW, there was no such patch in previous version and your changelog is
silent about it.
Subject: drop all full stops. Subject never ends with full stop.
> ---
> .../aspeed,ast2700-intc.yaml | 60 +++++++++++++++----
> 1 file changed, 47 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> index 55636d06a674..eadfbc45326b 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> @@ -31,6 +31,7 @@ properties:
> type as defined in interrupt.txt in this directory.
>
> interrupts:
> + minItems: 1
Nope, not explained, not constrained. Your schema is supposed to be
constrained.
> maxItems: 6
> description: |
> Depend to which INTC0 or INTC1 used.
> @@ -68,19 +69,52 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> bus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + intc0: interrupt-controller@12100000 {
> + compatible = "simple-mfd";
> + reg = <0 0x12100000 0x4000>;
> + ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
> #address-cells = <2>;
> - #size-cells = <2>;
> -
> - interrupt-controller@12101b00 {
> - compatible = "aspeed,ast2700-intc-ic";
> - reg = <0 0x12101b00 0 0x10>;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
I don't understand what is all this.
> + #size-cells = <1>;
> +
> + intc0_11: interrupt-controller@1b00 {
> + compatible = "aspeed,ast2700-intc-ic";
> + reg = <0 0x12101b00 0x10>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> + };
> +
> + intc1: interrupt-controller@14c18000 {
> + compatible = "simple-mfd";
> + reg = <0 0x14c18000 0x400>;
> + ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + intc1_4: interrupt-controller@140 {
> + compatible = "aspeed,ast2700-intc-ic";
> + reg = <0x0 0x140 0x10>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupts-extended = <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> + };
> +
> + uart12: serial@14c33b00 {
> + compatible = "ns16550a";
> + reg = <0x0 0x14c33b00 0x100>;
> + interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + no-loopback-test;
> + };
And above is not related at all. Don't add entirely unrelated changes. Drop.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-12-13 7:58 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-12 15:52 [PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC Kevin Chen
2024-12-12 15:52 ` [PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC Kevin Chen
2024-12-13 7:56 ` Krzysztof Kozlowski
2024-12-12 15:52 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage Kevin Chen
2024-12-13 7:58 ` Krzysztof Kozlowski [this message]
2024-12-18 3:04 ` Kevin Chen
2024-12-18 8:07 ` Krzysztof Kozlowski
2024-12-13 9:10 ` Krzysztof Kozlowski
2024-12-16 3:50 ` Kevin Chen
2024-12-12 15:52 ` [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC Kevin Chen
2024-12-13 7:59 ` Krzysztof Kozlowski
2024-12-13 8:03 ` Krzysztof Kozlowski
2024-12-18 2:55 ` Kevin Chen
2024-12-18 8:11 ` Krzysztof Kozlowski
2024-12-12 15:52 ` [PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc Kevin Chen
2024-12-13 7:59 ` Krzysztof Kozlowski
2024-12-12 15:52 ` [PATCH v3 3/6] arm64: aspeed: Add support for ASPEED AST27XX BMC SoC Kevin Chen
2024-12-12 15:52 ` [PATCH v3 4/6] arm64: dts: aspeed: Add initial AST27XX device tree Kevin Chen
2024-12-13 8:01 ` Krzysztof Kozlowski
2024-12-18 2:50 ` Kevin Chen
2024-12-12 15:52 ` [PATCH v3 5/6] arm64: dts: aspeed: Add initial AST2700 EVB " Kevin Chen
2024-12-13 8:03 ` Krzysztof Kozlowski
2024-12-16 3:58 ` Kevin Chen
2024-12-12 15:52 ` [PATCH v3 6/6] arm64: defconfig: Add ASPEED AST2700 family support Kevin Chen
2024-12-13 5:07 ` [PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC Andrew Jeffery
2024-12-16 3:34 ` Kevin Chen
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