From: Jaswinder Singh Rajput <jaswinder@kernel.org>
To: x86 maintainers <x86@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH V2] X86: Fix x86_cache_size value
Date: Fri, 14 Aug 2009 16:03:56 +0530 [thread overview]
Message-ID: <1250246036.9062.5.camel@ht.satnam> (raw)
In-Reply-To: <1250245149.9062.3.camel@ht.satnam>
Currently x86_cache_size is showing partial value: L1 or L2 or L3.
It should add all caches like L1 + L2 + L3 + Trace.
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
arch/x86/kernel/cpu/common.c | 2 +-
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5ce60a8..581fe17 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -422,7 +422,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
return; /* Again, no L2 cache is possible */
#endif
- c->x86_cache_size = l2size;
+ c->x86_cache_size += l2size;
printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
l2size, ecx & 0xFF);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 789efe2..43da49e 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -503,7 +503,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
if (l3)
printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
- c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
+ c->x86_cache_size = l3 + l2 + l1i + l1d + trace;
return l2;
}
--
1.6.0.6
next prev parent reply other threads:[~2009-08-14 10:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-08-14 10:19 [PATCH] X86: Fix x86_cache_size value Jaswinder Singh Rajput
2009-08-14 10:33 ` Jaswinder Singh Rajput [this message]
2009-08-14 18:09 ` [PATCH V2] " Valdis.Kletnieks
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