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From: Mario Limonciello <mario.limonciello@amd.com>
To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Cc: "Borislav Petkov" <bp@alien8.de>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	x86@kernel.org, "Gautham R . Shenoy" <gautham.shenoy@amd.com>,
	"Perry Yuan" <perry.yuan@amd.com>,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org,
	"Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
Subject: Re: [PATCH v2 05/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver
Date: Tue, 15 Oct 2024 13:09:42 -0500	[thread overview]
Message-ID: <1395bee1-95a7-4d14-a5e8-0e1dc71fadac@amd.com> (raw)
In-Reply-To: <20241015035233.GA28522@ranerica-svr.sc.intel.com>

On 10/14/2024 22:52, Ricardo Neri wrote:
> On Thu, Oct 10, 2024 at 02:36:57PM -0500, Mario Limonciello wrote:
>> From: Perry Yuan <Perry.Yuan@amd.com>
>>
>> The AMD Heterogeneous core design and Hardware Feedback Interface (HFI)
>> provide behavioral classification and a dynamically updated ranking table
>> for the scheduler to use when choosing cores for tasks.
>>
>> There are two CPU core types defined: `Classic Core` and `Dense Core`.
>> "Classic" cores are the standard performance cores, while "Dense" cores
>> are optimized for area and efficiency.
>>
>> Heterogeneous compute refers to CPU implementations that are comprised
>> of more than one architectural class, each with two capabilities. This
>> means each CPU reports two separate capabilities: "perf" and "eff".
>>
>> Each capability lists all core ranking numbers between 0 and 255, where
>> a higher number represents a higher capability.
>>
>> Heterogeneous systems can also extend to more than two architectural
>> classes.
>>
>> The purpose of the scheduling feedback mechanism is to provide information
>> to the operating system scheduler in real time, allowing the scheduler to
>> direct threads to the optimal core during task scheduling.
>>
>> All core ranking data are provided by the BIOS via a shared memory ranking
>> table, which the driver reads and uses to update core capabilities to the
>> scheduler. When the hardware updates the table, it generates a platform
>> interrupt to notify the OS to read the new ranking table.
>>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> 
> I tried to find the HFI details on the documents in this "bug" but I could
> not find them. What document in specific could I look at?
> 
> Thanks and BR,
> Ricardo

Hi Ricardo,

It is spread out across multiple places.  This is part of the reason for 
patch 1 in the series outlines details of how it works.

The reason for that "collect all" Bugzilla for documentation is because 
the URLs for AMD documentation have undergone changes in the past and it 
makes it difficult to put stable URLs in commit messages.  So teams that 
want to reference documentation put it on a dump all bug for a stable 
URL to reference.

On that link you will find the APM, which will have some documentation 
specifically for the CPUID leafs used for topology identification and 
clearing history.

Read patch 1 and let me know if it covers what specifically you're 
looking for.  If it's still missing some info let me know what you would 
like added.

Also; I do want to note something; this is the first series to lay some 
foundation for static information and not everything in patch 1 is 
implemented in this first series.  There will be further follow-ups later.

  reply	other threads:[~2024-10-15 18:09 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-10 19:36 [PATCH v2 00/13] Add support for AMD hardware feedback interface Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Mario Limonciello
2024-10-12  3:53   ` Bagas Sanjaya
2024-10-10 19:36 ` [PATCH v2 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 03/13] x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 04/13] x86/msr-index: define AMD heterogeneous CPU related MSR Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 05/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Mario Limonciello
2024-10-14  9:10   ` Ilpo Järvinen
2024-10-14 19:46     ` Mario Limonciello
2024-10-14  9:20   ` Ilpo Järvinen
2024-10-15  3:52   ` Ricardo Neri
2024-10-15 18:09     ` Mario Limonciello [this message]
2024-10-17 23:33       ` Ricardo Neri
2024-10-18 13:46         ` Mario Limonciello
2024-10-16  9:36   ` Uwe Kleine-König
2024-10-16  9:59     ` Hans de Goede
2024-10-16 16:06       ` Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 06/13] platform/x86: hfi: parse CPU core ranking data from shared memory Mario Limonciello
2024-10-14 10:14   ` Ilpo Järvinen
2024-10-14 20:09     ` Mario Limonciello
2024-10-10 19:36 ` [PATCH v2 07/13] platform/x86: hfi: init per-cpu scores for each class Mario Limonciello
2024-10-14 10:15   ` Ilpo Järvinen
2024-10-10 19:37 ` [PATCH v2 08/13] platform/x86: hfi: add online and offline callback support Mario Limonciello
2024-10-14 10:27   ` Ilpo Järvinen
2024-10-10 19:37 ` [PATCH v2 09/13] platform/x86: hfi: add power management callback Mario Limonciello
2024-10-14 10:29   ` Ilpo Järvinen
2024-10-10 19:37 ` [PATCH v2 10/13] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Mario Limonciello
2024-10-10 19:37 ` [PATCH v2 11/13] x86/process: Clear hardware feedback history for AMD processors Mario Limonciello
2024-10-10 19:37 ` [PATCH v2 12/13] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Mario Limonciello
2024-10-10 19:37 ` [PATCH v2 13/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Mario Limonciello
2024-10-11  0:54 ` [PATCH v2 00/13] Add support for AMD hardware feedback interface Bagas Sanjaya
2024-10-11  1:29   ` Mario Limonciello
2024-10-12  2:21     ` Bagas Sanjaya

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