[PATCH RFC net-next 00/19] net: mvpp2: Add TX Flow Control support

[<stefanc@marvell.com>]

From: Stefan Chulski <stefanc@marvell.com>

Armada hardware has a pause generation mechanism in GOP (MAC).
GOP has to generate flow control frames based on an indication
programmed in Ports Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register
only sends a one time pause. To complement the function the GOP has
a mechanism to periodically send pause control messages based on periodic counters.
This mechanism ensures that the pause is effective as long as the Appropriate PortX Pause
is asserted.

Problem is that Packet Processor witch actually can drop packets due to lack of resources
not connected to the GOP flow control generation mechanism.
To solve this issue Armada has firmware running on CM3 CPU dedectated for Flow Control
support. Firmware monitors Packet Processor resources and asserts XON/XOFF by writing
to Ports Control 0 Register.

MSS shared memory used to communicate between CM3 firmware and MVPP2 driver.
During init MVPP2 driver informs firmware about used BM pools, RXQs and congestion and
depletion thresholds.

The pause is generated whenever congestion or depletion in resources is detected.
The back pressure is stopped when the resource reaches a sufficient level.
So the congestion/depletion and sufficient implement a hysteresis mechanism that
reduces the toggle frequency.

For buffer pools which are a depletion means that a pause frame should be generated.
For this the SW needs to poll BPPINumberOfPointers and BPPENumberOfPoint. For queues
congestion means that a pause frame should be generated. For this the SW
needs to poll OccupiedDescriptorsCounter.

Packet Processor v23 has hardware support to monitor FIFO fill level.
patch "add PPv23 version definition" to differ between v23 and v22 hardware.
Patch "add TX FC firmware check" verifies that CM3 firmware support Flow Control
monitoring.

Konstantin Porotchkin (1):
  dts: marvell: add CM3 SRAM memory to cp115 ethernet device tree

Stefan Chulski (18):
  doc: marvell: add cm3-mem device tree bindings description
  net: mvpp2: add CM3 SRAM memory map
  net: mvpp2: add PPv23 version definition
  net: mvpp2: always compare hw-version vs MVPP21
  net: mvpp2: increase BM pool size to 2048 buffers
  net: mvpp2: increase RXQ size to 1024 descriptors
  net: mvpp2: add FCA periodic timer configurations
  net: mvpp2: add FCA RXQ non occupied descriptor threshold
  net: mvpp2: add spinlock for FW FCA configuration path
  net: mvpp2: add flow control RXQ and BM pool config callbacks
  net: mvpp2: enable global flow control
  net: mvpp2: add RXQ flow control configurations
  net: mvpp2: add ethtool flow control configuration support
  net: mvpp2: add BM protection underrun feature support
  net: mvpp2: add PPv23 RX FIFO flow control
  net: mvpp2: set 802.3x GoP Flow Control mode
  net: mvpp2: add ring size validation before enabling FC
  net: mvpp2: add TX FC firmware check

 Documentation/devicetree/bindings/net/marvell-pp2.txt |   1 +
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi         |  10 +
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h            | 130 ++++-
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c       | 570 +++++++++++++++++++-
 4 files changed, 669 insertions(+), 42 deletions(-)

-- 
1.9.1