* [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
@ 2023-08-09 16:56 Mingzheng Xing
2023-08-17 15:20 ` patchwork-bot+linux-riscv
0 siblings, 1 reply; 8+ messages in thread
From: Mingzheng Xing @ 2023-08-09 16:56 UTC (permalink / raw)
To: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Nathan Chancellor, Nick Desaulniers, Tom Rix
Cc: Bin Meng, Guo Ren, linux-riscv, linux-kernel, llvm, stable,
Mingzheng Xing, Conor Dooley
Binutils-2.38 and GCC-12.1.0 bumped[0][1] the default ISA spec to the newer
20191213 version which moves some instructions from the I extension to the
Zicsr and Zifencei extensions. So if one of the binutils and GCC exceeds
that version, we should explicitly specifying Zicsr and Zifencei via -march
to cope with the new changes. but this only occurs when binutils >= 2.36
and GCC >= 11.1.0. It's a different story when binutils < 2.36.
binutils-2.36 supports the Zifencei extension[2] and splits Zifencei and
Zicsr from I[3]. GCC-11.1.0 is particular[4] because it add support Zicsr
and Zifencei extension for -march. binutils-2.35 does not support the
Zifencei extension, and does not need to specify Zicsr and Zifencei when
working with GCC >= 12.1.0.
To make our lives easier, let's relax the check to binutils >= 2.36 in
CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. For the other two cases,
where clang < 17 or GCC < 11.1.0, we will deal with them in
CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
For more information, please refer to:
commit 6df2a016c0c8 ("riscv: fix build with binutils 2.38")
commit e89c2e815e76 ("riscv: Handle zicsr/zifencei issues between clang and binutils")
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc [0]
Link: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd [1]
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=5a1b31e1e1cee6e9f1c92abff59cdcfff0dddf30 [2]
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=729a53530e86972d1143553a415db34e6e01d5d2 [3]
Link: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49 [4]
Link: https://lore.kernel.org/all/20230308220842.1231003-1-conor@kernel.org
Link: https://lore.kernel.org/all/20230223220546.52879-1-conor@kernel.org
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Guo Ren <guoren@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
---
Changelog and test results:
v4 -> v5:
- Add Reviewed-by and Acked-by to commit message, no other code
changes.
v3 -> v4:
- Update the Kconfig help text and commit message.
Link: https://lore.kernel.org/all/20230731150511.38140-1-xingmingzheng@iscas.ac.cn
v2 -> v3:
- Relax the check to binutils >= 2.36.
- Update the Kconfig help text and commit message.
Link: https://lore.kernel.org/all/20230731095936.23397-1-xingmingzheng@iscas.ac.cn
v1 -> v2:
- Update the Kconfig help text and commit message.
- Add considerations for low version gcc case.
Link: https://lore.kernel.org/all/20230726174524.340952-1-xingmingzheng@iscas.ac.cn
v1:
Link: https://lore.kernel.org/all/20230725170405.251011-1-xingmingzheng@iscas.ac.cn
Here are my test results:
* Compiling the kernel for the master branch with a combination of
multiple versions of gcc and binutils.
gcc binutils patched no patch
11.4.0 2.35 ok ok
11.4.0 2.36 ok ok
11.4.0 2.38 ok ok
12.2.0 2.35 ok error[1]
12.2.0 2.36 ok error[2]
12.2.0 2.38 ok ok
10.5.0 2.35 ok ok
10.5.0 2.36 ok ok
10.5.0 2.38 ok error[3]
11.1.0 2.35 ok ok
11.1.0 2.36 ok ok
11.1.0 2.38 ok ok
11.2.0 2.35 ok ok
11.2.0 2.36 ok ok
11.2.0 2.38 ok ok
[1]
Assembler messages:
Fatal error: -march=rv32imafd_zicsr_zifencei: Invalid or unknown z ISA extension: 'zifencei'
make[2]: *** [arch/riscv/kernel/compat_vdso/Makefile:47: arch/riscv/kernel/compat_vdso/rt_sigreturn.o] Error 1
[2]
./arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
./arch/riscv/include/asm/vdso/gettimeofday.h:79: Error: unrecognized opcode `csrr a5,0xc01'
./arch/riscv/include/asm/vdso/gettimeofday.h:79: Error: unrecognized opcode `csrr a5,0xc01'
./arch/riscv/include/asm/vdso/gettimeofday.h:79: Error: unrecognized opcode `csrr a5,0xc01'
./arch/riscv/include/asm/vdso/gettimeofday.h:79: Error: unrecognized opcode `csrr a5,0xc01'
make[2]: *** [scripts/Makefile.build:243: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1
[3]
cc1: error: '-march=rv64imac_zicsr_zifencei': unsupported ISA subset 'z'
cc1: error: ABI requires '-march=rv64'
make[2]: *** [scripts/Makefile.build:243: scripts/mod/empty.o] Error 1
make[2]: *** Waiting for unfinished jobs....
cc1: error: '-march=rv64imac_zicsr_zifencei': unsupported ISA subset 'z'
cc1: error: ABI requires '-march=rv64'
arch/riscv/Kconfig | 32 +++++++++++++++-----------
arch/riscv/kernel/compat_vdso/Makefile | 8 ++++++-
2 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f52dd125ac5e..ce3a6667cfdb 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -570,24 +570,30 @@ config TOOLCHAIN_HAS_ZIHINTPAUSE
config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
def_bool y
# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
- depends on AS_IS_GNU && AS_VERSION >= 23800
- help
- Newer binutils versions default to ISA spec version 20191213 which
- moves some instructions from the I extension to the Zicsr and Zifencei
- extensions.
+ # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
+ depends on AS_IS_GNU && AS_VERSION >= 23600
+ help
+ Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer
+ 20191213 version, which moves some instructions from the I extension to
+ the Zicsr and Zifencei extensions. This requires explicitly specifying
+ Zicsr and Zifencei when binutils >= 2.38 or GCC >= 12.1.0. Zicsr
+ and Zifencei are supported in binutils from version 2.36 onwards.
+ To make life easier, and avoid forcing toolchains that default to a
+ newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
+ For clang < 17 or GCC < 11.1.0, for which this is not possible, this is
+ dealt with in CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
def_bool y
depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
# https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
- depends on CC_IS_CLANG && CLANG_VERSION < 170000
- help
- Certain versions of clang do not support zicsr and zifencei via -march
- but newer versions of binutils require it for the reasons noted in the
- help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This
- option causes an older ISA spec compatible with these older versions
- of clang to be passed to GAS, which has the same result as passing zicsr
- and zifencei to -march.
+ # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49
+ depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110100)
+ help
+ Certain versions of clang and GCC do not support zicsr and zifencei via
+ -march. This option causes an older ISA spec compatible with these older
+ versions of clang and GCC to be passed to GAS, which has the same result
+ as passing zicsr and zifencei to -march.
config FPU
bool "FPU support"
diff --git a/arch/riscv/kernel/compat_vdso/Makefile b/arch/riscv/kernel/compat_vdso/Makefile
index 189345773e7e..b86e5e2c3aea 100644
--- a/arch/riscv/kernel/compat_vdso/Makefile
+++ b/arch/riscv/kernel/compat_vdso/Makefile
@@ -11,7 +11,13 @@ compat_vdso-syms += flush_icache
COMPAT_CC := $(CC)
COMPAT_LD := $(LD)
-COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
+# binutils 2.35 does not support the zifencei extension, but in the ISA
+# spec 20191213, G stands for IMAFD_ZICSR_ZIFENCEI.
+ifdef CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
+ COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
+else
+ COMPAT_CC_FLAGS := -march=rv32imafd -mabi=ilp32
+endif
COMPAT_LD_FLAGS := -melf32lriscv
# Disable attributes, as they're useless and break the build.
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
2023-08-09 16:56 [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils Mingzheng Xing
@ 2023-08-17 15:20 ` patchwork-bot+linux-riscv
2023-08-23 11:51 ` Conor Dooley
0 siblings, 1 reply; 8+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-08-17 15:20 UTC (permalink / raw)
To: Mingzheng Xing
Cc: linux-riscv, conor, paul.walmsley, palmer, aou, nathan,
ndesaulniers, trix, bmeng, guoren, linux-kernel, llvm, stable,
conor.dooley
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 10 Aug 2023 00:56:48 +0800 you wrote:
> Binutils-2.38 and GCC-12.1.0 bumped[0][1] the default ISA spec to the newer
> 20191213 version which moves some instructions from the I extension to the
> Zicsr and Zifencei extensions. So if one of the binutils and GCC exceeds
> that version, we should explicitly specifying Zicsr and Zifencei via -march
> to cope with the new changes. but this only occurs when binutils >= 2.36
> and GCC >= 11.1.0. It's a different story when binutils < 2.36.
>
> [...]
Here is the summary with links:
- [v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
https://git.kernel.org/riscv/c/ca09f772ccca
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
2023-08-17 15:20 ` patchwork-bot+linux-riscv
@ 2023-08-23 11:51 ` Conor Dooley
[not found] ` <20230823-facelift-ovary-41f2eb4d9eac@spud>
0 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2023-08-23 11:51 UTC (permalink / raw)
To: patchwork-bot+linux-riscv
Cc: Mingzheng Xing, linux-riscv, conor, paul.walmsley, palmer, aou,
nathan, ndesaulniers, trix, bmeng, guoren, linux-kernel, llvm,
stable
[-- Attachment #1: Type: text/plain, Size: 1148 bytes --]
On Thu, Aug 17, 2023 at 03:20:24PM +0000, patchwork-bot+linux-riscv@kernel.org wrote:
> Hello:
>
> This patch was applied to riscv/linux.git (fixes)
> by Palmer Dabbelt <palmer@rivosinc.com>:
>
> On Thu, 10 Aug 2023 00:56:48 +0800 you wrote:
> > Binutils-2.38 and GCC-12.1.0 bumped[0][1] the default ISA spec to the newer
> > 20191213 version which moves some instructions from the I extension to the
> > Zicsr and Zifencei extensions. So if one of the binutils and GCC exceeds
> > that version, we should explicitly specifying Zicsr and Zifencei via -march
> > to cope with the new changes. but this only occurs when binutils >= 2.36
> > and GCC >= 11.1.0. It's a different story when binutils < 2.36.
> >
> > [...]
>
> Here is the summary with links:
> - [v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
> https://git.kernel.org/riscv/c/ca09f772ccca
*sigh* so this breaks the build for gcc-11 & binutils 2.37 w/
Assembler messages:
Error: cannot find default versions of the ISA extension `zicsr'
Error: cannot find default versions of the ISA extension `zifencei'
I'll have a poke later.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <20230824-cortex-mobilize-8b94e059e130@spud>]
* Re: [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
[not found] <20230824-cortex-mobilize-8b94e059e130@spud>
@ 2023-08-24 18:29 ` Palmer Dabbelt
2023-08-24 19:16 ` Mingzheng Xing
0 siblings, 1 reply; 8+ messages in thread
From: Palmer Dabbelt @ 2023-08-24 18:29 UTC (permalink / raw)
To: Conor Dooley
Cc: xingmingzheng, Conor Dooley, patchwork-bot+linux-riscv,
linux-riscv, Paul Walmsley, aou, nathan, ndesaulniers, trix,
bmeng, guoren, linux-kernel, llvm, stable
On Thu, 24 Aug 2023 11:05:13 PDT (-0700), Conor Dooley wrote:
> On Fri, Aug 25, 2023 at 01:46:59AM +0800, Mingzheng Xing wrote:
>
>> Just a question, I see that the previous patch has been merged
>> into 6.5-rc7, and now a new fix patch should be sent out based
>> on that, right?
>
> yes
Ideally ASAP, it's very late in the cycle. I have something for
tomorrow morning, but this will need time to test...
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils
2023-08-24 18:29 ` Palmer Dabbelt
@ 2023-08-24 19:16 ` Mingzheng Xing
0 siblings, 0 replies; 8+ messages in thread
From: Mingzheng Xing @ 2023-08-24 19:16 UTC (permalink / raw)
To: Palmer Dabbelt, Conor Dooley
Cc: Conor Dooley, patchwork-bot+linux-riscv, linux-riscv,
Paul Walmsley, aou, nathan, ndesaulniers, trix, bmeng, guoren,
linux-kernel, llvm, stable
On 8/25/23 02:29, Palmer Dabbelt wrote:
> On Thu, 24 Aug 2023 11:05:13 PDT (-0700), Conor Dooley wrote:
>> On Fri, Aug 25, 2023 at 01:46:59AM +0800, Mingzheng Xing wrote:
>>
>>> Just a question, I see that the previous patch has been merged
>>> into 6.5-rc7, and now a new fix patch should be sent out based
>>> on that, right?
>>
>> yes
>
> Ideally ASAP, it's very late in the cycle. I have something for
> tomorrow morning, but this will need time to test...
I sent a new patch here:
https://lore.kernel.org/all/20230824190852.45470-1-xingmingzheng@iscas.ac.cn
Best Regards,
Mingzheng.
^ permalink raw reply [flat|nested] 8+ messages in thread
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2023-08-09 16:56 [PATCH v5] riscv: Handle zicsr/zifencei issue between gcc and binutils Mingzheng Xing
2023-08-17 15:20 ` patchwork-bot+linux-riscv
2023-08-23 11:51 ` Conor Dooley
[not found] ` <20230823-facelift-ovary-41f2eb4d9eac@spud>
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