RE: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts

RE: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts

[Hongxing Zhu]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Thursday, April 30, 2026 6:49 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-
> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme
> interrupts
> 
> On 30/04/2026 10:37, Hongxing Zhu wrote:
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: Thursday, April 30, 2026 4:04 PM
> >> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> >> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> >> bhelgaas@google.com; Frank Li <frank.li@nxp.com>;
> >> l.stach@pengutronix.de; lpieralisi@kernel.org;
> >> kwilczynski@kernel.org; mani@kernel.org; s.hauer@pengutronix.de;
> >> kernel@pengutronix.de; festevam@gmail.com; linux-
> >> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >> devicetree@vger.kernel.org; imx@lists.linux.dev;
> >> linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr,
> >> aer and pme interrupts
> >>
> >> On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:
> >>> Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe
> >>> binding to support PCIe event-based interrupts for general
> >>> controller events, Advanced Error Reporting, and Power Management Events
> respectively.
> >>>
> >>> These interrupts are optional for existing variants (imx6q, imx6sx,
> >>> imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward
> >>> compatibility with existing device trees.
> >>>
> >>> For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are
> >>> mandatory due to hardware requirements.
> >>>
> >>> This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95
> >>> hardware requires dedicated interrupt lines for AER, PME, and
> >>> general controller events due to its redesigned interrupt
> >>> architecture. i.MX95 cannot function correctly without explicit
> >>> interrupt routing for error handling, power management and link event
> detection.
> >>
> >> fsl,imx95-pcie was added more than two years ago, so how it cannot
> >> function correctly? Are you saying that for two years you had here
> >> completely broken code?
> >>
> >> If this wasn't tested for two years, how can we believe anything is tested now?
> > The basic PCIe functionality has been working since the initial
> > fsl,imx95-pcie support. However, AER (Advanced Error Reporting) and
> > link up/down detection were not previously enabled. This patch-set
> > adds and verifies support for these advanced features.
> >
> 
> That is not what you said in the commit msg.
Hi Krzysztof:
Sorry for the delayed response due to a holiday.
After reviewing this patch-set again, I'd like to suggest an alternative
approach: would it be possible to mark these newly added interrupts as
optional?
This approach has several benefits.
  - The current implementation works correctly for basic PCIe operation with
    only MSI interrupt present.
  - It avoids introducing dt-binding check warnings, since dt-binding and dts
    changes are typically merged through different trees. The i.MX943 PCIe
    would also report dt-binding check warnings if these interrupts are not
    marked as optional.
  - AER, PME, and link event handling are optional features rather than
    mandatory requirements for basic PCIe functionality.

What do you think about this approach?

Best Regards
Richard Zhu
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts

[mani]

On Thu, May 07, 2026 at 08:04:22AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzk@kernel.org>
> > Sent: Thursday, April 30, 2026 6:49 PM
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > bhelgaas@google.com; Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-
> > pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme
> > interrupts
> > 
> > On 30/04/2026 10:37, Hongxing Zhu wrote:
> > >> -----Original Message-----
> > >> From: Krzysztof Kozlowski <krzk@kernel.org>
> > >> Sent: Thursday, April 30, 2026 4:04 PM
> > >> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > >> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > >> bhelgaas@google.com; Frank Li <frank.li@nxp.com>;
> > >> l.stach@pengutronix.de; lpieralisi@kernel.org;
> > >> kwilczynski@kernel.org; mani@kernel.org; s.hauer@pengutronix.de;
> > >> kernel@pengutronix.de; festevam@gmail.com; linux-
> > >> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > >> devicetree@vger.kernel.org; imx@lists.linux.dev;
> > >> linux-kernel@vger.kernel.org
> > >> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr,
> > >> aer and pme interrupts
> > >>
> > >> On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:
> > >>> Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe
> > >>> binding to support PCIe event-based interrupts for general
> > >>> controller events, Advanced Error Reporting, and Power Management Events
> > respectively.
> > >>>
> > >>> These interrupts are optional for existing variants (imx6q, imx6sx,
> > >>> imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward
> > >>> compatibility with existing device trees.
> > >>>
> > >>> For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are
> > >>> mandatory due to hardware requirements.
> > >>>
> > >>> This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95
> > >>> hardware requires dedicated interrupt lines for AER, PME, and
> > >>> general controller events due to its redesigned interrupt
> > >>> architecture. i.MX95 cannot function correctly without explicit
> > >>> interrupt routing for error handling, power management and link event
> > detection.
> > >>
> > >> fsl,imx95-pcie was added more than two years ago, so how it cannot
> > >> function correctly? Are you saying that for two years you had here
> > >> completely broken code?
> > >>
> > >> If this wasn't tested for two years, how can we believe anything is tested now?
> > > The basic PCIe functionality has been working since the initial
> > > fsl,imx95-pcie support. However, AER (Advanced Error Reporting) and
> > > link up/down detection were not previously enabled. This patch-set
> > > adds and verifies support for these advanced features.
> > >
> > 
> > That is not what you said in the commit msg.
> Hi Krzysztof:
> Sorry for the delayed response due to a holiday.
> After reviewing this patch-set again, I'd like to suggest an alternative
> approach: would it be possible to mark these newly added interrupts as
> optional?

Yes, since even without these interrupts, PCIe functionality still works. Only
issue is that it cannot report error and recover from LDn.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts

[Krzysztof Kozlowski]

On 12/05/2026 15:26, mani@kernel.org wrote:
>>>>>>
>>>>>> These interrupts are optional for existing variants (imx6q, imx6sx,
>>>>>> imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward
>>>>>> compatibility with existing device trees.
>>>>>>
>>>>>> For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are
>>>>>> mandatory due to hardware requirements.
>>>>>>
>>>>>> This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95
>>>>>> hardware requires dedicated interrupt lines for AER, PME, and
>>>>>> general controller events due to its redesigned interrupt
>>>>>> architecture. i.MX95 cannot function correctly without explicit
>>>>>> interrupt routing for error handling, power management and link event
>>> detection.
>>>>>
>>>>> fsl,imx95-pcie was added more than two years ago, so how it cannot
>>>>> function correctly? Are you saying that for two years you had here
>>>>> completely broken code?
>>>>>
>>>>> If this wasn't tested for two years, how can we believe anything is tested now?
>>>> The basic PCIe functionality has been working since the initial
>>>> fsl,imx95-pcie support. However, AER (Advanced Error Reporting) and
>>>> link up/down detection were not previously enabled. This patch-set
>>>> adds and verifies support for these advanced features.
>>>>
>>>
>>> That is not what you said in the commit msg.
>> Hi Krzysztof:
>> Sorry for the delayed response due to a holiday.
>> After reviewing this patch-set again, I'd like to suggest an alternative
>> approach: would it be possible to mark these newly added interrupts as
>> optional?
> 
> Yes, since even without these interrupts, PCIe functionality still works. Only
> issue is that it cannot report error and recover from LDn.

Yes. Please mention how the hardware or SW implementation behave when
these are missing, which is then serving as proof why they can be optional.

Best regards,
Krzysztof