[PATCH net-next v2 1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

[PATCH net-next v2 1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

[Oleksij Rempel]

From: Lucas Stach <l.stach@pengutronix.de>

On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
register offset.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
changes v2:
- add LAN9371 port 4 support
---
 drivers/net/dsa/microchip/ksz_common.h   | 1 +
 drivers/net/dsa/microchip/lan937x_main.c | 4 ++++
 drivers/net/dsa/microchip/lan937x_reg.h  | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index ee7db46e469d5..c4a4664c03859 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -22,6 +22,7 @@
 /* all KSZ switches count ports from 1 */
 #define KSZ_PORT_1 0
 #define KSZ_PORT_2 1
+#define KSZ_PORT_4 3
 
 struct ksz_device;
 struct ksz_port;
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index b479a628b1ae5..eaa862eb6b265 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -55,6 +55,10 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
 	u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
 	u16 temp;
 
+	if ((dev->info->chip_id == LAN9371_CHIP_ID ||
+	     dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4)
+		addr_base = REG_PORT_TX_PHY_CTRL_BASE;
+
 	/* get register address based on the logical port */
 	temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
 
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 45b606b6429f6..7ecada9240233 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -147,6 +147,7 @@
 
 /* 1 - Phy */
 #define REG_PORT_T1_PHY_CTRL_BASE	0x0100
+#define REG_PORT_TX_PHY_CTRL_BASE	0x0280
 
 /* 3 - xMII */
 #define PORT_SGMII_SEL			BIT(7)
-- 
2.39.2

[PATCH net-next v2 2/3] net: dsa: microchip: lan937x: disable in-band status support for RGMII interfaces

[Oleksij Rempel]

From: Lucas Stach <l.stach@pengutronix.de>

This driver do not support in-band mode and in case of CPU<->Switch
link, this mode is not working any way. So, disable it otherwise ingress
path of the switch MAC will stay disabled.

Note: lan9372 manual do not document 0xN301 BIT(2) for the RGMII mode
and recommend[1] to disable in-band link status update for the RGMII RX
path by clearing 0xN302 BIT(0). But, 0xN301 BIT(2) seems to work too, so
keep it unified with other KSZ switches.

[1] https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
changes v2:
- use ksz_set_xmii() instead of LAN937X specific code
---
 drivers/net/dsa/microchip/ksz_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index baa1eeb9a1b04..b074b4bb06296 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -3116,7 +3116,8 @@ static void ksz_set_xmii(struct ksz_device *dev, int port,
 		/* On KSZ9893, disable RGMII in-band status support */
 		if (dev->chip_id == KSZ9893_CHIP_ID ||
 		    dev->chip_id == KSZ8563_CHIP_ID ||
-		    dev->chip_id == KSZ9563_CHIP_ID)
+		    dev->chip_id == KSZ9563_CHIP_ID ||
+		    is_lan937x(dev))
 			data8 &= ~P_MII_MAC_MODE;
 		break;
 	default:
-- 
2.39.2

Re: [PATCH net-next v2 2/3] net: dsa: microchip: lan937x: disable in-band status support for RGMII interfaces

[Vladimir Oltean]

On Mon, Jul 01, 2024 at 10:53:42AM +0200, Oleksij Rempel wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This driver do not support in-band mode and in case of CPU<->Switch
> link, this mode is not working any way. So, disable it otherwise ingress
> path of the switch MAC will stay disabled.
> 
> Note: lan9372 manual do not document 0xN301 BIT(2) for the RGMII mode
> and recommend[1] to disable in-band link status update for the RGMII RX
> path by clearing 0xN302 BIT(0). But, 0xN301 BIT(2) seems to work too, so
> keep it unified with other KSZ switches.
> 
> [1] https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> changes v2:
> - use ksz_set_xmii() instead of LAN937X specific code
> ---

Reviewed-by: Vladimir Oltean <olteanv@gmail.com>

Re: [PATCH net-next v2 2/3] net: dsa: microchip: lan937x: disable in-band status support for RGMII interfaces

[Arun.Ramadoss]

Hi Oleksij,
On Mon, 2024-07-01 at 10:53 +0200, Oleksij Rempel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This driver do not support in-band mode and in case of CPU<->Switch
> link, this mode is not working any way. So, disable it otherwise
> ingress
> path of the switch MAC will stay disabled.
> 
> Note: lan9372 manual do not document 0xN301 BIT(2) for the RGMII mode
> and recommend[1] to disable in-band link status update for the RGMII
> RX
> path by clearing 0xN302 BIT(0).
>  But, 0xN301 BIT(2) seems to work too, so
> keep it unified with other KSZ switches.
> 
> [1] 
> https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

But If you want IBS to be enabled, then we need to set both the bit
0xN301 BIT(2) and 0xN302 BIT(0).

Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>

[PATCH net-next v2 3/3] net: dsa: microchip: lan937x: disable VPHY support

[Oleksij Rempel]

From: Lucas Stach <l.stach@pengutronix.de>

As described by the microchip article "LAN937X - The required
configuration for the external MAC port to operate at RGMII-to-RGMII
1Gbps link speed." [1]:

"When VPHY is enabled, the auto-negotiation process following IEEE 802.3
standard will be triggered and will result in RGMII-to-RGMII signal
failure on the interface because VPHY will try to poll the PHY status
that is not available in the scenario of RGMII-to-RGMII connection
(normally the link partner is usually an external processor).

Note that when VPHY fails on accessing PHY registers, it will fall back
to 100Mbps speed, it indicates disabling VPHY is optional if you only
need the port to link at 100Mbps speed.

Again, VPHY must and can only be disabled by writing VPHY_DISABLE bit in
the register below as there is no strapping pin for the control."

This patch was tested on LAN9372, so far it seems to not to affect VPHY
based clock crossing optimization for the ports with integrated PHYs.

[1]: https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
changes v2:
- reword the comment and link microchip article
---
 drivers/net/dsa/microchip/lan937x_main.c | 3 +++
 drivers/net/dsa/microchip/lan937x_reg.h  | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index eaa862eb6b265..0606796b14856 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -390,6 +390,9 @@ int lan937x_setup(struct dsa_switch *ds)
 	lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 		    (SW_CLK125_ENB | SW_CLK25_ENB), true);
 
+	/* Disable global VPHY support. Related to CPU interface only? */
+	ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, SW_VPHY_DISABLE);
+
 	return 0;
 }
 
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 7ecada9240233..2f22a9d01de36 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -37,6 +37,10 @@
 #define SW_CLK125_ENB			BIT(1)
 #define SW_CLK25_ENB			BIT(0)
 
+/* 2 - PHY Control */
+#define REG_SW_CFG_STRAP_OVR		0x0214
+#define SW_VPHY_DISABLE			BIT(31)
+
 /* 3 - Operation Control */
 #define REG_SW_OPERATION		0x0300
 
-- 
2.39.2

Re: [PATCH net-next v2 3/3] net: dsa: microchip: lan937x: disable VPHY support

[Vladimir Oltean]

On Mon, Jul 01, 2024 at 10:53:43AM +0200, Oleksij Rempel wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> As described by the microchip article "LAN937X - The required
> configuration for the external MAC port to operate at RGMII-to-RGMII
> 1Gbps link speed." [1]:
> 
> "When VPHY is enabled, the auto-negotiation process following IEEE 802.3
> standard will be triggered and will result in RGMII-to-RGMII signal
> failure on the interface because VPHY will try to poll the PHY status
> that is not available in the scenario of RGMII-to-RGMII connection
> (normally the link partner is usually an external processor).
> 
> Note that when VPHY fails on accessing PHY registers, it will fall back
> to 100Mbps speed, it indicates disabling VPHY is optional if you only
> need the port to link at 100Mbps speed.
> 
> Again, VPHY must and can only be disabled by writing VPHY_DISABLE bit in
> the register below as there is no strapping pin for the control."
> 
> This patch was tested on LAN9372, so far it seems to not to affect VPHY
> based clock crossing optimization for the ports with integrated PHYs.
> 
> [1]: https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> changes v2:
> - reword the comment and link microchip article
> ---

Reviewed-by: Vladimir Oltean <olteanv@gmail.com>

Re: [PATCH net-next v2 3/3] net: dsa: microchip: lan937x: disable VPHY support

[Arun.Ramadoss]

Hi Oleksij,


> ---
>  drivers/net/dsa/microchip/lan937x_main.c | 3 +++
>  drivers/net/dsa/microchip/lan937x_reg.h  | 4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c
> b/drivers/net/dsa/microchip/lan937x_main.c
> index eaa862eb6b265..0606796b14856 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -390,6 +390,9 @@ int lan937x_setup(struct dsa_switch *ds)
>         lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
>                     (SW_CLK125_ENB | SW_CLK25_ENB), true);
> 
> +       /* Disable global VPHY support. Related to CPU interface
> only? */
> +       ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE,
> SW_VPHY_DISABLE);

Do we need to check the return value of ksz_rmw32?

> +
>         return 0;
>  }
> 
> 

Re: [PATCH net-next v2 1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

[Arun.Ramadoss]

On Mon, 2024-07-01 at 10:53 +0200, Oleksij Rempel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
> instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
> register offset.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>

Re: [PATCH net-next v2 1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:

On Mon,  1 Jul 2024 10:53:41 +0200 you wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
> instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
> register offset.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> 
> [...]

Here is the summary with links:
  - [net-next,v2,1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support
    https://git.kernel.org/netdev/net-next/c/8d7330b3a9c6
  - [net-next,v2,2/3] net: dsa: microchip: lan937x: disable in-band status support for RGMII interfaces
    https://git.kernel.org/netdev/net-next/c/c3db39468a42
  - [net-next,v2,3/3] net: dsa: microchip: lan937x: disable VPHY support
    https://git.kernel.org/netdev/net-next/c/2e3ed20c17e7

You are awesome, thank you!
-- 
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