Re: [PATCH v3 1/2] dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping

Re: [PATCH v3 1/2] dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping

[Rob Herring (Arm)]

On Thu, 30 Apr 2026 16:41:56 +0000, Caleb James DeLisle wrote:
> In MIPS VEIC mode (Vectored External Interrupt Controller), the
> hardware stops directly dispatching CPU interrupts such as IPIs or CPU
> performance counters, and instead it communicates them to the external
> interrupt controller (the hardware described here) which prioritizes,
> renumbers, and integrates them with its own hardware interrupt pins.
> Interrupts from the external controller are then dispatched through a
> different method via a dispatch table. In effect, the external
> controller subsumes the CPU controller and becomes the root.
> 
> 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136
> 
> Since there are interrupts which ought to be controlled by the CPU
> controller driver - particularly the IPI interrupts - we create a
> reverse mapping where those interrupts may be sent back to the CPU
> intc when they are received. This maintains the fiction that there is
> still a hierarchy, and keeps the DT the same no matter whether the
> processor is in VEIC mode or not. The econet,cpu-interrupt-map is
> optional and if omitted, it's assumed that no interrupts need to be
> mapped.
> 
> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
> ---
>  .../econet,en751221-intc.yaml                 | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[tip: irq/drivers] dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping

[tip-bot2 for Caleb James DeLisle]

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     02bea6ff684b62c14d5c6eafaee752d24fe62352
Gitweb:        https://git.kernel.org/tip/02bea6ff684b62c14d5c6eafaee752d24fe62352
Author:        Caleb James DeLisle <cjd@cjdns.fr>
AuthorDate:    Thu, 30 Apr 2026 16:41:56 
Committer:     Thomas Gleixner <tglx@kernel.org>
CommitterDate: Mon, 11 May 2026 15:29:30 +02:00

dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping

In MIPS VEIC mode (Vectored External Interrupt Controller), the
hardware stops directly dispatching CPU interrupts such as IPIs or CPU
performance counters, and instead it communicates them to the external
interrupt controller (the hardware described here) which prioritizes,
renumbers, and integrates them with its own hardware interrupt pins.
Interrupts from the external controller are then dispatched through a
different method via a dispatch table. In effect, the external
controller subsumes the CPU controller and becomes the root.

34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136

Since there are interrupts which ought to be controlled by the CPU
controller driver - particularly the IPI interrupts - we create a
reverse mapping where those interrupts may be sent back to the CPU
intc when they are received. This maintains the fiction that there is
still a hierarchy, and keeps the DT the same no matter whether the
processor is in VEIC mode or not. The econet,cpu-interrupt-map is
optional and if omitted, it's assumed that no interrupts need to be
mapped.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr
---
 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
index 5536319..44c0978 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
@@ -52,6 +52,25 @@ properties:
         - description: primary per-CPU IRQ
         - description: shadow IRQ number
 
+  econet,cpu-interrupt-map:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    description:
+      When running in VEIC mode, the hardware re-routes interrupts from the
+      CPU interrupt controller core to the "external" interrupt controller
+      (this device). It then prioritizes them and sends them back to the CPU
+      along with its own interrupts. The CPU hardware handles interrupts using
+      a special dispatch table (the normal interrupt handler is not invoked).
+      In this interrupt controller, the CPU interrupts are renumbered as they
+      are merged with this controller's own hardware interrupts.
+
+      This is the inverse of an interrupt-map, mapping which interrupts from
+      this controller must be routed back to the CPU interrupt domain for
+      correct handling there.
+    items:
+      items:
+        - description: The interrupt number as received in this controller
+        - description: The interrupt number to be dispatched on the CPU intc
+
 required:
   - compatible
   - reg
@@ -74,5 +93,6 @@ examples:
         interrupts = <2>;
 
         econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
+        econet,cpu-interrupt-map = <7 0>, <8 1>;
     };
 ...