CONFIG_BLK_DEV_SL82C105 should not be PPC/ARM specific

CONFIG_BLK_DEV_SL82C105 should not be PPC/ARM specific

[Mark W. Eichin]

[1.] One line summary of the problem:    
CONFIG_BLK_DEV_SL82C105 should not be PPC/ARM specific

[2.] Full description of the problem/report:

kernel-source-2.4.9/drivers/ide/Config.in:
	 if [ "$CONFIG_PPC" = "y" -o "$CONFIG_ARM" = "y" ]; then
	    bool '    Winbond SL82c105 support' CONFIG_BLK_DEV_SL82C105
	 fi
The ALR Revolution 2XL dual-x86 (well, celeron) motherboard does, in
fact, use this controller:

00:02.0 IDE interface: Symphony Labs SL82c105 (rev 06) (prog-if 8a [Master SecP PriP])
        Flags: bus master, medium devsel, latency 64
        I/O ports at fcd0

and if I bludgeon the config so that it actually builds, it does work
(under 2.2, regrettably in pio-only mode, but I'll try 2.4.9 shortly)

W82C105: IDE controller on PCI bus 00 dev 10
W82C105: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0xfcd0-0xfcd7, BIOS settings: hda:pio, hdb:pio
SL82C105 command word: 5
IDE timing: 00001313, resetting to PIO0 timing
IDE control/status register: 08ff0801


[3.] Keywords (i.e., modules, networking, kernel):
kernel Config IDE block architecture x86

[4.] Kernel version (from /proc/version):
2.2.19, 2.4.9 (from inspection of source)

[5.] Output of Oops.. message (if applicable) with symbolic information 
     resolved (see Documentation/oops-tracing.txt)
n/a
[6.] A small shell script or example program which triggers the
     problem (if possible)
n/a
[7.] Environment
[7.1.] Software (add the output of the ver_linux script here)
[7.2.] Processor information (from /proc/cpuinfo):
[7.3.] Module information (from /proc/modules):
[7.4.] Loaded driver and hardware information (/proc/ioports, /proc/iomem)
[7.5.] PCI information ('lspci -vvv' as root)

00:02.0 IDE interface: Symphony Labs SL82c105 (rev 06) (prog-if 8a [Master SecP PriP])
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 2 min, 40 max, 64 set, cache line size 08
        Interrupt: pin A routed to IRQ 0
        Region 4: I/O ports at fcd0

[7.6.] SCSI information (from /proc/scsi/scsi)
[7.7.] Other information that might be relevant to the problem
       (please look in /proc and include all information that you
       think to be relevant):
[X.] Other notes, patches, fixes, workarounds:

The hedrick IDE backport doesn't change this either.

			_Mark_ <eichin@thok.org>
			The Herd Of Kittens

Re: CONFIG_BLK_DEV_SL82C105 should not be PPC/ARM specific

[Russell King]

[-- Attachment #1: Type: text/plain, Size: 512 bytes --]

On Thu, Sep 06, 2001 at 06:30:01PM -0400, Mark W. Eichin wrote:
> and if I bludgeon the config so that it actually builds, it does work
> (under 2.2, regrettably in pio-only mode, but I'll try 2.4.9 shortly)

Please report back when you've done your 2.4.9 testing; you might like
to apply the patch PaulM has been bouncing around here trying to get
Linus to accept.

--
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html


[-- Attachment #2: Type: message/rfc822, Size: 4203 bytes --]

From: Paul Mackerras <paulus@samba.org>
To: torvalds@transmeta.com, linux-kernel@vger.kernel.org
Cc: trini@kernel.crashing.org, benh@kernel.crashing.org
Subject: [PATCH] [RESEND] remove rubbish from sl82c105.c
Date: Mon, 3 Sep 2001 22:36:16 +1000 (EST)
Message-ID: <15251.31040.478167.658461@tango.paulus.ozlabs.org>

Currently, drivers/ide/sl82c105.c has two sets of code in it: some
good code done by Russell King, and some old rubbishy code.  Russell's
code is inside #ifdef CONFIG_ARCH_NETWINDER.  I tried Russell's code
on my Longtrail CHRP PPC box and it not only compiles and links ok
(which the old code doesn't), it also works just fine.

So the patch below takes out the CONFIG_ARCH_NETWINDER and the old
code, so we use Russell's code on all platforms.  I put this patch out
on linux-kernel a couple of weeks ago and no one has complained since.
The old code won't link at the moment anyway (it references
ide_special_settings which isn't exported from ide-pci.c).

Linus, please apply this patch to your tree.

Paul.

diff -urN linux/drivers/ide/sl82c105.c linuxppc_2_4/drivers/ide/sl82c105.c
--- linux/drivers/ide/sl82c105.c	Wed Jul  4 14:33:21 2001
+++ linuxppc_2_4/drivers/ide/sl82c105.c	Sun Jul 22 17:58:43 2001
@@ -28,7 +28,6 @@
 
 extern char *ide_xfer_verbose (byte xfer_rate);
 
-#ifdef CONFIG_ARCH_NETWINDER
 /*
  * Convert a PIO mode and cycle time to the required on/off
  * times for the interface.  This has protection against run-away
@@ -272,37 +271,4 @@
 {
 	hwif->tuneproc = tune_sl82c105;
 }
-
-#else
-
-unsigned int pci_init_sl82c105(struct pci_dev *dev, const char *msg)
-{
-	return ide_special_settings(dev, msg);
-}
-
-void dma_init_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
-{
-	ide_setup_dma(hwif, dma_base, 8);
-}
-
-void __init ide_init_sl82c105(ide_hwif_t *hwif)
-{
-	struct pci_dev *dev = hwif->pci_dev;
-	unsigned short t16;
-	unsigned int t32;
-	pci_read_config_word(dev, PCI_COMMAND, &t16);
-	printk("SL82C105 command word: %x\n",t16);
-        t16 |= PCI_COMMAND_IO;
-        pci_write_config_word(dev, PCI_COMMAND, t16);
-	/* IDE timing */
-	pci_read_config_dword(dev, 0x44, &t32);
-	printk("IDE timing: %08x, resetting to PIO0 timing\n",t32);
-	pci_write_config_dword(dev, 0x44, 0x03e4);
-#ifndef CONFIG_MBX
-	pci_read_config_dword(dev, 0x40, &t32);
-	printk("IDE control/status register: %08x\n",t32);
-	pci_write_config_dword(dev, 0x40, 0x10ff08a1);
-#endif /* CONFIG_MBX */
-}
-#endif

-
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Re: CONFIG_BLK_DEV_SL82C105 should not be PPC/ARM specific

[Mark Eichin]

That patch (plus bludgeoning the config) certainly *works* on this
chipset, but it doesn't get DMA support; logs follow.  If I run hdparm
to put it into using_dma mode, and then try to access it, using_dma
mode gets turned off after some delay...

Uniform Multi-Platform E-IDE driver Revision: 6.31
ide: Assuming 33MHz system bus speed for PIO modes; override with
idebus=xx
W82C105: IDE controller on PCI bus 00 dev 10
PCI: No IRQ known for interrupt pin A of device 00:02.0. Probably
buggy MP table.
W82C105: chipset revision 6
W82C105: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0xfcd0-0xfcd7, BIOS settings: hda:DMA, hdb:DMA
    ide1: BM-DMA at 0xfcd8-0xfcdf, BIOS settings: hdc:DMA, hdd:DMA
hda: Maxtor 4W100H6, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
hda: 195711264 sectors (100204 MB) w/2048KiB Cache, CHS=194158/16/63,
(U)DMA
 hda:hda: timeout waiting for DMA
ide_dmaproc: chipset supported ide_dma_timeout func only: 14
hda: timeout waiting for DMA
ide_dmaproc: chipset supported ide_dma_timeout func only: 14
hda: timeout waiting for DMA
ide_dmaproc: chipset supported ide_dma_timeout func only: 14
hda: timeout waiting for DMA
ide_dmaproc: chipset supported ide_dma_timeout func only: 14
LDM:  DEBUG (ldm.c, 876): validate_partition_table: Found basic MS-DOS
partition, not a 
dynamic disk.
 hda1 hda2

# hdparm -v  /dev/hda

/dev/hda:
 multcount    =  0 (off)
 I/O support  =  0 (default 16-bit)
 unmaskirq    =  1 (on)
 using_dma    =  1 (on)
 keepsettings =  0 (off)
 nowerr       =  0 (off)
 readonly     =  0 (off)
 readahead    =  8 (on)
 geometry     = 63086/16/63, sectors = 195711264, start = 0
# hdparm -t  /dev/hda

/dev/hda:
 Timing buffered disk reads:  64 MB in 57.65 seconds =  1.11 MB/sec
# hdparm -v  /dev/hda

/dev/hda:
 multcount    =  0 (off)
 I/O support  =  0 (default 16-bit)
 unmaskirq    =  1 (on)
 using_dma    =  0 (off)
 keepsettings =  0 (off)
 nowerr       =  0 (off)
 readonly     =  0 (off)
 readahead    =  8 (on)
 geometry     = 63086/16/63, sectors = 195711264, start = 0