Re: [PATCH] x86: Support always running TSC on Intel CPUs

[Venki Pallipadi <venkatesh.pallipadi@intel.com>]

On Mon, Nov 17, 2008 at 04:52:21PM -0800, H. Peter Anvin wrote:
> Venki Pallipadi wrote:
> > On Mon, Nov 17, 2008 at 04:18:16PM -0800, H. Peter Anvin wrote:
> >> Pallipadi, Venkatesh wrote:
> >>> All C-states higher than C1.
> >>>
> >> Including C2?  If so, the TSC is unusable since C2 can be invoked
> >> asynchronously by the chipset.
> >>
> >
> > No. Not on Intel CPUs atleast. On Intel CPUs, we enter C-states only on
> > hlt or mwait.  C1 is always C1 or C1E, where TSC always runs.
> > C2, C3, ... implementation vary depending on processor and TSC may or may
> > not run. This 0x80000007 feature bit basically says TSC is going to run
> > during any C-state.
> >
> 
> I was under the impression that C2 was invoked by the chipset on a
> thermal condition, at least on older (P3-era) processors.  Is that no
> longer true?  If what you say is above (HLT and MWAIT only), then *was*
> it ever true?

I should also add io port based C-state to HLT and MWAIT. But, that again is
OS initiated.

I don't know of C2 invocation in thermal condition. Thermal condition, all
CPUs that I know of (P3 and beyond), use either clock modulation or frequency
changes. And on some such CPUs, where TSC runs at constant freq during such
modulation/freq change, we set CONSTANT_TSC bit based on model number check.
So, on CPUs earlier than those, we cannot use TSC or we have to scale TSC
based on freq. This patch shouldn't have any impact for those CPUs.

Thanks,
Venki