* [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-29 11:00 ` Russell King - ARM Linux
2009-01-28 19:18 ` [PATCH D 02/11] OMAP2/3 clock: clean up mach-omap2/clock.c Paul Walmsley
` (9 subsequent siblings)
10 siblings, 1 reply; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: linux-omap, MånsRullgård, Paul Walmsley, Tony Lindgren
From: Mans Rullgard <mans@mansr.com>
This makes clk_get_parent() work on OMAP2/3.
linux-omap source commit is efd65273726b12e42c7225bd1703e5252bdb46c0.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 5 +++++
arch/arm/mach-omap2/clock.h | 1 +
arch/arm/mach-omap2/clock24xx.c | 1 +
arch/arm/mach-omap2/clock34xx.c | 1 +
4 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e57694f..9957813 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -870,6 +870,11 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
return 0;
}
+struct clk *omap2_clk_get_parent(struct clk *clk)
+{
+ return clk->parent;
+}
+
/* DPLL rate rounding code */
/**
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 72bb320..4dbd582 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -44,6 +44,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+struct clk *omap2_clk_get_parent(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index a2c13ef..2398711 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -436,6 +436,7 @@ static struct clk_functions omap2_clk_functions = {
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
+ .clk_get_parent = omap2_clk_get_parent,
.clk_disable_unused = omap2_clk_disable_unused,
#ifdef CONFIG_CPU_FREQ
.clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 33d5a51..0c8d88e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -565,6 +565,7 @@ static struct clk_functions omap2_clk_functions = {
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
+ .clk_get_parent = omap2_clk_get_parent,
.clk_disable_unused = omap2_clk_disable_unused,
};
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-28 19:18 ` [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3 Paul Walmsley
@ 2009-01-29 11:00 ` Russell King - ARM Linux
2009-01-30 6:29 ` Paul Walmsley
0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-01-29 11:00 UTC (permalink / raw)
To: Paul Walmsley
Cc: linux-arm-kernel, linux-kernel, linux-omap,
MånsRullgård, Tony Lindgren
On Wed, Jan 28, 2009 at 12:18:16PM -0700, Paul Walmsley wrote:
> From: Mans Rullgard <mans@mansr.com>
>
> This makes clk_get_parent() work on OMAP2/3.
This is clearly something that the generic code should be doing.
It's not something specific to OMAP2/3. Please move it to
arch/arm/plat-omap/clock.c
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-29 11:00 ` Russell King - ARM Linux
@ 2009-01-30 6:29 ` Paul Walmsley
2009-01-31 14:23 ` Russell King - ARM Linux
0 siblings, 1 reply; 25+ messages in thread
From: Paul Walmsley @ 2009-01-30 6:29 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel, linux-kernel, linux-omap,
Måns Rullgård, Tony Lindgren
[-- Attachment #1: Type: TEXT/PLAIN, Size: 2236 bytes --]
On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
> On Wed, Jan 28, 2009 at 12:18:16PM -0700, Paul Walmsley wrote:
> > From: Mans Rullgard <mans@mansr.com>
> >
> > This makes clk_get_parent() work on OMAP2/3.
>
> This is clearly something that the generic code should be doing.
> It's not something specific to OMAP2/3. Please move it to
> arch/arm/plat-omap/clock.c
Done; revised patch below.
- Paul
From: Mans Rullgard <mans@mansr.com>
Date: Thu Jan 29 23:26:35 2009 -0700
OMAP: Add clk_get_parent() for OMAP1/2/3
This makes clk_get_parent() work on OMAP.
linux-omap source commit is efd65273726b12e42c7225bd1703e5252bdb46c0.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: per rmk, made this function available on all OMAPs
and fixated its implementation]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index be6aab9..eb59874 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -210,18 +210,7 @@ EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
- unsigned long flags;
- struct clk * ret = NULL;
-
- if (clk == NULL || IS_ERR(clk))
- return ret;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- if (arch_clock->clk_get_parent)
- ret = arch_clock->clk_get_parent(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
+ return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f6adf39..47c9a11 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -104,7 +104,6 @@ struct clk_functions {
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
int (*clk_set_rate)(struct clk *clk, unsigned long rate);
int (*clk_set_parent)(struct clk *clk, struct clk *parent);
- struct clk * (*clk_get_parent)(struct clk *clk);
void (*clk_allow_idle)(struct clk *clk);
void (*clk_deny_idle)(struct clk *clk);
void (*clk_disable_unused)(struct clk *clk);
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-30 6:29 ` Paul Walmsley
@ 2009-01-31 14:23 ` Russell King - ARM Linux
2009-01-31 15:07 ` Måns Rullgård
0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-01-31 14:23 UTC (permalink / raw)
To: Paul Walmsley
Cc: linux-arm-kernel, linux-kernel, linux-omap,
Måns Rullgård, Tony Lindgren
On Thu, Jan 29, 2009 at 11:29:31PM -0700, Paul Walmsley wrote:
> On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
>
> > On Wed, Jan 28, 2009 at 12:18:16PM -0700, Paul Walmsley wrote:
> > > From: Mans Rullgard <mans@mansr.com>
> > >
> > > This makes clk_get_parent() work on OMAP2/3.
> >
> > This is clearly something that the generic code should be doing.
> > It's not something specific to OMAP2/3. Please move it to
> > arch/arm/plat-omap/clock.c
>
> Done; revised patch below.
Great, thanks. However, I'd forgotten that one of my patches completely
removes clk_get_parent() since it's unused by any code in OMAP at present.
What was the reasoning behind making this work?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-31 14:23 ` Russell King - ARM Linux
@ 2009-01-31 15:07 ` Måns Rullgård
2009-01-31 15:26 ` Russell King - ARM Linux
0 siblings, 1 reply; 25+ messages in thread
From: Måns Rullgård @ 2009-01-31 15:07 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Paul Walmsley, linux-arm-kernel, linux-kernel, linux-omap,
Måns Rullgård, Tony Lindgren
Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> On Thu, Jan 29, 2009 at 11:29:31PM -0700, Paul Walmsley wrote:
>> On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
>>
>> > On Wed, Jan 28, 2009 at 12:18:16PM -0700, Paul Walmsley wrote:
>> > > From: Mans Rullgard <mans@mansr.com>
>> > >
>> > > This makes clk_get_parent() work on OMAP2/3.
>> >
>> > This is clearly something that the generic code should be doing.
>> > It's not something specific to OMAP2/3. Please move it to
>> > arch/arm/plat-omap/clock.c
>>
>> Done; revised patch below.
>
> Great, thanks. However, I'd forgotten that one of my patches completely
> removes clk_get_parent() since it's unused by any code in OMAP at present.
>
> What was the reasoning behind making this work?
It is needed for the omapfb/dss driver to set an optimal rate for
dpll4_m4_ck.
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-31 15:07 ` Måns Rullgård
@ 2009-01-31 15:26 ` Russell King - ARM Linux
2009-01-31 15:39 ` Måns Rullgård
0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-01-31 15:26 UTC (permalink / raw)
To: Måns Rullgård
Cc: Paul Walmsley, linux-arm-kernel, linux-kernel, linux-omap,
Tony Lindgren
On Sat, Jan 31, 2009 at 03:07:06PM +0000, Måns Rullgård wrote:
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> > Great, thanks. However, I'd forgotten that one of my patches completely
> > removes clk_get_parent() since it's unused by any code in OMAP at present.
> >
> > What was the reasoning behind making this work?
>
> It is needed for the omapfb/dss driver to set an optimal rate for
> dpll4_m4_ck.
I assume this isn't merged yet? Where can I see what it's doing?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-31 15:26 ` Russell King - ARM Linux
@ 2009-01-31 15:39 ` Måns Rullgård
2009-01-31 15:56 ` Russell King - ARM Linux
0 siblings, 1 reply; 25+ messages in thread
From: Måns Rullgård @ 2009-01-31 15:39 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Måns Rullgård, Paul Walmsley, linux-arm-kernel,
linux-kernel, linux-omap, Tony Lindgren, Tomi Valkeinen
Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> On Sat, Jan 31, 2009 at 03:07:06PM +0000, Måns Rullgård wrote:
>> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>> > Great, thanks. However, I'd forgotten that one of my patches completely
>> > removes clk_get_parent() since it's unused by any code in OMAP at present.
>> >
>> > What was the reasoning behind making this work?
>>
>> It is needed for the omapfb/dss driver to set an optimal rate for
>> dpll4_m4_ck.
>
> I assume this isn't merged yet? Where can I see what it's doing?
The new DSS driver by Tomi Valkeinen uses it. Patches have been
posted to the linux-omap list.
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-31 15:39 ` Måns Rullgård
@ 2009-01-31 15:56 ` Russell King - ARM Linux
2009-01-31 16:51 ` Måns Rullgård
0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-01-31 15:56 UTC (permalink / raw)
To: Måns Rullgård
Cc: Paul Walmsley, linux-arm-kernel, linux-kernel, linux-omap,
Tony Lindgren, Tomi Valkeinen
On Sat, Jan 31, 2009 at 03:39:07PM +0000, Måns Rullgård wrote:
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>
> > On Sat, Jan 31, 2009 at 03:07:06PM +0000, Måns Rullgård wrote:
> >> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> >> > Great, thanks. However, I'd forgotten that one of my patches completely
> >> > removes clk_get_parent() since it's unused by any code in OMAP at present.
> >> >
> >> > What was the reasoning behind making this work?
> >>
> >> It is needed for the omapfb/dss driver to set an optimal rate for
> >> dpll4_m4_ck.
> >
> > I assume this isn't merged yet? Where can I see what it's doing?
>
> The new DSS driver by Tomi Valkeinen uses it. Patches have been
> posted to the linux-omap list.
Can't find them. Found the DSS patches posted on the 12th but they don't
use clk_get_parent().
So, I repeat. Where can I see where this function is used?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3
2009-01-31 15:56 ` Russell King - ARM Linux
@ 2009-01-31 16:51 ` Måns Rullgård
0 siblings, 0 replies; 25+ messages in thread
From: Måns Rullgård @ 2009-01-31 16:51 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Måns Rullgård, Paul Walmsley, linux-arm-kernel,
linux-kernel, linux-omap, Tony Lindgren, Tomi Valkeinen
Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
> On Sat, Jan 31, 2009 at 03:39:07PM +0000, Måns Rullgård wrote:
>> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>>
>> > On Sat, Jan 31, 2009 at 03:07:06PM +0000, Måns Rullgård wrote:
>> >> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>> >> > Great, thanks. However, I'd forgotten that one of my patches
>> >> > completely removes clk_get_parent() since it's unused by any
>> >> > code in OMAP at present.
>> >> >
>> >> > What was the reasoning behind making this work?
>> >>
>> >> It is needed for the omapfb/dss driver to set an optimal rate for
>> >> dpll4_m4_ck.
>> >
>> > I assume this isn't merged yet? Where can I see what it's doing?
>>
>> The new DSS driver by Tomi Valkeinen uses it. Patches have been
>> posted to the linux-omap list.
>
> Can't find them. Found the DSS patches posted on the 12th but they don't
> use clk_get_parent().
>
> So, I repeat. Where can I see where this function is used?
I have the patches applied in my git tree:
http://git.mansr.com/?p=linux-omap;a=blob;f=arch/arm/plat-omap/dss/dispc.c;h=e6954637b113c66cb6a0ee8c7c4c3993d170b4a3;hb=HEAD#l1494
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH D 02/11] OMAP2/3 clock: clean up mach-omap2/clock.c
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
2009-01-28 19:18 ` [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3 Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 03/11] OMAP2 PRCM: clean up CM_IDLEST bits Paul Walmsley
` (8 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
This patch rolls up several cleanup patches.
1. Some unnecessarily verbose variable names are used in several clock.c
functions; clean these up per CodingStyle.
2. Remove omap2_get_clksel() and just use clk->clksel_reg and
clk->clksel_mask directly.
3. Get rid of void __iomem * usage in omap2_clksel_get_src_field.
Prepend the function name with an underscore to highlight that it is a
static function.
linux-omap source commits are 7fa95e007ea2f3c4d0ecd2779d809756e7775894,
af0ea23f1ee4a5bea3b026e38761b47089f9048a, and
91c0c979b47c44b08f80e4f8d4c990fb158d82c4.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 99 +++++++++++++++----------------------------
1 files changed, 35 insertions(+), 64 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 9957813..185e1b7 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -357,7 +357,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
*/
static int _omap2_clk_enable(struct clk *clk)
{
- u32 regval32;
+ u32 v;
if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
return 0;
@@ -371,12 +371,12 @@ static int _omap2_clk_enable(struct clk *clk)
return 0; /* REVISIT: -EINVAL */
}
- regval32 = __raw_readl(clk->enable_reg);
+ v = __raw_readl(clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
- regval32 &= ~(1 << clk->enable_bit);
+ v &= ~(1 << clk->enable_bit);
else
- regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ v |= (1 << clk->enable_bit);
+ __raw_writel(v, clk->enable_reg);
wmb();
omap2_clk_wait_ready(clk);
@@ -387,7 +387,7 @@ static int _omap2_clk_enable(struct clk *clk)
/* Disables clock without considering parent dependencies or use count */
static void _omap2_clk_disable(struct clk *clk)
{
- u32 regval32;
+ u32 v;
if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
return;
@@ -407,12 +407,12 @@ static void _omap2_clk_disable(struct clk *clk)
return;
}
- regval32 = __raw_readl(clk->enable_reg);
+ v = __raw_readl(clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
- regval32 |= (1 << clk->enable_bit);
+ v |= (1 << clk->enable_bit);
else
- regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ v &= ~(1 << clk->enable_bit);
+ __raw_writel(v, clk->enable_reg);
wmb();
}
@@ -683,23 +683,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
}
/**
- * omap2_get_clksel - find clksel register addr & field mask for a clk
- * @clk: struct clk to use
- * @field_mask: ptr to u32 to store the register field mask
- *
- * Returns the address of the clksel register upon success or NULL on error.
- */
-static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
-{
- if (!clk->clksel_reg || (clk->clksel_mask == 0))
- return NULL;
-
- *field_mask = clk->clksel_mask;
-
- return clk->clksel_reg;
-}
-
-/**
* omap2_clksel_get_divisor - get current divider applied to parent clock.
* @clk: OMAP struct clk to use.
*
@@ -707,41 +690,36 @@ static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
*/
u32 omap2_clksel_get_divisor(struct clk *clk)
{
- u32 field_mask, field_val;
- void __iomem *div_addr;
+ u32 v;
- div_addr = omap2_get_clksel(clk, &field_mask);
- if (!div_addr)
+ if (!clk->clksel_mask)
return 0;
- field_val = __raw_readl(div_addr) & field_mask;
- field_val >>= __ffs(field_mask);
+ v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ v >>= __ffs(clk->clksel_mask);
- return omap2_clksel_to_divisor(clk, field_val);
+ return omap2_clksel_to_divisor(clk, v);
}
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
{
- u32 field_mask, field_val, validrate, new_div = 0;
- void __iomem *div_addr;
- u32 v;
+ u32 v, field_val, validrate, new_div = 0;
- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
- if (validrate != rate)
+ if (!clk->clksel_mask)
return -EINVAL;
- div_addr = omap2_get_clksel(clk, &field_mask);
- if (!div_addr)
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
return -EINVAL;
field_val = omap2_divisor_to_clksel(clk, new_div);
if (field_val == ~0)
return -EINVAL;
- v = __raw_readl(div_addr);
- v &= ~field_mask;
- v |= field_val << __ffs(field_mask);
- __raw_writel(v, div_addr);
+ v = __raw_readl(clk->clksel_reg);
+ v &= ~clk->clksel_mask;
+ v |= field_val << __ffs(clk->clksel_mask);
+ __raw_writel(v, clk->clksel_reg);
wmb();
@@ -781,18 +759,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
/*
* Converts encoded control register address into a full address
- * On error, *src_addr will be returned as 0.
+ * On error, the return value (parent_div) will be 0.
*/
-static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
- struct clk *src_clk, u32 *field_mask,
- struct clk *clk, u32 *parent_div)
+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
+ u32 *field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
- *parent_div = 0;
- *src_addr = NULL;
-
clks = omap2_get_clksel_by_parent(clk, src_clk);
if (!clks)
return 0;
@@ -812,17 +786,14 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
/* Should never happen. Add a clksel mask to the struct clk. */
WARN_ON(clk->clksel_mask == 0);
- *field_mask = clk->clksel_mask;
- *src_addr = clk->clksel_reg;
- *parent_div = clkr->div;
+ *field_val = clkr->val;
- return clkr->val;
+ return clkr->div;
}
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
- void __iomem *src_addr;
- u32 field_val, field_mask, reg_val, parent_div;
+ u32 field_val, v, parent_div;
if (clk->flags & CONFIG_PARTICIPANT)
return -EINVAL;
@@ -830,18 +801,18 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
if (!clk->clksel)
return -EINVAL;
- field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
- &field_mask, clk, &parent_div);
- if (!src_addr)
+ parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+ if (!parent_div)
return -EINVAL;
if (clk->usecount > 0)
_omap2_clk_disable(clk);
/* Set new source value (previous dividers if any in effect) */
- reg_val = __raw_readl(src_addr) & ~field_mask;
- reg_val |= (field_val << __ffs(field_mask));
- __raw_writel(reg_val, src_addr);
+ v = __raw_readl(clk->clksel_reg);
+ v &= ~clk->clksel_mask;
+ v |= field_val << __ffs(clk->clksel_mask);
+ __raw_writel(v, clk->clksel_reg);
wmb();
if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 03/11] OMAP2 PRCM: clean up CM_IDLEST bits
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
2009-01-28 19:18 ` [PATCH D 01/11] OMAP: Add clk_get_parent() for OMAP2/3 Paul Walmsley
2009-01-28 19:18 ` [PATCH D 02/11] OMAP2/3 clock: clean up mach-omap2/clock.c Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 04/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
` (7 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly
marked as being OMAP2xxx-wide, when they were actually 2420-specific.
Also, originally when the PRCM register macros were defined, bit shift
macros used a "_SHIFT" suffix, and mask macros used none. This became
a source of bugs and confusion, as the mask macros were mistakenly
used for shift values. Gradually, the mask macros have been updated,
piece by piece, to add a "_MASK" suffix on the end to clarify. This
patch applies this change to the CM_IDLEST_* register bits.
The patch also adds a few bits that were missing, mostly from the 3430ES1
to ES2 revisions.
linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77,
e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of
9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/cm-regbits-24xx.h | 80 +++++++++----
arch/arm/mach-omap2/cm-regbits-34xx.h | 96 ++++++++++++----
arch/arm/mach-omap2/prcm-common.h | 198 ++++++++++++++++++++++-----------
3 files changed, 257 insertions(+), 117 deletions(-)
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 1098ecf..297a2fe 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -110,35 +110,56 @@
#define OMAP24XX_EN_DES (1 << 0)
/* CM_IDLEST1_CORE specific bits */
-#define OMAP24XX_ST_MAILBOXES (1 << 30)
-#define OMAP24XX_ST_WDT4 (1 << 29)
-#define OMAP2420_ST_WDT3 (1 << 28)
-#define OMAP24XX_ST_MSPRO (1 << 27)
-#define OMAP24XX_ST_FAC (1 << 25)
-#define OMAP2420_ST_EAC (1 << 24)
-#define OMAP24XX_ST_HDQ (1 << 23)
-#define OMAP24XX_ST_I2C2 (1 << 20)
-#define OMAP24XX_ST_I2C1 (1 << 19)
-#define OMAP24XX_ST_MCBSP2 (1 << 16)
-#define OMAP24XX_ST_MCBSP1 (1 << 15)
-#define OMAP24XX_ST_DSS (1 << 0)
+#define OMAP24XX_ST_MAILBOXES_SHIFT 30
+#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
+#define OMAP24XX_ST_WDT4_SHIFT 29
+#define OMAP24XX_ST_WDT4_MASK (1 << 29)
+#define OMAP2420_ST_WDT3_SHIFT 28
+#define OMAP2420_ST_WDT3_MASK (1 << 28)
+#define OMAP24XX_ST_MSPRO_SHIFT 27
+#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
+#define OMAP24XX_ST_FAC_SHIFT 25
+#define OMAP24XX_ST_FAC_MASK (1 << 25)
+#define OMAP2420_ST_EAC_SHIFT 24
+#define OMAP2420_ST_EAC_MASK (1 << 24)
+#define OMAP24XX_ST_HDQ_SHIFT 23
+#define OMAP24XX_ST_HDQ_MASK (1 << 23)
+#define OMAP2420_ST_I2C2_SHIFT 20
+#define OMAP2420_ST_I2C2_MASK (1 << 20)
+#define OMAP2420_ST_I2C1_SHIFT 19
+#define OMAP2420_ST_I2C1_MASK (1 << 19)
+#define OMAP24XX_ST_MCBSP2_SHIFT 16
+#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
+#define OMAP24XX_ST_MCBSP1_SHIFT 15
+#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
+#define OMAP24XX_ST_DSS_SHIFT 0
+#define OMAP24XX_ST_DSS_MASK (1 << 0)
/* CM_IDLEST2_CORE */
-#define OMAP2430_ST_MCBSP5 (1 << 5)
-#define OMAP2430_ST_MCBSP4 (1 << 4)
-#define OMAP2430_ST_MCBSP3 (1 << 3)
-#define OMAP24XX_ST_SSI (1 << 1)
+#define OMAP2430_ST_MCBSP5_SHIFT 5
+#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
+#define OMAP2430_ST_MCBSP4_SHIFT 4
+#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
+#define OMAP2430_ST_MCBSP3_SHIFT 3
+#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
+#define OMAP24XX_ST_SSI_SHIFT 1
+#define OMAP24XX_ST_SSI_MASK (1 << 1)
/* CM_IDLEST3_CORE */
/* 2430 only */
-#define OMAP2430_ST_SDRC (1 << 2)
+#define OMAP2430_ST_SDRC_MASK (1 << 2)
/* CM_IDLEST4_CORE */
-#define OMAP24XX_ST_PKA (1 << 4)
-#define OMAP24XX_ST_AES (1 << 3)
-#define OMAP24XX_ST_RNG (1 << 2)
-#define OMAP24XX_ST_SHA (1 << 1)
-#define OMAP24XX_ST_DES (1 << 0)
+#define OMAP24XX_ST_PKA_SHIFT 4
+#define OMAP24XX_ST_PKA_MASK (1 << 4)
+#define OMAP24XX_ST_AES_SHIFT 3
+#define OMAP24XX_ST_AES_MASK (1 << 3)
+#define OMAP24XX_ST_RNG_SHIFT 2
+#define OMAP24XX_ST_RNG_MASK (1 << 2)
+#define OMAP24XX_ST_SHA_SHIFT 1
+#define OMAP24XX_ST_SHA_MASK (1 << 1)
+#define OMAP24XX_ST_DES_SHIFT 0
+#define OMAP24XX_ST_DES_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP24XX_AUTO_CAM (1 << 31)
@@ -275,11 +296,16 @@
#define OMAP24XX_EN_32KSYNC (1 << 1)
/* CM_IDLEST_WKUP specific bits */
-#define OMAP2430_ST_ICR (1 << 6)
-#define OMAP24XX_ST_OMAPCTRL (1 << 5)
-#define OMAP24XX_ST_WDT1 (1 << 4)
-#define OMAP24XX_ST_MPU_WDT (1 << 3)
-#define OMAP24XX_ST_32KSYNC (1 << 1)
+#define OMAP2430_ST_ICR_SHIFT 6
+#define OMAP2430_ST_ICR_MASK (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
+#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
+#define OMAP24XX_ST_WDT1_SHIFT 4
+#define OMAP24XX_ST_WDT1_MASK (1 << 4)
+#define OMAP24XX_ST_MPU_WDT_SHIFT 3
+#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
+#define OMAP24XX_ST_32KSYNC_SHIFT 1
+#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
/* CM_AUTOIDLE_WKUP */
#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 844356c..6f3f5a3 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -183,29 +183,52 @@
#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
-#define OMAP3430_ST_ICR (1 << 29)
-#define OMAP3430_ST_AES2 (1 << 28)
-#define OMAP3430_ST_SHA12 (1 << 27)
-#define OMAP3430_ST_DES2 (1 << 26)
-#define OMAP3430_ST_MSPRO (1 << 23)
-#define OMAP3430_ST_HDQ (1 << 22)
-#define OMAP3430ES1_ST_FAC (1 << 8)
-#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
-#define OMAP3430_ST_OMAPCTRL (1 << 6)
-#define OMAP3430_ST_SDMA (1 << 2)
-#define OMAP3430_ST_SDRC (1 << 1)
-#define OMAP3430_ST_SSI (1 << 0)
+#define OMAP3430ES2_ST_MMC3_SHIFT 30
+#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
+#define OMAP3430_ST_ICR_SHIFT 29
+#define OMAP3430_ST_ICR_MASK (1 << 29)
+#define OMAP3430_ST_AES2_SHIFT 28
+#define OMAP3430_ST_AES2_MASK (1 << 28)
+#define OMAP3430_ST_SHA12_SHIFT 27
+#define OMAP3430_ST_SHA12_MASK (1 << 27)
+#define OMAP3430_ST_DES2_SHIFT 26
+#define OMAP3430_ST_DES2_MASK (1 << 26)
+#define OMAP3430_ST_MSPRO_SHIFT 23
+#define OMAP3430_ST_MSPRO_MASK (1 << 23)
+#define OMAP3430_ST_HDQ_SHIFT 22
+#define OMAP3430_ST_HDQ_MASK (1 << 22)
+#define OMAP3430ES1_ST_FAC_SHIFT 8
+#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
+#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
+#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
+#define OMAP3430_ST_MAILBOXES_SHIFT 7
+#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
+#define OMAP3430_ST_OMAPCTRL_SHIFT 6
+#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
+#define OMAP3430_ST_SDMA_SHIFT 2
+#define OMAP3430_ST_SDMA_MASK (1 << 2)
+#define OMAP3430_ST_SDRC_SHIFT 1
+#define OMAP3430_ST_SDRC_MASK (1 << 1)
+#define OMAP3430_ST_SSI_STDBY_SHIFT 0
+#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
/* CM_IDLEST2_CORE */
-#define OMAP3430_ST_PKA (1 << 4)
-#define OMAP3430_ST_AES1 (1 << 3)
-#define OMAP3430_ST_RNG (1 << 2)
-#define OMAP3430_ST_SHA11 (1 << 1)
-#define OMAP3430_ST_DES1 (1 << 0)
+#define OMAP3430_ST_PKA_SHIFT 4
+#define OMAP3430_ST_PKA_MASK (1 << 4)
+#define OMAP3430_ST_AES1_SHIFT 3
+#define OMAP3430_ST_AES1_MASK (1 << 3)
+#define OMAP3430_ST_RNG_SHIFT 2
+#define OMAP3430_ST_RNG_MASK (1 << 2)
+#define OMAP3430_ST_SHA11_SHIFT 1
+#define OMAP3430_ST_SHA11_MASK (1 << 1)
+#define OMAP3430_ST_DES1_SHIFT 0
+#define OMAP3430_ST_DES1_MASK (1 << 0)
/* CM_IDLEST3_CORE */
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
+#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
+#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP3430ES2_AUTO_MMC3 (1 << 30)
@@ -360,6 +383,7 @@
/* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
+#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
/* CM_ICLKEN_WKUP specific bits */
#define OMAP3430_EN_WDT1 (1 << 4)
@@ -368,11 +392,18 @@
#define OMAP3430_EN_32KSYNC_SHIFT 2
/* CM_IDLEST_WKUP specific bits */
-#define OMAP3430_ST_WDT2 (1 << 5)
-#define OMAP3430_ST_WDT1 (1 << 4)
-#define OMAP3430_ST_32KSYNC (1 << 2)
+#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
+#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
+#define OMAP3430_ST_WDT2_SHIFT 5
+#define OMAP3430_ST_WDT2_MASK (1 << 5)
+#define OMAP3430_ST_WDT1_SHIFT 4
+#define OMAP3430_ST_WDT1_MASK (1 << 4)
+#define OMAP3430_ST_32KSYNC_SHIFT 2
+#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
/* CM_AUTOIDLE_WKUP */
+#define OMAP3430ES2_AUTO_USIMOCP (1 << 9)
+#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
#define OMAP3430_AUTO_WDT2 (1 << 5)
#define OMAP3430_AUTO_WDT2_SHIFT 5
#define OMAP3430_AUTO_WDT1 (1 << 4)
@@ -437,6 +468,8 @@
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
+#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
@@ -508,7 +541,12 @@
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
/* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS (1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
+#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
+#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
+#define OMAP3430ES1_ST_DSS_SHIFT 0
+#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
/* CM_AUTOIDLE_DSS */
#define OMAP3430_AUTO_DSS (1 << 0)
@@ -562,10 +600,14 @@
/* CM_ICLKEN_PER specific bits */
/* CM_IDLEST_PER */
-#define OMAP3430_ST_WDT3 (1 << 12)
-#define OMAP3430_ST_MCBSP4 (1 << 2)
-#define OMAP3430_ST_MCBSP3 (1 << 1)
-#define OMAP3430_ST_MCBSP2 (1 << 0)
+#define OMAP3430_ST_WDT3_SHIFT 12
+#define OMAP3430_ST_WDT3_MASK (1 << 12)
+#define OMAP3430_ST_MCBSP4_SHIFT 2
+#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
+#define OMAP3430_ST_MCBSP3_SHIFT 1
+#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
+#define OMAP3430_ST_MCBSP2_SHIFT 0
+#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
/* CM_AUTOIDLE_PER */
#define OMAP3430_AUTO_GPIO6 (1 << 17)
@@ -693,6 +735,10 @@
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
/* CM_IDLEST_USBHOST */
+#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
+#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
+#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
+#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
/* CM_AUTOIDLE_USBHOST */
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 4a32822..812d50e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -113,33 +113,58 @@
#define OMAP2430_EN_USBHS (1 << 6)
/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC (1 << 26)
-#define OMAP24XX_ST_UART2 (1 << 22)
-#define OMAP24XX_ST_UART1 (1 << 21)
-#define OMAP24XX_ST_MCSPI2 (1 << 18)
-#define OMAP24XX_ST_MCSPI1 (1 << 17)
-#define OMAP24XX_ST_GPT12 (1 << 14)
-#define OMAP24XX_ST_GPT11 (1 << 13)
-#define OMAP24XX_ST_GPT10 (1 << 12)
-#define OMAP24XX_ST_GPT9 (1 << 11)
-#define OMAP24XX_ST_GPT8 (1 << 10)
-#define OMAP24XX_ST_GPT7 (1 << 9)
-#define OMAP24XX_ST_GPT6 (1 << 8)
-#define OMAP24XX_ST_GPT5 (1 << 7)
-#define OMAP24XX_ST_GPT4 (1 << 6)
-#define OMAP24XX_ST_GPT3 (1 << 5)
-#define OMAP24XX_ST_GPT2 (1 << 4)
-#define OMAP2420_ST_VLYNQ (1 << 3)
+#define OMAP2420_ST_MMC_SHIFT 26
+#define OMAP2420_ST_MMC_MASK (1 << 26)
+#define OMAP24XX_ST_UART2_SHIFT 22
+#define OMAP24XX_ST_UART2_MASK (1 << 22)
+#define OMAP24XX_ST_UART1_SHIFT 21
+#define OMAP24XX_ST_UART1_MASK (1 << 21)
+#define OMAP24XX_ST_MCSPI2_SHIFT 18
+#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
+#define OMAP24XX_ST_MCSPI1_SHIFT 17
+#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
+#define OMAP24XX_ST_GPT12_SHIFT 14
+#define OMAP24XX_ST_GPT12_MASK (1 << 14)
+#define OMAP24XX_ST_GPT11_SHIFT 13
+#define OMAP24XX_ST_GPT11_MASK (1 << 13)
+#define OMAP24XX_ST_GPT10_SHIFT 12
+#define OMAP24XX_ST_GPT10_MASK (1 << 12)
+#define OMAP24XX_ST_GPT9_SHIFT 11
+#define OMAP24XX_ST_GPT9_MASK (1 << 11)
+#define OMAP24XX_ST_GPT8_SHIFT 10
+#define OMAP24XX_ST_GPT8_MASK (1 << 10)
+#define OMAP24XX_ST_GPT7_SHIFT 9
+#define OMAP24XX_ST_GPT7_MASK (1 << 9)
+#define OMAP24XX_ST_GPT6_SHIFT 8
+#define OMAP24XX_ST_GPT6_MASK (1 << 8)
+#define OMAP24XX_ST_GPT5_SHIFT 7
+#define OMAP24XX_ST_GPT5_MASK (1 << 7)
+#define OMAP24XX_ST_GPT4_SHIFT 6
+#define OMAP24XX_ST_GPT4_MASK (1 << 6)
+#define OMAP24XX_ST_GPT3_SHIFT 5
+#define OMAP24XX_ST_GPT3_MASK (1 << 5)
+#define OMAP24XX_ST_GPT2_SHIFT 4
+#define OMAP24XX_ST_GPT2_MASK (1 << 4)
+#define OMAP2420_ST_VLYNQ_SHIFT 3
+#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC (1 << 11)
-#define OMAP2430_ST_GPIO5 (1 << 10)
-#define OMAP2430_ST_MCSPI3 (1 << 9)
-#define OMAP2430_ST_MMCHS2 (1 << 8)
-#define OMAP2430_ST_MMCHS1 (1 << 7)
-#define OMAP2430_ST_USBHS (1 << 6)
-#define OMAP24XX_ST_UART3 (1 << 2)
-#define OMAP24XX_ST_USB (1 << 0)
+#define OMAP2430_ST_MDM_INTC_SHIFT 11
+#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
+#define OMAP2430_ST_GPIO5_SHIFT 10
+#define OMAP2430_ST_GPIO5_MASK (1 << 10)
+#define OMAP2430_ST_MCSPI3_SHIFT 9
+#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
+#define OMAP2430_ST_MMCHS2_SHIFT 8
+#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
+#define OMAP2430_ST_MMCHS1_SHIFT 7
+#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
+#define OMAP2430_ST_USBHS_SHIFT 6
+#define OMAP2430_ST_USBHS_MASK (1 << 6)
+#define OMAP24XX_ST_UART3_SHIFT 2
+#define OMAP24XX_ST_UART3_MASK (1 << 2)
+#define OMAP24XX_ST_USB_SHIFT 0
+#define OMAP24XX_ST_USB_MASK (1 << 0)
/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP24XX_EN_GPIOS_SHIFT 2
@@ -148,11 +173,13 @@
#define OMAP24XX_EN_GPT1 (1 << 0)
/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS (1 << 2)
-#define OMAP24XX_ST_GPT1 (1 << 0)
+#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
+#define OMAP24XX_ST_GPIOS_MASK 2
+#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
+#define OMAP24XX_ST_GPT1_MASK 0
/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT (1 << 0)
/* 3430 register bits shared between CM & PRM registers */
@@ -205,24 +232,46 @@
#define OMAP3430_EN_HSOTGUSB_SHIFT 4
/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
-#define OMAP3430_ST_MMC2 (1 << 25)
-#define OMAP3430_ST_MMC1 (1 << 24)
-#define OMAP3430_ST_MCSPI4 (1 << 21)
-#define OMAP3430_ST_MCSPI3 (1 << 20)
-#define OMAP3430_ST_MCSPI2 (1 << 19)
-#define OMAP3430_ST_MCSPI1 (1 << 18)
-#define OMAP3430_ST_I2C3 (1 << 17)
-#define OMAP3430_ST_I2C2 (1 << 16)
-#define OMAP3430_ST_I2C1 (1 << 15)
-#define OMAP3430_ST_UART2 (1 << 14)
-#define OMAP3430_ST_UART1 (1 << 13)
-#define OMAP3430_ST_GPT11 (1 << 12)
-#define OMAP3430_ST_GPT10 (1 << 11)
-#define OMAP3430_ST_MCBSP5 (1 << 10)
-#define OMAP3430_ST_MCBSP1 (1 << 9)
-#define OMAP3430_ST_FSHOSTUSB (1 << 5)
-#define OMAP3430_ST_HSOTGUSB (1 << 4)
-#define OMAP3430_ST_D2D (1 << 3)
+#define OMAP3430_ST_MMC2_SHIFT 25
+#define OMAP3430_ST_MMC2_MASK (1 << 25)
+#define OMAP3430_ST_MMC1_SHIFT 24
+#define OMAP3430_ST_MMC1_MASK (1 << 24)
+#define OMAP3430_ST_MCSPI4_SHIFT 21
+#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
+#define OMAP3430_ST_MCSPI3_SHIFT 20
+#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
+#define OMAP3430_ST_MCSPI2_SHIFT 19
+#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
+#define OMAP3430_ST_MCSPI1_SHIFT 18
+#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
+#define OMAP3430_ST_I2C3_SHIFT 17
+#define OMAP3430_ST_I2C3_MASK (1 << 17)
+#define OMAP3430_ST_I2C2_SHIFT 16
+#define OMAP3430_ST_I2C2_MASK (1 << 16)
+#define OMAP3430_ST_I2C1_SHIFT 15
+#define OMAP3430_ST_I2C1_MASK (1 << 15)
+#define OMAP3430_ST_UART2_SHIFT 14
+#define OMAP3430_ST_UART2_MASK (1 << 14)
+#define OMAP3430_ST_UART1_SHIFT 13
+#define OMAP3430_ST_UART1_MASK (1 << 13)
+#define OMAP3430_ST_GPT11_SHIFT 12
+#define OMAP3430_ST_GPT11_MASK (1 << 12)
+#define OMAP3430_ST_GPT10_SHIFT 11
+#define OMAP3430_ST_GPT10_MASK (1 << 11)
+#define OMAP3430_ST_MCBSP5_SHIFT 10
+#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
+#define OMAP3430_ST_MCBSP1_SHIFT 9
+#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
+#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
+#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
+#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
+#define OMAP3430_ST_D2D_SHIFT 3
+#define OMAP3430_ST_D2D_MASK (1 << 3)
/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPIO1 (1 << 3)
@@ -241,11 +290,16 @@
#define OMAP3430_EN_GPT12_SHIFT 1
/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
-#define OMAP3430_ST_SR2 (1 << 7)
-#define OMAP3430_ST_SR1 (1 << 6)
-#define OMAP3430_ST_GPIO1 (1 << 3)
-#define OMAP3430_ST_GPT12 (1 << 1)
-#define OMAP3430_ST_GPT1 (1 << 0)
+#define OMAP3430_ST_SR2_SHIFT 7
+#define OMAP3430_ST_SR2_MASK (1 << 7)
+#define OMAP3430_ST_SR1_SHIFT 6
+#define OMAP3430_ST_SR1_MASK (1 << 6)
+#define OMAP3430_ST_GPIO1_SHIFT 3
+#define OMAP3430_ST_GPIO1_MASK (1 << 3)
+#define OMAP3430_ST_GPT12_SHIFT 1
+#define OMAP3430_ST_GPT12_MASK (1 << 1)
+#define OMAP3430_ST_GPT1_SHIFT 0
+#define OMAP3430_ST_GPT1_MASK (1 << 0)
/*
* CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
@@ -296,20 +350,34 @@
#define OMAP3430_EN_MCBSP2_SHIFT 0
/* CM_IDLEST_PER, PM_WKST_PER shared bits */
-#define OMAP3430_ST_GPIO6 (1 << 17)
-#define OMAP3430_ST_GPIO5 (1 << 16)
-#define OMAP3430_ST_GPIO4 (1 << 15)
-#define OMAP3430_ST_GPIO3 (1 << 14)
-#define OMAP3430_ST_GPIO2 (1 << 13)
-#define OMAP3430_ST_UART3 (1 << 11)
-#define OMAP3430_ST_GPT9 (1 << 10)
-#define OMAP3430_ST_GPT8 (1 << 9)
-#define OMAP3430_ST_GPT7 (1 << 8)
-#define OMAP3430_ST_GPT6 (1 << 7)
-#define OMAP3430_ST_GPT5 (1 << 6)
-#define OMAP3430_ST_GPT4 (1 << 5)
-#define OMAP3430_ST_GPT3 (1 << 4)
-#define OMAP3430_ST_GPT2 (1 << 3)
+#define OMAP3430_ST_GPIO6_SHIFT 17
+#define OMAP3430_ST_GPIO6_MASK (1 << 17)
+#define OMAP3430_ST_GPIO5_SHIFT 16
+#define OMAP3430_ST_GPIO5_MASK (1 << 16)
+#define OMAP3430_ST_GPIO4_SHIFT 15
+#define OMAP3430_ST_GPIO4_MASK (1 << 15)
+#define OMAP3430_ST_GPIO3_SHIFT 14
+#define OMAP3430_ST_GPIO3_MASK (1 << 14)
+#define OMAP3430_ST_GPIO2_SHIFT 13
+#define OMAP3430_ST_GPIO2_MASK (1 << 13)
+#define OMAP3430_ST_UART3_SHIFT 11
+#define OMAP3430_ST_UART3_MASK (1 << 11)
+#define OMAP3430_ST_GPT9_SHIFT 10
+#define OMAP3430_ST_GPT9_MASK (1 << 10)
+#define OMAP3430_ST_GPT8_SHIFT 9
+#define OMAP3430_ST_GPT8_MASK (1 << 9)
+#define OMAP3430_ST_GPT7_SHIFT 8
+#define OMAP3430_ST_GPT7_MASK (1 << 8)
+#define OMAP3430_ST_GPT6_SHIFT 7
+#define OMAP3430_ST_GPT6_MASK (1 << 7)
+#define OMAP3430_ST_GPT5_SHIFT 6
+#define OMAP3430_ST_GPT5_MASK (1 << 6)
+#define OMAP3430_ST_GPT4_SHIFT 5
+#define OMAP3430_ST_GPT4_MASK (1 << 5)
+#define OMAP3430_ST_GPT3_SHIFT 4
+#define OMAP3430_ST_GPT3_MASK (1 << 4)
+#define OMAP3430_ST_GPT2_SHIFT 3
+#define OMAP3430_ST_GPT2_MASK (1 << 3)
/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
#define OMAP3430_EN_CORE_SHIFT 0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 04/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (2 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 03/11] OMAP2 PRCM: clean up CM_IDLEST bits Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 05/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks Paul Walmsley
` (6 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
McBSP clock source control registers are located in the System Control
Module, not the PRCM. However, the clock enable/disable registers are
in the CM. Since the following patches require all registers in a
struct clk to be in only one of {CM, PRM, SCM}, we must split the
source clock selection into a separate struct clk from the clock
enable/disable control.
linux-omap source commit is b670a37e77372b66bfb22a1f8633d906b9bbc26c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock34xx.h | 82 +++++++++++++++++++++++++++++++--------
1 files changed, 66 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 00ac92f..987fc4c 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1473,12 +1473,10 @@ static const struct clksel mcbsp_15_clksel[] = {
{ .parent = NULL }
};
-static struct clk mcbsp5_fck = {
- .name = "mcbsp_fck",
+static struct clk mcbsp5_src_fck = {
+ .name = "mcbsp_src_fck",
.id = 5,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel,
@@ -1487,12 +1485,21 @@ static struct clk mcbsp5_fck = {
.recalc = &omap2_clksel_recalc,
};
-static struct clk mcbsp1_fck = {
+static struct clk mcbsp5_fck = {
.name = "mcbsp_fck",
+ .id = 5,
+ .parent = &mcbsp5_src_fck,
+ .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp1_src_fck = {
+ .name = "mcbsp_src_fck",
.id = 1,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel,
@@ -1501,6 +1508,17 @@ static struct clk mcbsp1_fck = {
.recalc = &omap2_clksel_recalc,
};
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp_fck",
+ .id = 1,
+ .parent = &mcbsp1_src_fck,
+ .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
/* CORE_48M_FCK-derived clocks */
static struct clk core_48m_fck = {
@@ -2773,14 +2791,35 @@ static const struct clksel mcbsp_234_clksel[] = {
{ .parent = NULL }
};
+static struct clk mcbsp2_src_fck = {
+ .name = "mcbsp_src_fck",
+ .id = 2,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
+ .clksel = mcbsp_234_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "per_clkdm" },
+ .recalc = &omap2_clksel_recalc,
+};
+
static struct clk mcbsp2_fck = {
.name = "mcbsp_fck",
.id = 2,
- .init = &omap2_init_clksel_parent,
+ .parent = &mcbsp2_src_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
- .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "per_clkdm" },
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_src_fck = {
+ .name = "mcbsp_src_fck",
+ .id = 3,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2790,11 +2829,20 @@ static struct clk mcbsp2_fck = {
static struct clk mcbsp3_fck = {
.name = "mcbsp_fck",
.id = 3,
- .init = &omap2_init_clksel_parent,
+ .parent = &mcbsp3_src_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "per_clkdm" },
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_src_fck = {
+ .name = "mcbsp_src_fck",
+ .id = 4,
+ .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
- .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
+ .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2804,12 +2852,9 @@ static struct clk mcbsp3_fck = {
static struct clk mcbsp4_fck = {
.name = "mcbsp_fck",
.id = 4,
- .init = &omap2_init_clksel_parent,
+ .parent = &mcbsp4_src_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
- .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
- .clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
@@ -3091,7 +3136,9 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&i2c3_fck,
&i2c2_fck,
&i2c1_fck,
+ &mcbsp5_src_fck,
&mcbsp5_fck,
+ &mcbsp1_src_fck,
&mcbsp1_fck,
&core_48m_fck,
&mcspi4_fck,
@@ -3207,8 +3254,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&mcbsp2_ick,
&mcbsp3_ick,
&mcbsp4_ick,
+ &mcbsp2_src_fck,
&mcbsp2_fck,
+ &mcbsp3_src_fck,
&mcbsp3_fck,
+ &mcbsp4_src_fck,
&mcbsp4_fck,
&emu_src_ck,
&pclk_fck,
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 05/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (3 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 04/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 06/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks Paul Walmsley
` (5 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
Add a "prcm_mod" field to the struct clk in OMAP2/3, and annotate each
OMAP2xxx real hardware clock controlled by the PRCM with the PRCM
module offset. (A subsequent patch will annotate OMAP3 clocks.)
Add flags for this field that allow the registers to
be marked as existing in the PRM, CM, or System Control Module.
A subsequent patch will use this to simplify register addressing in the
struct clk.
linux-omap source commit is 754cdc4a81159bbe1387a4dd701b6b50acc51ba3.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock24xx.h | 128 +++++++++++++++++++++++++++++++
arch/arm/plat-omap/include/mach/clock.h | 8 ++
2 files changed, 136 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 8de312a..7150a3f 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -695,6 +695,7 @@ static struct dpll_data dpll_dd = {
static struct clk dpll_ck = {
.name = "dpll_ck",
.parent = &sys_ck, /* Can be func_32k also */
+ .prcm_mod = PLL_MOD,
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -706,6 +707,7 @@ static struct clk dpll_ck = {
static struct clk apll96_ck = {
.name = "apll96_ck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
@@ -720,6 +722,7 @@ static struct clk apll96_ck = {
static struct clk apll54_ck = {
.name = "apll54_ck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
@@ -756,6 +759,7 @@ static const struct clksel func_54m_clksel[] = {
static struct clk func_54m_ck = {
.name = "func_54m_ck",
.parent = &apll54_ck, /* can also be alt_clk */
+ .prcm_mod = PLL_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
@@ -796,6 +800,7 @@ static const struct clksel func_96m_clksel[] = {
static struct clk func_96m_ck = {
.name = "func_96m_ck",
.parent = &apll96_ck,
+ .prcm_mod = PLL_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
@@ -829,6 +834,7 @@ static const struct clksel func_48m_clksel[] = {
static struct clk func_48m_ck = {
.name = "func_48m_ck",
.parent = &apll96_ck, /* 96M or Alt */
+ .prcm_mod = PLL_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
@@ -899,6 +905,7 @@ static const struct clksel common_clkout_src_clksel[] = {
static struct clk sys_clkout_src = {
.name = "sys_clkout_src",
.parent = &func_54m_ck,
+ .prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | OFFSET_GR_MOD,
.clkdm = { .name = "prm_clkdm" },
@@ -930,6 +937,7 @@ static const struct clksel sys_clkout_clksel[] = {
static struct clk sys_clkout = {
.name = "sys_clkout",
.parent = &sys_clkout_src,
+ .prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
.clkdm = { .name = "prm_clkdm" },
@@ -945,6 +953,7 @@ static struct clk sys_clkout = {
static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.parent = &func_54m_ck,
+ .prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
.clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
@@ -967,6 +976,7 @@ static const struct clksel sys_clkout2_clksel[] = {
static struct clk sys_clkout2 = {
.name = "sys_clkout2",
.parent = &sys_clkout2_src,
+ .prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
OFFSET_GR_MOD,
.clkdm = { .name = "cm_clkdm" },
@@ -981,6 +991,7 @@ static struct clk sys_clkout2 = {
static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
+ .prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
.clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
@@ -1016,6 +1027,7 @@ static const struct clksel mpu_clksel[] = {
static struct clk mpu_ck = { /* Control cpu */
.name = "mpu_ck",
.parent = &core_ck,
+ .prcm_mod = MPU_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
@@ -1059,6 +1071,7 @@ static const struct clksel dsp_fck_clksel[] = {
static struct clk dsp_fck = {
.name = "dsp_fck",
.parent = &core_ck,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm = { .name = "dsp_clkdm" },
@@ -1089,6 +1102,7 @@ static const struct clksel dsp_irate_ick_clksel[] = {
static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick",
.parent = &dsp_fck,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "dsp_clkdm" },
@@ -1104,6 +1118,7 @@ static struct clk dsp_irate_ick = {
static struct clk dsp_ick = {
.name = "dsp_ick", /* apparently ipi and isp */
.parent = &dsp_irate_ick,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "dsp_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
@@ -1114,6 +1129,7 @@ static struct clk dsp_ick = {
static struct clk iva2_1_ick = {
.name = "iva2_1_ick",
.parent = &dsp_irate_ick,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "dsp_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
@@ -1128,6 +1144,7 @@ static struct clk iva2_1_ick = {
static struct clk iva1_ifck = {
.name = "iva1_ifck",
.parent = &core_ck,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
RATE_PROPAGATES | DELAYED_APP,
.clkdm = { .name = "iva1_clkdm" },
@@ -1145,6 +1162,7 @@ static struct clk iva1_ifck = {
static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
+ .prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "iva1_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
@@ -1191,6 +1209,7 @@ static const struct clksel core_l3_clksel[] = {
static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.name = "core_l3_ck",
.parent = &core_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
@@ -1220,6 +1239,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
.parent = &core_l3_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1254,6 +1274,7 @@ static const struct clksel l4_clksel[] = {
static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.parent = &core_l3_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1292,6 +1313,7 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
static struct clk ssi_ssr_sst_fck = {
.name = "ssi_fck",
.parent = &core_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
@@ -1312,6 +1334,7 @@ static struct clk ssi_ssr_sst_fck = {
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1342,6 +1365,7 @@ static const struct clksel gfx_fck_clksel[] = {
static struct clk gfx_3d_fck = {
.name = "gfx_3d_fck",
.parent = &core_l3_ck,
+ .prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
@@ -1357,6 +1381,7 @@ static struct clk gfx_3d_fck = {
static struct clk gfx_2d_fck = {
.name = "gfx_2d_fck",
.parent = &core_l3_ck,
+ .prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
@@ -1372,6 +1397,7 @@ static struct clk gfx_2d_fck = {
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.parent = &core_l3_ck,
+ .prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
@@ -1402,6 +1428,7 @@ static const struct clksel mdm_ick_clksel[] = {
static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
.parent = &core_ck,
+ .prcm_mod = OMAP2430_MDM_MOD,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "mdm_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -1417,6 +1444,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck",
.parent = &osc_ck,
+ .prcm_mod = OMAP2430_MDM_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "mdm_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -1462,6 +1490,7 @@ static const struct clksel dss1_fck_clksel[] = {
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1472,6 +1501,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
static struct clk dss1_fck = {
.name = "dss1_fck",
.parent = &core_ck, /* Core or sys */
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "dss_clkdm" },
@@ -1505,6 +1535,7 @@ static const struct clksel dss2_fck_clksel[] = {
static struct clk dss2_fck = { /* Alt clk used in power management */
.name = "dss2_fck",
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "dss_clkdm" },
@@ -1520,6 +1551,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
static struct clk dss_54m_fck = { /* Alt clk used in power management */
.name = "dss_54m_fck", /* 54m tv clk */
.parent = &func_54m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1548,6 +1580,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -1558,6 +1591,7 @@ static struct clk gpt1_ick = {
static struct clk gpt1_fck = {
.name = "gpt1_fck",
.parent = &func_32k_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -1574,6 +1608,7 @@ static struct clk gpt1_fck = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1584,6 +1619,7 @@ static struct clk gpt2_ick = {
static struct clk gpt2_fck = {
.name = "gpt2_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1598,6 +1634,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1608,6 +1645,7 @@ static struct clk gpt3_ick = {
static struct clk gpt3_fck = {
.name = "gpt3_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1622,6 +1660,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1632,6 +1671,7 @@ static struct clk gpt4_ick = {
static struct clk gpt4_fck = {
.name = "gpt4_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1646,6 +1686,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1656,6 +1697,7 @@ static struct clk gpt5_ick = {
static struct clk gpt5_fck = {
.name = "gpt5_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1670,6 +1712,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1680,6 +1723,7 @@ static struct clk gpt6_ick = {
static struct clk gpt6_fck = {
.name = "gpt6_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1694,6 +1738,7 @@ static struct clk gpt6_fck = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1704,6 +1749,7 @@ static struct clk gpt7_ick = {
static struct clk gpt7_fck = {
.name = "gpt7_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1718,6 +1764,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1728,6 +1775,7 @@ static struct clk gpt8_ick = {
static struct clk gpt8_fck = {
.name = "gpt8_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1742,6 +1790,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1752,6 +1801,7 @@ static struct clk gpt9_ick = {
static struct clk gpt9_fck = {
.name = "gpt9_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1766,6 +1816,7 @@ static struct clk gpt9_fck = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1776,6 +1827,7 @@ static struct clk gpt10_ick = {
static struct clk gpt10_fck = {
.name = "gpt10_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1790,6 +1842,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1800,6 +1853,7 @@ static struct clk gpt11_ick = {
static struct clk gpt11_fck = {
.name = "gpt11_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1814,6 +1868,7 @@ static struct clk gpt11_fck = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1824,6 +1879,7 @@ static struct clk gpt12_ick = {
static struct clk gpt12_fck = {
.name = "gpt12_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1839,6 +1895,7 @@ static struct clk mcbsp1_ick = {
.name = "mcbsp_ick",
.id = 1,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1850,6 +1907,7 @@ static struct clk mcbsp1_fck = {
.name = "mcbsp_fck",
.id = 1,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1861,6 +1919,7 @@ static struct clk mcbsp2_ick = {
.name = "mcbsp_ick",
.id = 2,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1872,6 +1931,7 @@ static struct clk mcbsp2_fck = {
.name = "mcbsp_fck",
.id = 2,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1883,6 +1943,7 @@ static struct clk mcbsp3_ick = {
.name = "mcbsp_ick",
.id = 3,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1894,6 +1955,7 @@ static struct clk mcbsp3_fck = {
.name = "mcbsp_fck",
.id = 3,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1905,6 +1967,7 @@ static struct clk mcbsp4_ick = {
.name = "mcbsp_ick",
.id = 4,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1916,6 +1979,7 @@ static struct clk mcbsp4_fck = {
.name = "mcbsp_fck",
.id = 4,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1927,6 +1991,7 @@ static struct clk mcbsp5_ick = {
.name = "mcbsp_ick",
.id = 5,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1938,6 +2003,7 @@ static struct clk mcbsp5_fck = {
.name = "mcbsp_fck",
.id = 5,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1949,6 +2015,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi_ick",
.id = 1,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1960,6 +2027,7 @@ static struct clk mcspi1_fck = {
.name = "mcspi_fck",
.id = 1,
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1971,6 +2039,7 @@ static struct clk mcspi2_ick = {
.name = "mcspi_ick",
.id = 2,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1982,6 +2051,7 @@ static struct clk mcspi2_fck = {
.name = "mcspi_fck",
.id = 2,
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1993,6 +2063,7 @@ static struct clk mcspi3_ick = {
.name = "mcspi_ick",
.id = 3,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2004,6 +2075,7 @@ static struct clk mcspi3_fck = {
.name = "mcspi_fck",
.id = 3,
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2014,6 +2086,7 @@ static struct clk mcspi3_fck = {
static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2024,6 +2097,7 @@ static struct clk uart1_ick = {
static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2034,6 +2108,7 @@ static struct clk uart1_fck = {
static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2044,6 +2119,7 @@ static struct clk uart2_ick = {
static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2054,6 +2130,7 @@ static struct clk uart2_fck = {
static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2064,6 +2141,7 @@ static struct clk uart3_ick = {
static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2074,6 +2152,7 @@ static struct clk uart3_fck = {
static struct clk gpios_ick = {
.name = "gpios_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2084,6 +2163,7 @@ static struct clk gpios_ick = {
static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -2095,6 +2175,7 @@ static struct clk gpios_fck = {
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2106,6 +2187,7 @@ static struct clk mpu_wdt_ick = {
static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -2116,6 +2198,7 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2128,6 +2211,7 @@ static struct clk sync_32k_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2138,6 +2222,7 @@ static struct clk wdt1_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2149,6 +2234,7 @@ static struct clk omapctrl_ick = {
static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
+ .prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2159,6 +2245,7 @@ static struct clk icr_ick = {
static struct clk cam_ick = {
.name = "cam_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2174,6 +2261,7 @@ static struct clk cam_ick = {
static struct clk cam_fck = {
.name = "cam_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2184,6 +2272,7 @@ static struct clk cam_fck = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2194,6 +2283,7 @@ static struct clk mailboxes_ick = {
static struct clk wdt4_ick = {
.name = "wdt4_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2204,6 +2294,7 @@ static struct clk wdt4_ick = {
static struct clk wdt4_fck = {
.name = "wdt4_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2214,6 +2305,7 @@ static struct clk wdt4_fck = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2224,6 +2316,7 @@ static struct clk wdt3_ick = {
static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2234,6 +2327,7 @@ static struct clk wdt3_fck = {
static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2244,6 +2338,7 @@ static struct clk mspro_ick = {
static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2254,6 +2349,7 @@ static struct clk mspro_fck = {
static struct clk mmc_ick = {
.name = "mmc_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2264,6 +2360,7 @@ static struct clk mmc_ick = {
static struct clk mmc_fck = {
.name = "mmc_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2274,6 +2371,7 @@ static struct clk mmc_fck = {
static struct clk fac_ick = {
.name = "fac_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2284,6 +2382,7 @@ static struct clk fac_ick = {
static struct clk fac_fck = {
.name = "fac_fck",
.parent = &func_12m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2294,6 +2393,7 @@ static struct clk fac_fck = {
static struct clk eac_ick = {
.name = "eac_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2304,6 +2404,7 @@ static struct clk eac_ick = {
static struct clk eac_fck = {
.name = "eac_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2314,6 +2415,7 @@ static struct clk eac_fck = {
static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2324,6 +2426,7 @@ static struct clk hdq_ick = {
static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &func_12m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2335,6 +2438,7 @@ static struct clk i2c2_ick = {
.name = "i2c_ick",
.id = 2,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2346,6 +2450,7 @@ static struct clk i2c2_fck = {
.name = "i2c_fck",
.id = 2,
.parent = &func_12m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2357,6 +2462,7 @@ static struct clk i2chs2_fck = {
.name = "i2c_fck",
.id = 2,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2368,6 +2474,7 @@ static struct clk i2c1_ick = {
.name = "i2c_ick",
.id = 1,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2379,6 +2486,7 @@ static struct clk i2c1_fck = {
.name = "i2c_fck",
.id = 1,
.parent = &func_12m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2390,6 +2498,7 @@ static struct clk i2chs1_fck = {
.name = "i2c_fck",
.id = 1,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2425,6 +2534,7 @@ static struct clk sdma_ick = {
static struct clk vlynq_ick = {
.name = "vlynq_ick",
.parent = &core_l3_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2460,6 +2570,7 @@ static const struct clksel vlynq_fck_clksel[] = {
static struct clk vlynq_fck = {
.name = "vlynq_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2476,6 +2587,7 @@ static struct clk vlynq_fck = {
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
@@ -2486,6 +2598,7 @@ static struct clk sdrc_ick = {
static struct clk des_ick = {
.name = "des_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2496,6 +2609,7 @@ static struct clk des_ick = {
static struct clk sha_ick = {
.name = "sha_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2506,6 +2620,7 @@ static struct clk sha_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2516,6 +2631,7 @@ static struct clk rng_ick = {
static struct clk aes_ick = {
.name = "aes_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2526,6 +2642,7 @@ static struct clk aes_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2536,6 +2653,7 @@ static struct clk pka_ick = {
static struct clk usb_fck = {
.name = "usb_fck",
.parent = &func_48m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2546,6 +2664,7 @@ static struct clk usb_fck = {
static struct clk usbhs_ick = {
.name = "usbhs_ick",
.parent = &core_l3_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2556,6 +2675,7 @@ static struct clk usbhs_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2566,6 +2686,7 @@ static struct clk mmchs1_ick = {
static struct clk mmchs1_fck = {
.name = "mmchs_fck",
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2577,6 +2698,7 @@ static struct clk mmchs2_ick = {
.name = "mmchs_ick",
.id = 1,
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2588,6 +2710,7 @@ static struct clk mmchs2_fck = {
.name = "mmchs_fck",
.id = 1,
.parent = &func_96m_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2598,6 +2721,7 @@ static struct clk mmchs2_fck = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2608,6 +2732,7 @@ static struct clk gpio5_ick = {
static struct clk gpio5_fck = {
.name = "gpio5_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2618,6 +2743,7 @@ static struct clk gpio5_fck = {
static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.parent = &l4_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2628,6 +2754,7 @@ static struct clk mdm_intc_ick = {
static struct clk mmchsdb1_fck = {
.name = "mmchsdb_fck",
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2639,6 +2766,7 @@ static struct clk mmchsdb2_fck = {
.name = "mmchsdb_fck",
.id = 1,
.parent = &func_32k_ck,
+ .prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f6adf39..22db786 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -87,6 +87,7 @@ struct clk {
const char *name;
struct clockdomain *ptr;
} clkdm;
+ s16 prcm_mod;
#else
__u8 rate_offset;
__u8 src_offset;
@@ -165,5 +166,12 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
+/*
+ * clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod
+ * is significant)
+ */
+#define PRCM_MOD_ADDR_MASK 0xff00
+#define CLK_REG_IN_PRM (1 << 0)
+#define CLK_REG_IN_SCM (1 << 1)
#endif
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 06/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (4 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 05/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 07/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg() Paul Walmsley
` (4 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
Annotate each OMAP2xxx real hardware clock controlled by the PRCM with
the PRCM module offset.
A subsequent patch will use this to simplify register addressing in the
struct clk.
linux-omap source commit is 05fb452b387fa248c5774540219ba9630318e409.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock34xx.h | 172 +++++++++++++++++++++++++++++++++++++++
1 files changed, 172 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 987fc4c..e0cb6c3 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -186,6 +186,7 @@ static const struct clksel osc_sys_clksel[] = {
/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
static struct clk osc_sys_ck = {
.name = "osc_sys_ck",
+ .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP3430_PRM_CLKSEL,
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
@@ -213,6 +214,7 @@ static const struct clksel sys_clksel[] = {
static struct clk sys_ck = {
.name = "sys_ck",
.parent = &osc_sys_ck,
+ .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
.clksel_mask = OMAP_SYSCLKDIV_MASK,
@@ -246,6 +248,7 @@ static struct clk mcbsp_clks = {
static struct clk sys_clkout1 = {
.name = "sys_clkout1",
.parent = &osc_sys_ck,
+ .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
.enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -308,6 +311,7 @@ static struct dpll_data dpll1_dd = {
static struct clk dpll1_ck = {
.name = "dpll1_ck",
.parent = &sys_ck,
+ .prcm_mod = MPU_MOD,
.dpll_data = &dpll1_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
@@ -342,6 +346,7 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
static struct clk dpll1_x2m2_ck = {
.name = "dpll1_x2m2_ck",
.parent = &dpll1_x2_ck,
+ .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
.clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
@@ -382,6 +387,7 @@ static struct dpll_data dpll2_dd = {
static struct clk dpll2_ck = {
.name = "dpll2_ck",
.parent = &sys_ck,
+ .prcm_mod = OMAP3430_IVA2_MOD,
.dpll_data = &dpll2_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.enable = &omap3_noncore_dpll_enable,
@@ -404,6 +410,7 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
static struct clk dpll2_m2_ck = {
.name = "dpll2_m2_ck",
.parent = &dpll2_ck,
+ .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
OMAP3430_CM_CLKSEL2_PLL),
@@ -444,6 +451,7 @@ static struct dpll_data dpll3_dd = {
static struct clk dpll3_ck = {
.name = "dpll3_ck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.dpll_data = &dpll3_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
@@ -512,6 +520,7 @@ static const struct clksel div31_dpll3m2_clksel[] = {
static struct clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
.parent = &dpll3_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
@@ -550,6 +559,7 @@ static const struct clksel div16_dpll3_clksel[] = {
static struct clk dpll3_m3_ck = {
.name = "dpll3_m3_ck",
.parent = &dpll3_ck,
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL3_MASK,
@@ -564,6 +574,7 @@ static struct clk dpll3_m3_ck = {
static struct clk dpll3_m3x2_ck = {
.name = "dpll3_m3x2_ck",
.parent = &dpll3_m3_ck,
+ .prcm_mod = PLL_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -608,6 +619,7 @@ static struct dpll_data dpll4_dd = {
static struct clk dpll4_ck = {
.name = "dpll4_ck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.dpll_data = &dpll4_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.enable = &omap3_noncore_dpll_enable,
@@ -641,6 +653,7 @@ static const struct clksel div16_dpll4_clksel[] = {
static struct clk dpll4_m2_ck = {
.name = "dpll4_m2_ck",
.parent = &dpll4_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
.clksel_mask = OMAP3430_DIV_96M_MASK,
@@ -655,6 +668,7 @@ static struct clk dpll4_m2_ck = {
static struct clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
.parent = &dpll4_m2_ck,
+ .prcm_mod = PLL_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -705,6 +719,7 @@ static const struct clksel omap_96m_fck_clksel[] = {
static struct clk omap_96m_fck = {
.name = "omap_96m_fck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_96M_MASK,
@@ -719,6 +734,7 @@ static struct clk omap_96m_fck = {
static struct clk dpll4_m3_ck = {
.name = "dpll4_m3_ck",
.parent = &dpll4_ck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
@@ -733,6 +749,7 @@ static struct clk dpll4_m3_ck = {
static struct clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.parent = &dpll4_m3_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
@@ -759,6 +776,7 @@ static const struct clksel omap_54m_clksel[] = {
static struct clk omap_54m_fck = {
.name = "omap_54m_fck",
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_54M_MASK,
@@ -787,6 +805,7 @@ static const struct clksel omap_48m_clksel[] = {
static struct clk omap_48m_fck = {
.name = "omap_48m_fck",
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_48M_MASK,
@@ -811,6 +830,7 @@ static struct clk omap_12m_fck = {
static struct clk dpll4_m4_ck = {
.name = "dpll4_m4_ck",
.parent = &dpll4_ck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
@@ -827,6 +847,7 @@ static struct clk dpll4_m4_ck = {
static struct clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
.parent = &dpll4_m4_ck,
+ .prcm_mod = PLL_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -838,6 +859,7 @@ static struct clk dpll4_m4x2_ck = {
static struct clk dpll4_m5_ck = {
.name = "dpll4_m5_ck",
.parent = &dpll4_ck,
+ .prcm_mod = OMAP3430_CAM_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
@@ -852,6 +874,7 @@ static struct clk dpll4_m5_ck = {
static struct clk dpll4_m5x2_ck = {
.name = "dpll4_m5x2_ck",
.parent = &dpll4_m5_ck,
+ .prcm_mod = PLL_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -863,6 +886,7 @@ static struct clk dpll4_m5x2_ck = {
static struct clk dpll4_m6_ck = {
.name = "dpll4_m6_ck",
.parent = &dpll4_ck,
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
@@ -877,6 +901,7 @@ static struct clk dpll4_m6_ck = {
static struct clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.parent = &dpll4_m6_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
@@ -923,6 +948,7 @@ static struct dpll_data dpll5_dd = {
static struct clk dpll5_ck = {
.name = "dpll5_ck",
.parent = &sys_ck,
+ .prcm_mod = PLL_MOD,
.dpll_data = &dpll5_dd,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
.enable = &omap3_noncore_dpll_enable,
@@ -941,6 +967,7 @@ static const struct clksel div16_dpll5_clksel[] = {
static struct clk dpll5_m2_ck = {
.name = "dpll5_m2_ck",
.parent = &dpll5_ck,
+ .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
@@ -983,6 +1010,7 @@ static const struct clksel clkout2_src_clksel[] = {
static struct clk clkout2_src_ck = {
.name = "clkout2_src_ck",
+ .prcm_mod = OMAP3430_CCR_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
@@ -1010,6 +1038,7 @@ static const struct clksel sys_clkout2_clksel[] = {
static struct clk sys_clkout2 = {
.name = "sys_clkout2",
+ .prcm_mod = OMAP3430_CCR_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
@@ -1047,6 +1076,7 @@ static const struct clksel div4_core_clksel[] = {
static struct clk dpll1_fck = {
.name = "dpll1_fck",
.parent = &core_ck,
+ .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
@@ -1081,6 +1111,7 @@ static const struct clksel arm_fck_clksel[] = {
static struct clk arm_fck = {
.name = "arm_fck",
.parent = &mpu_ck,
+ .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
@@ -1109,6 +1140,7 @@ static struct clk emu_mpu_alwon_ck = {
static struct clk dpll2_fck = {
.name = "dpll2_fck",
.parent = &core_ck,
+ .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
@@ -1122,6 +1154,7 @@ static struct clk dpll2_fck = {
static struct clk iva2_ck = {
.name = "iva2_ck",
.parent = &dpll2_m2_ck,
+ .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
@@ -1140,6 +1173,7 @@ static const struct clksel div2_core_clksel[] = {
static struct clk l3_ick = {
.name = "l3_ick",
.parent = &core_ck,
+ .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L3_MASK,
@@ -1158,6 +1192,7 @@ static const struct clksel div2_l3_clksel[] = {
static struct clk l4_ick = {
.name = "l4_ick",
.parent = &l3_ick,
+ .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L4_MASK,
@@ -1177,6 +1212,7 @@ static const struct clksel div2_l4_clksel[] = {
static struct clk rm_ick = {
.name = "rm_ick",
.parent = &l4_ick,
+ .prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
@@ -1199,6 +1235,7 @@ static const struct clksel gfx_l3_clksel[] = {
static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.parent = &l3_ick,
+ .prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
@@ -1210,6 +1247,7 @@ static struct clk gfx_l3_ck = {
static struct clk gfx_l3_fck = {
.name = "gfx_l3_fck",
.parent = &gfx_l3_ck,
+ .prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
@@ -1231,6 +1269,7 @@ static struct clk gfx_l3_ick = {
static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
+ .prcm_mod = GFX_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1241,6 +1280,7 @@ static struct clk gfx_cg1_ck = {
static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
+ .prcm_mod = GFX_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1271,6 +1311,7 @@ static const struct clksel sgx_clksel[] = {
static struct clk sgx_fck = {
.name = "sgx_fck",
.init = &omap2_init_clksel_parent,
+ .prcm_mod = OMAP3430ES2_SGX_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
@@ -1284,6 +1325,7 @@ static struct clk sgx_fck = {
static struct clk sgx_ick = {
.name = "sgx_ick",
.parent = &l3_ick,
+ .prcm_mod = OMAP3430ES2_SGX_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1296,6 +1338,7 @@ static struct clk sgx_ick = {
static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck",
.parent = &sys_ck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1312,6 +1355,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
static struct clk gpt10_fck = {
.name = "gpt10_fck",
.parent = &sys_ck,
+ .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1326,6 +1370,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_fck = {
.name = "gpt11_fck",
.parent = &sys_ck,
+ .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1340,6 +1385,7 @@ static struct clk gpt11_fck = {
static struct clk cpefuse_fck = {
.name = "cpefuse_fck",
.parent = &sys_ck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1350,6 +1396,7 @@ static struct clk cpefuse_fck = {
static struct clk ts_fck = {
.name = "ts_fck",
.parent = &omap_32k_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1360,6 +1407,7 @@ static struct clk ts_fck = {
static struct clk usbtll_fck = {
.name = "usbtll_fck",
.parent = &dpll5_m2_ck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1382,6 +1430,7 @@ static struct clk mmchs3_fck = {
.name = "mmchs_fck",
.id = 2,
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1393,6 +1442,7 @@ static struct clk mmchs2_fck = {
.name = "mmchs_fck",
.id = 1,
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1403,6 +1453,7 @@ static struct clk mmchs2_fck = {
static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1413,6 +1464,7 @@ static struct clk mspro_fck = {
static struct clk mmchs1_fck = {
.name = "mmchs_fck",
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1424,6 +1476,7 @@ static struct clk i2c3_fck = {
.name = "i2c_fck",
.id = 3,
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1435,6 +1488,7 @@ static struct clk i2c2_fck = {
.name = "i2c_fck",
.id = 2,
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1446,6 +1500,7 @@ static struct clk i2c1_fck = {
.name = "i2c_fck",
.id = 1,
.parent = &core_96m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1476,6 +1531,7 @@ static const struct clksel mcbsp_15_clksel[] = {
static struct clk mcbsp5_src_fck = {
.name = "mcbsp_src_fck",
.id = 5,
+ .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
@@ -1489,6 +1545,7 @@ static struct clk mcbsp5_fck = {
.name = "mcbsp_fck",
.id = 5,
.parent = &mcbsp5_src_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1499,6 +1556,7 @@ static struct clk mcbsp5_fck = {
static struct clk mcbsp1_src_fck = {
.name = "mcbsp_src_fck",
.id = 1,
+ .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
@@ -1512,6 +1570,7 @@ static struct clk mcbsp1_fck = {
.name = "mcbsp_fck",
.id = 1,
.parent = &mcbsp1_src_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1534,6 +1593,7 @@ static struct clk mcspi4_fck = {
.name = "mcspi_fck",
.id = 4,
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1545,6 +1605,7 @@ static struct clk mcspi3_fck = {
.name = "mcspi_fck",
.id = 3,
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1556,6 +1617,7 @@ static struct clk mcspi2_fck = {
.name = "mcspi_fck",
.id = 2,
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1567,6 +1629,7 @@ static struct clk mcspi1_fck = {
.name = "mcspi_fck",
.id = 1,
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1577,6 +1640,7 @@ static struct clk mcspi1_fck = {
static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1587,6 +1651,7 @@ static struct clk uart2_fck = {
static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1597,6 +1662,7 @@ static struct clk uart1_fck = {
static struct clk fshostusb_fck = {
.name = "fshostusb_fck",
.parent = &core_48m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1618,6 +1684,7 @@ static struct clk core_12m_fck = {
static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &core_12m_fck,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1645,6 +1712,7 @@ static const struct clksel ssi_ssr_clksel[] = {
static struct clk ssi_ssr_fck = {
.name = "ssi_ssr_fck",
.init = &omap2_init_clksel_parent,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
@@ -1684,6 +1752,7 @@ static struct clk core_l3_ick = {
static struct clk hsotgusb_ick = {
.name = "hsotgusb_ick",
.parent = &core_l3_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1694,6 +1763,7 @@ static struct clk hsotgusb_ick = {
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &core_l3_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
@@ -1724,6 +1794,7 @@ static struct clk security_l3_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
.parent = &security_l3_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1745,6 +1816,7 @@ static struct clk core_l4_ick = {
static struct clk usbtll_ick = {
.name = "usbtll_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1756,6 +1828,7 @@ static struct clk mmchs3_ick = {
.name = "mmchs_ick",
.id = 2,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1767,6 +1840,7 @@ static struct clk mmchs3_ick = {
static struct clk icr_ick = {
.name = "icr_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1777,6 +1851,7 @@ static struct clk icr_ick = {
static struct clk aes2_ick = {
.name = "aes2_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1787,6 +1862,7 @@ static struct clk aes2_ick = {
static struct clk sha12_ick = {
.name = "sha12_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1797,6 +1873,7 @@ static struct clk sha12_ick = {
static struct clk des2_ick = {
.name = "des2_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1808,6 +1885,7 @@ static struct clk mmchs2_ick = {
.name = "mmchs_ick",
.id = 1,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1818,6 +1896,7 @@ static struct clk mmchs2_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1828,6 +1907,7 @@ static struct clk mmchs1_ick = {
static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1838,6 +1918,7 @@ static struct clk mspro_ick = {
static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1849,6 +1930,7 @@ static struct clk mcspi4_ick = {
.name = "mcspi_ick",
.id = 4,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1860,6 +1942,7 @@ static struct clk mcspi3_ick = {
.name = "mcspi_ick",
.id = 3,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1871,6 +1954,7 @@ static struct clk mcspi2_ick = {
.name = "mcspi_ick",
.id = 2,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1882,6 +1966,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi_ick",
.id = 1,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1893,6 +1978,7 @@ static struct clk i2c3_ick = {
.name = "i2c_ick",
.id = 3,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1904,6 +1990,7 @@ static struct clk i2c2_ick = {
.name = "i2c_ick",
.id = 2,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1915,6 +2002,7 @@ static struct clk i2c1_ick = {
.name = "i2c_ick",
.id = 1,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1925,6 +2013,7 @@ static struct clk i2c1_ick = {
static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1935,6 +2024,7 @@ static struct clk uart2_ick = {
static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1945,6 +2035,7 @@ static struct clk uart1_ick = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1955,6 +2046,7 @@ static struct clk gpt11_ick = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1966,6 +2058,7 @@ static struct clk mcbsp5_ick = {
.name = "mcbsp_ick",
.id = 5,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1977,6 +2070,7 @@ static struct clk mcbsp1_ick = {
.name = "mcbsp_ick",
.id = 1,
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -1987,6 +2081,7 @@ static struct clk mcbsp1_ick = {
static struct clk fac_ick = {
.name = "fac_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1997,6 +2092,7 @@ static struct clk fac_ick = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2007,6 +2103,7 @@ static struct clk mailboxes_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &core_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
@@ -2028,6 +2125,7 @@ static struct clk ssi_l4_ick = {
static struct clk ssi_ick = {
.name = "ssi_ick",
.parent = &ssi_l4_ick,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2046,6 +2144,7 @@ static const struct clksel usb_l4_clksel[] = {
static struct clk usb_l4_ick = {
.name = "usb_l4_ick",
.parent = &l4_ick,
+ .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
@@ -2073,6 +2172,7 @@ static struct clk security_l4_ick2 = {
static struct clk aes1_ick = {
.name = "aes1_ick",
.parent = &security_l4_ick2,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2083,6 +2183,7 @@ static struct clk aes1_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
.parent = &security_l4_ick2,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2093,6 +2194,7 @@ static struct clk rng_ick = {
static struct clk sha11_ick = {
.name = "sha11_ick",
.parent = &security_l4_ick2,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2103,6 +2205,7 @@ static struct clk sha11_ick = {
static struct clk des1_ick = {
.name = "des1_ick",
.parent = &security_l4_ick2,
+ .prcm_mod = CORE_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2114,6 +2217,7 @@ static struct clk des1_ick = {
static struct clk dss1_alwon_fck = {
.name = "dss1_alwon_fck",
.parent = &dpll4_m4x2_ck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2124,6 +2228,7 @@ static struct clk dss1_alwon_fck = {
static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
.parent = &omap_54m_fck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2134,6 +2239,7 @@ static struct clk dss_tv_fck = {
static struct clk dss_96m_fck = {
.name = "dss_96m_fck",
.parent = &omap_96m_fck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2144,6 +2250,7 @@ static struct clk dss_96m_fck = {
static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.parent = &sys_ck,
+ .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2155,6 +2262,7 @@ static struct clk dss_ick = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.parent = &l4_ick,
+ .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2167,6 +2275,7 @@ static struct clk dss_ick = {
static struct clk cam_mclk = {
.name = "cam_mclk",
.parent = &dpll4_m5x2_ck,
+ .prcm_mod = OMAP3430_CAM_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2178,6 +2287,7 @@ static struct clk cam_ick = {
/* Handles both L3 and L4 clocks */
.name = "cam_ick",
.parent = &l4_ick,
+ .prcm_mod = OMAP3430_CAM_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2188,6 +2298,7 @@ static struct clk cam_ick = {
static struct clk csi2_96m_fck = {
.name = "csi2_96m_fck",
.parent = &core_96m_fck,
+ .prcm_mod = OMAP3430_CAM_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2200,6 +2311,7 @@ static struct clk csi2_96m_fck = {
static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.parent = &dpll5_m2_ck,
+ .prcm_mod = OMAP3430ES2_USBHOST_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2210,6 +2322,7 @@ static struct clk usbhost_120m_fck = {
static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.parent = &omap_48m_fck,
+ .prcm_mod = OMAP3430ES2_USBHOST_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2221,6 +2334,7 @@ static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
.parent = &l4_ick,
+ .prcm_mod = OMAP3430ES2_USBHOST_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2256,6 +2370,7 @@ static const struct clksel usim_clksel[] = {
/* 3430ES2 only */
static struct clk usim_fck = {
.name = "usim_fck",
+ .prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2270,6 +2385,7 @@ static struct clk usim_fck = {
/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
static struct clk gpt1_fck = {
.name = "gpt1_fck",
+ .prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2292,6 +2408,7 @@ static struct clk wkup_32k_fck = {
static struct clk gpio1_dbck = {
.name = "gpio1_dbck",
.parent = &wkup_32k_fck,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2302,6 +2419,7 @@ static struct clk gpio1_dbck = {
static struct clk wdt2_fck = {
.name = "wdt2_fck",
.parent = &wkup_32k_fck,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2322,6 +2440,7 @@ static struct clk wkup_l4_ick = {
static struct clk usim_ick = {
.name = "usim_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2332,6 +2451,7 @@ static struct clk usim_ick = {
static struct clk wdt2_ick = {
.name = "wdt2_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2342,6 +2462,7 @@ static struct clk wdt2_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2352,6 +2473,7 @@ static struct clk wdt1_ick = {
static struct clk gpio1_ick = {
.name = "gpio1_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2362,6 +2484,7 @@ static struct clk gpio1_ick = {
static struct clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2372,6 +2495,7 @@ static struct clk omap_32ksync_ick = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2382,6 +2506,7 @@ static struct clk gpt12_ick = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &wkup_l4_ick,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2414,6 +2539,7 @@ static struct clk per_48m_fck = {
static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &per_48m_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2423,6 +2549,7 @@ static struct clk uart3_fck = {
static struct clk gpt2_fck = {
.name = "gpt2_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2436,6 +2563,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_fck = {
.name = "gpt3_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2449,6 +2577,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_fck = {
.name = "gpt4_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2462,6 +2591,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_fck = {
.name = "gpt5_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2475,6 +2605,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_fck = {
.name = "gpt6_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2488,6 +2619,7 @@ static struct clk gpt6_fck = {
static struct clk gpt7_fck = {
.name = "gpt7_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2501,6 +2633,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_fck = {
.name = "gpt8_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2514,6 +2647,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_fck = {
.name = "gpt9_fck",
+ .prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2536,6 +2670,7 @@ static struct clk per_32k_alwon_fck = {
static struct clk gpio6_dbck = {
.name = "gpio6_dbck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2546,6 +2681,7 @@ static struct clk gpio6_dbck = {
static struct clk gpio5_dbck = {
.name = "gpio5_dbck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2556,6 +2692,7 @@ static struct clk gpio5_dbck = {
static struct clk gpio4_dbck = {
.name = "gpio4_dbck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2566,6 +2703,7 @@ static struct clk gpio4_dbck = {
static struct clk gpio3_dbck = {
.name = "gpio3_dbck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2576,6 +2714,7 @@ static struct clk gpio3_dbck = {
static struct clk gpio2_dbck = {
.name = "gpio2_dbck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2586,6 +2725,7 @@ static struct clk gpio2_dbck = {
static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &per_32k_alwon_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2605,6 +2745,7 @@ static struct clk per_l4_ick = {
static struct clk gpio6_ick = {
.name = "gpio6_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2615,6 +2756,7 @@ static struct clk gpio6_ick = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2625,6 +2767,7 @@ static struct clk gpio5_ick = {
static struct clk gpio4_ick = {
.name = "gpio4_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2635,6 +2778,7 @@ static struct clk gpio4_ick = {
static struct clk gpio3_ick = {
.name = "gpio3_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2645,6 +2789,7 @@ static struct clk gpio3_ick = {
static struct clk gpio2_ick = {
.name = "gpio2_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2655,6 +2800,7 @@ static struct clk gpio2_ick = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2665,6 +2811,7 @@ static struct clk wdt3_ick = {
static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2675,6 +2822,7 @@ static struct clk uart3_ick = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2685,6 +2833,7 @@ static struct clk gpt9_ick = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2695,6 +2844,7 @@ static struct clk gpt8_ick = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2705,6 +2855,7 @@ static struct clk gpt7_ick = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2715,6 +2866,7 @@ static struct clk gpt6_ick = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2725,6 +2877,7 @@ static struct clk gpt5_ick = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2735,6 +2888,7 @@ static struct clk gpt4_ick = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2745,6 +2899,7 @@ static struct clk gpt3_ick = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2756,6 +2911,7 @@ static struct clk mcbsp2_ick = {
.name = "mcbsp_ick",
.id = 2,
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2767,6 +2923,7 @@ static struct clk mcbsp3_ick = {
.name = "mcbsp_ick",
.id = 3,
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2778,6 +2935,7 @@ static struct clk mcbsp4_ick = {
.name = "mcbsp_ick",
.id = 4,
.parent = &per_l4_ick,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2794,6 +2952,7 @@ static const struct clksel mcbsp_234_clksel[] = {
static struct clk mcbsp2_src_fck = {
.name = "mcbsp_src_fck",
.id = 2,
+ .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
@@ -2807,6 +2966,7 @@ static struct clk mcbsp2_fck = {
.name = "mcbsp_fck",
.id = 2,
.parent = &mcbsp2_src_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2817,6 +2977,7 @@ static struct clk mcbsp2_fck = {
static struct clk mcbsp3_src_fck = {
.name = "mcbsp_src_fck",
.id = 3,
+ .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
@@ -2830,6 +2991,7 @@ static struct clk mcbsp3_fck = {
.name = "mcbsp_fck",
.id = 3,
.parent = &mcbsp3_src_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2840,6 +3002,7 @@ static struct clk mcbsp3_fck = {
static struct clk mcbsp4_src_fck = {
.name = "mcbsp_src_fck",
.id = 4,
+ .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
@@ -2853,6 +3016,7 @@ static struct clk mcbsp4_fck = {
.name = "mcbsp_fck",
.id = 4,
.parent = &mcbsp4_src_fck,
+ .prcm_mod = OMAP3430_PER_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2899,6 +3063,7 @@ static const struct clksel emu_src_clksel[] = {
*/
static struct clk emu_src_ck = {
.name = "emu_src_ck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
@@ -2923,6 +3088,7 @@ static const struct clksel pclk_emu_clksel[] = {
static struct clk pclk_fck = {
.name = "pclk_fck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
@@ -2946,6 +3112,7 @@ static const struct clksel pclkx2_emu_clksel[] = {
static struct clk pclkx2_fck = {
.name = "pclkx2_fck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
@@ -2962,6 +3129,7 @@ static const struct clksel atclk_emu_clksel[] = {
static struct clk atclk_fck = {
.name = "atclk_fck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
@@ -2973,6 +3141,7 @@ static struct clk atclk_fck = {
static struct clk traceclk_src_fck = {
.name = "traceclk_src_fck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
@@ -2996,6 +3165,7 @@ static const struct clksel traceclk_clksel[] = {
static struct clk traceclk_fck = {
.name = "traceclk_fck",
+ .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
@@ -3011,6 +3181,7 @@ static struct clk traceclk_fck = {
static struct clk sr1_fck = {
.name = "sr1_fck",
.parent = &sys_ck,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -3022,6 +3193,7 @@ static struct clk sr1_fck = {
static struct clk sr2_fck = {
.name = "sr2_fck",
.parent = &sys_ck,
+ .prcm_mod = WKUP_MOD,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 07/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg()
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (5 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 06/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 08/11] OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing Paul Walmsley
` (3 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
Create new static functions to read/write registers used in the struct
clk, _omap2_clk_{read,write}_reg(). A subsequent patch will use these
to ensure the correct register read/write instruction is used, which depends
on whether the clock registers are in the CM, PRM, or SCM.
linux-omap source commit is 2d8ea5c30f091efa6258f5c9dac292835cd36412.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 37 +++++++++++++++++++++++++++++++++++++
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 185e1b7..1662d85 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -28,6 +28,7 @@
#include <mach/clockdomain.h>
#include <mach/cpu.h>
#include <mach/prcm.h>
+#include <mach/control.h>
#include <asm/div64.h>
#include "memory.h"
@@ -76,6 +77,42 @@ u8 cpu_mask;
*-------------------------------------------------------------------------*/
/*
+ * _omap2_clk_read_reg - read a clock register
+ * @clk: struct clk *
+ *
+ * Given a struct clk *, returns the value of the clock's register.
+ */
+static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
+{
+ if (clk->prcm_mod & CLK_REG_IN_SCM)
+ return omap_ctrl_readl(reg_offset);
+ else if (clk->prcm_mod & CLK_REG_IN_PRM)
+ return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
+ reg_offset);
+ else
+ return cm_read_mod_reg(clk->prcm_mod, reg_offset);
+}
+
+/*
+ * _omap2_clk_write_reg - write a clock's register
+ * @v: value to write to the clock's enable_reg
+ * @clk: struct clk *
+ *
+ * Given a register value @v and struct clk * @clk, writes the value of @v to
+ * the clock's enable register. No return value.
+ */
+static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
+{
+ if (clk->prcm_mod & CLK_REG_IN_SCM)
+ omap_ctrl_writel(v, reg_offset);
+ else if (clk->prcm_mod & CLK_REG_IN_PRM)
+ prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
+ reg_offset);
+ else
+ cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
+}
+
+/*
* _dpll_test_fint - test whether an Fint value is valid for the DPLL
* @clk: DPLL struct clk to test
* @n: divider value (N) to test
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 08/11] OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (6 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 07/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg() Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 09/11] OMAP2/3 clock: encode target IDLEST bits Paul Walmsley
` (2 subsequent siblings)
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Paul Walmsley, Tony Lindgren
Use the clk->prcm_mod field for all register addresses in struct clk.
Remove all usage of the *_REGADDR() and *_OFFSET() macros from the
clock tree. This eliminates a set of (__force void __iomem *) casts
and removes all of the OMAP2xxx register address rewriting. Shrink
the width of the enable_reg/clksel_reg registers to 16 bits, saving 4
bytes per struct clk.
linux-omap source commit is 8607e3ad18003020969cc5c344453d37640c678c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 68 ++---
arch/arm/mach-omap2/clock24xx.c | 48 ----
arch/arm/mach-omap2/clock24xx.h | 324 ++++++++++++------------
arch/arm/mach-omap2/clock34xx.c | 27 +-
arch/arm/mach-omap2/clock34xx.h | 421 +++++++++++++++----------------
arch/arm/mach-omap2/cm.h | 3
arch/arm/plat-omap/common.c | 1
arch/arm/plat-omap/include/mach/clock.h | 17 +
8 files changed, 414 insertions(+), 495 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1662d85..dff4eaa 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -203,7 +203,8 @@ void omap2_init_clksel_parent(struct clk *clk)
if (!clk->clksel)
return;
- r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ r = _omap2_clk_read_reg(clk->clksel_reg, clk);
+ r &= clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
for (clks = clk->clksel; clks->parent && !found; clks++) {
@@ -254,10 +255,9 @@ u32 omap2_get_dpll_rate(struct clk *clk)
return 0;
/* Return bypass rate if DPLL is bypassed */
- v = __raw_readl(dd->control_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
-
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
@@ -272,7 +272,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
}
- v = __raw_readl(dd->mult_div1_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
dpll_mult = v & dd->mult_mask;
dpll_mult >>= __ffs(dd->mult_mask);
dpll_div = v & dd->div1_mask;
@@ -345,7 +345,8 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
*/
static void omap2_clk_wait_ready(struct clk *clk)
{
- void __iomem *reg, *other_reg, *st_reg;
+ void __iomem *other_reg, *st_reg;
+ u16 reg;
u32 bit;
/*
@@ -353,18 +354,18 @@ static void omap2_clk_wait_ready(struct clk *clk)
* it and pull it into struct clk itself somehow.
*/
reg = clk->enable_reg;
- if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
- (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
- other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
- else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
- (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
- other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
+ if (((reg & 0xff) >= CM_FCLKEN1) &&
+ ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+ other_reg = (void __iomem *)((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+ else if (((reg & 0xff) >= CM_ICLKEN1) &&
+ ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+ other_reg = (void __iomem *)((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
else
return;
/* REVISIT: What are the appropriate exclusions for 34XX? */
/* No check for DSS or cam clocks */
- if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+ if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
@@ -374,8 +375,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
/* REVISIT: What are the appropriate exclusions for 34XX? */
/* OMAP3: ignore DSS-mod clocks */
if (cpu_is_omap34xx() &&
- (((u32)reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
- ((((u32)reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
+ ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
+ (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
return;
@@ -402,18 +403,12 @@ static int _omap2_clk_enable(struct clk *clk)
if (clk->enable)
return clk->enable(clk);
- if (!clk->enable_reg) {
- printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
- clk->name);
- return 0; /* REVISIT: -EINVAL */
- }
-
- v = __raw_readl(clk->enable_reg);
+ v = _omap2_clk_read_reg(clk->enable_reg, clk);
if (clk->flags & INVERT_ENABLE)
v &= ~(1 << clk->enable_bit);
else
v |= (1 << clk->enable_bit);
- __raw_writel(v, clk->enable_reg);
+ _omap2_clk_write_reg(v, clk->enable_reg, clk);
wmb();
omap2_clk_wait_ready(clk);
@@ -434,22 +429,12 @@ static void _omap2_clk_disable(struct clk *clk)
return;
}
- if (!clk->enable_reg) {
- /*
- * 'Independent' here refers to a clock which is not
- * controlled by its parent.
- */
- printk(KERN_ERR "clock: clk_disable called on independent "
- "clock %s which has no enable_reg\n", clk->name);
- return;
- }
-
- v = __raw_readl(clk->enable_reg);
+ v = _omap2_clk_read_reg(clk->enable_reg, clk);
if (clk->flags & INVERT_ENABLE)
v |= (1 << clk->enable_bit);
else
v &= ~(1 << clk->enable_bit);
- __raw_writel(v, clk->enable_reg);
+ _omap2_clk_write_reg(v, clk->enable_reg, clk);
wmb();
}
@@ -732,7 +717,8 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
if (!clk->clksel_mask)
return 0;
- v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk);
+ v &= clk->clksel_mask;
v >>= __ffs(clk->clksel_mask);
return omap2_clksel_to_divisor(clk, v);
@@ -747,16 +733,16 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
if (validrate != rate)
- return -EINVAL;
+ return -EINVAL;
field_val = omap2_divisor_to_clksel(clk, new_div);
if (field_val == ~0)
return -EINVAL;
- v = __raw_readl(clk->clksel_reg);
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
- __raw_writel(v, clk->clksel_reg);
+ _omap2_clk_write_reg(v, clk->clksel_reg, clk);
wmb();
@@ -846,10 +832,10 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
_omap2_clk_disable(clk);
/* Set new source value (previous dividers if any in effect) */
- v = __raw_readl(clk->clksel_reg);
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
- __raw_writel(v, clk->clksel_reg);
+ _omap2_clk_write_reg(v, clk->clksel_reg, clk);
wmb();
if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
@@ -1084,7 +1070,7 @@ void omap2_clk_disable_unused(struct clk *clk)
v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
- regval32 = __raw_readl(clk->enable_reg);
+ regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
if ((regval32 & (1 << clk->enable_bit)) == v)
return;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 2398711..2047c06 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -223,7 +223,8 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
if (!dd)
goto dpll_exit;
- tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+ tmpset.cm_clksel1_pll = cm_read_mod_reg(clk->prcm_mod,
+ dd->mult_div1_reg);
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
@@ -522,39 +523,6 @@ static int __init omap2_clk_arch_init(void)
}
arch_initcall(omap2_clk_arch_init);
-static u32 prm_base;
-static u32 cm_base;
-
-/*
- * Since we share clock data for 242x and 243x, we need to rewrite some
- * some register base offsets. Assume offset is at prm_base if flagged,
- * else assume it's cm_base.
- */
-static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
-{
- u32 tmp = (__force u32)*reg;
-
- if ((tmp >> 24) != 0)
- return;
-
- if (flags & OFFSET_GR_MOD)
- tmp += prm_base;
- else
- tmp += cm_base;
-
- *reg = (__force void __iomem *)tmp;
-}
-
-void __init omap2_clk_rewrite_base(struct clk *clk)
-{
- omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
- omap2_clk_check_reg(clk->flags, &clk->enable_reg);
- if (clk->dpll_data) {
- omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
- omap2_clk_check_reg(0, &clk->dpll_data->control_reg);
- }
-}
-
int __init omap2_clk_init(void)
{
struct prcm_config *prcm;
@@ -566,12 +534,6 @@ int __init omap2_clk_init(void)
else if (cpu_is_omap2430())
cpu_mask = RATE_IN_243X;
- for (clkp = onchip_24xx_clks;
- clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
- clkp++) {
- omap2_clk_rewrite_base(*clkp);
- }
-
clk_init(&omap2_clk_functions);
omap2_osc_clk_recalc(&osc_ck);
@@ -625,9 +587,3 @@ int __init omap2_clk_init(void)
return 0;
}
-
-void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
-{
- prm_base = (__force u32)omap2_globals->prm;
- cm_base = (__force u32)omap2_globals->cm;
-}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 7150a3f..178f46d 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -600,13 +600,6 @@ static struct prcm_config rate_table[] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
-/*
- * Since 2420 and 2430 have different cm_base, we use offsets only here.
- * Clock code will rewrite the register address as needed.
- */
-#define _CM_REG_OFFSET(module, reg) ((void __iomem *)(module) + (reg))
-#define _GR_MOD_OFFSET(reg) ((void __iomem *)(OMAP24XX_GR_MOD + (reg)))
-
/*-------------------------------------------------------------------------
* 24xx clock tree.
*
@@ -677,10 +670,10 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
*/
static struct dpll_data dpll_dd = {
- .mult_div1_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+ .mult_div1_reg = CM_CLKSEL1,
.mult_mask = OMAP24XX_DPLL_MULT_MASK,
.div1_mask = OMAP24XX_DPLL_DIV_MASK,
- .control_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
+ .control_reg = CM_CLKEN,
.enable_mask = OMAP24XX_EN_DPLL_MASK,
.max_multiplier = 1024,
.min_divider = 1,
@@ -712,7 +705,7 @@ static struct clk apll96_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
.disable = &omap2_clk_fixed_disable,
@@ -727,7 +720,7 @@ static struct clk apll54_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
.disable = &omap2_clk_fixed_disable,
@@ -764,7 +757,7 @@ static struct clk func_54m_ck = {
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_54M_SOURCE,
.clksel = func_54m_clksel,
.recalc = &omap2_clksel_recalc,
@@ -805,7 +798,7 @@ static struct clk func_96m_ck = {
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP2430_96M_SOURCE,
.clksel = func_96m_clksel,
.recalc = &omap2_clksel_recalc,
@@ -839,7 +832,7 @@ static struct clk func_48m_ck = {
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_48M_SOURCE,
.clksel = func_48m_clksel,
.recalc = &omap2_clksel_recalc,
@@ -907,12 +900,12 @@ static struct clk sys_clkout_src = {
.parent = &func_54m_ck,
.prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | OFFSET_GR_MOD,
+ RATE_PROPAGATES,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
.clksel = common_clkout_src_clksel,
.recalc = &omap2_clksel_recalc,
@@ -939,9 +932,9 @@ static struct clk sys_clkout = {
.parent = &sys_clkout_src,
.prcm_mod = OMAP24XX_GR_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
+ PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "prm_clkdm" },
- .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel,
.recalc = &omap2_clksel_recalc,
@@ -954,12 +947,12 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.parent = &func_54m_ck,
.prcm_mod = OMAP24XX_GR_MOD,
- .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
+ .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
.clkdm = { .name = "cm_clkdm" },
- .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
.clksel = common_clkout_src_clksel,
.recalc = &omap2_clksel_recalc,
@@ -977,10 +970,9 @@ static struct clk sys_clkout2 = {
.name = "sys_clkout2",
.parent = &sys_clkout2_src,
.prcm_mod = OMAP24XX_GR_MOD,
- .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
- OFFSET_GR_MOD,
+ .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "cm_clkdm" },
- .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
.recalc = &omap2_clksel_recalc,
@@ -992,9 +984,9 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.prcm_mod = OMAP24XX_GR_MOD,
- .flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
+ .flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "cm_clkdm" },
- .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
+ .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc,
@@ -1033,7 +1025,7 @@ static struct clk mpu_ck = { /* Control cpu */
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm = { .name = "mpu_clkdm" },
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
.clksel = mpu_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1075,9 +1067,9 @@ static struct clk dsp_fck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm = { .name = "dsp_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
.clksel = dsp_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1106,7 +1098,7 @@ static struct clk dsp_irate_ick = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "dsp_clkdm" },
- .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1121,7 +1113,7 @@ static struct clk dsp_ick = {
.prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "dsp_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
};
@@ -1132,7 +1124,7 @@ static struct clk iva2_1_ick = {
.prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "dsp_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
};
@@ -1148,9 +1140,9 @@ static struct clk iva1_ifck = {
.flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
RATE_PROPAGATES | DELAYED_APP,
.clkdm = { .name = "iva1_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
.clksel = dsp_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1165,7 +1157,7 @@ static struct clk iva1_mpu_int_ifck = {
.prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "iva1_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
.fixed_div = 2,
.recalc = &omap2_fixed_divisor_recalc,
@@ -1214,7 +1206,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm = { .name = "core_l3_clkdm" },
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
.clksel = core_l3_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1243,9 +1235,9 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_USB_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
.clksel = usb_l4_ick_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1278,7 +1270,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
.clkdm = { .name = "core_l4_clkdm" },
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
.clksel = l4_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1317,9 +1309,9 @@ static struct clk ssi_ssr_sst_fck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_sst_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1337,7 +1329,7 @@ static struct clk ssi_l4_ick = {
.prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1368,9 +1360,9 @@ static struct clk gfx_3d_fck = {
.prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
- .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_3D_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1384,9 +1376,9 @@ static struct clk gfx_2d_fck = {
.prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
- .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_2D_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1400,7 +1392,7 @@ static struct clk gfx_ick = {
.prcm_mod = GFX_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "gfx_clkdm" },
- .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1431,9 +1423,9 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
.prcm_mod = OMAP2430_MDM_MOD,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm = { .name = "mdm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
- .clksel_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
.clksel = mdm_ick_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1447,7 +1439,7 @@ static struct clk mdm_osc_ck = {
.prcm_mod = OMAP2430_MDM_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "mdm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP2430_EN_OSC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1493,7 +1485,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "dss_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1505,10 +1497,10 @@ static struct clk dss1_fck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "dss_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
.clksel = dss1_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1539,10 +1531,10 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
.clkdm = { .name = "dss_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_DSS2_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
.clksel = dss2_fck_clksel,
.recalc = &followparent_recalc,
@@ -1554,7 +1546,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "dss_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_TV_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1583,7 +1575,7 @@ static struct clk gpt1_ick = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1594,10 +1586,10 @@ static struct clk gpt1_fck = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1611,7 +1603,7 @@ static struct clk gpt2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1622,10 +1614,10 @@ static struct clk gpt2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1637,7 +1629,7 @@ static struct clk gpt3_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1648,10 +1640,10 @@ static struct clk gpt3_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1663,7 +1655,7 @@ static struct clk gpt4_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1674,10 +1666,10 @@ static struct clk gpt4_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1689,7 +1681,7 @@ static struct clk gpt5_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1700,10 +1692,10 @@ static struct clk gpt5_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1715,7 +1707,7 @@ static struct clk gpt6_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1726,10 +1718,10 @@ static struct clk gpt6_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1741,7 +1733,7 @@ static struct clk gpt7_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1752,10 +1744,10 @@ static struct clk gpt7_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1767,7 +1759,7 @@ static struct clk gpt8_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1778,10 +1770,10 @@ static struct clk gpt8_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1793,7 +1785,7 @@ static struct clk gpt9_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1804,10 +1796,10 @@ static struct clk gpt9_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1819,7 +1811,7 @@ static struct clk gpt10_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1830,10 +1822,10 @@ static struct clk gpt10_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1845,7 +1837,7 @@ static struct clk gpt11_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1856,10 +1848,10 @@ static struct clk gpt11_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1871,7 +1863,7 @@ static struct clk gpt12_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1882,10 +1874,10 @@ static struct clk gpt12_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+ .clksel_reg = CM_CLKSEL2,
.clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
.clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc,
@@ -1898,7 +1890,7 @@ static struct clk mcbsp1_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1910,7 +1902,7 @@ static struct clk mcbsp1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1922,7 +1914,7 @@ static struct clk mcbsp2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1934,7 +1926,7 @@ static struct clk mcbsp2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1946,7 +1938,7 @@ static struct clk mcbsp3_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1958,7 +1950,7 @@ static struct clk mcbsp3_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1970,7 +1962,7 @@ static struct clk mcbsp4_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1982,7 +1974,7 @@ static struct clk mcbsp4_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1994,7 +1986,7 @@ static struct clk mcbsp5_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2006,7 +1998,7 @@ static struct clk mcbsp5_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2018,7 +2010,7 @@ static struct clk mcspi1_ick = {
.prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2030,7 +2022,7 @@ static struct clk mcspi1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2042,7 +2034,7 @@ static struct clk mcspi2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2054,7 +2046,7 @@ static struct clk mcspi2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2066,7 +2058,7 @@ static struct clk mcspi3_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2078,7 +2070,7 @@ static struct clk mcspi3_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2089,7 +2081,7 @@ static struct clk uart1_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2100,7 +2092,7 @@ static struct clk uart1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2111,7 +2103,7 @@ static struct clk uart2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2122,7 +2114,7 @@ static struct clk uart2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2133,7 +2125,7 @@ static struct clk uart3_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2144,7 +2136,7 @@ static struct clk uart3_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2155,7 +2147,7 @@ static struct clk gpios_ick = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2166,7 +2158,7 @@ static struct clk gpios_fck = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2178,7 +2170,7 @@ static struct clk mpu_wdt_ick = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2190,7 +2182,7 @@ static struct clk mpu_wdt_fck = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2202,7 +2194,7 @@ static struct clk sync_32k_ick = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2214,7 +2206,7 @@ static struct clk wdt1_ick = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "prm_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2226,7 +2218,7 @@ static struct clk omapctrl_ick = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2237,7 +2229,7 @@ static struct clk icr_ick = {
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP2430_EN_ICR_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2248,7 +2240,7 @@ static struct clk cam_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2264,7 +2256,7 @@ static struct clk cam_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2275,7 +2267,7 @@ static struct clk mailboxes_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2286,7 +2278,7 @@ static struct clk wdt4_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2297,7 +2289,7 @@ static struct clk wdt4_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2308,7 +2300,7 @@ static struct clk wdt3_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2319,7 +2311,7 @@ static struct clk wdt3_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2330,7 +2322,7 @@ static struct clk mspro_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2341,7 +2333,7 @@ static struct clk mspro_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2352,7 +2344,7 @@ static struct clk mmc_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2363,7 +2355,7 @@ static struct clk mmc_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2374,7 +2366,7 @@ static struct clk fac_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2385,7 +2377,7 @@ static struct clk fac_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2396,7 +2388,7 @@ static struct clk eac_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2407,7 +2399,7 @@ static struct clk eac_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2418,7 +2410,7 @@ static struct clk hdq_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2429,7 +2421,7 @@ static struct clk hdq_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2441,7 +2433,7 @@ static struct clk i2c2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2453,7 +2445,7 @@ static struct clk i2c2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2465,7 +2457,7 @@ static struct clk i2chs2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2477,7 +2469,7 @@ static struct clk i2c1_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2489,7 +2481,7 @@ static struct clk i2c1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2501,7 +2493,7 @@ static struct clk i2chs1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2537,7 +2529,7 @@ static struct clk vlynq_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2573,10 +2565,10 @@ static struct clk vlynq_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
.clksel = vlynq_fck_clksel,
.recalc = &omap2_clksel_recalc,
@@ -2590,7 +2582,7 @@ static struct clk sdrc_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
+ .enable_reg = CM_ICLKEN3,
.enable_bit = OMAP2430_EN_SDRC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2601,7 +2593,7 @@ static struct clk des_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_DES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2612,7 +2604,7 @@ static struct clk sha_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_SHA_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2623,7 +2615,7 @@ static struct clk rng_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_RNG_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2634,7 +2626,7 @@ static struct clk aes_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_AES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2645,7 +2637,7 @@ static struct clk pka_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_PKA_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2656,7 +2648,7 @@ static struct clk usb_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP24XX_EN_USB_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2667,7 +2659,7 @@ static struct clk usbhs_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_USBHS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2678,7 +2670,7 @@ static struct clk mmchs1_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2689,7 +2681,7 @@ static struct clk mmchs1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l3_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2701,7 +2693,7 @@ static struct clk mmchs2_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2713,7 +2705,7 @@ static struct clk mmchs2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2724,7 +2716,7 @@ static struct clk gpio5_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2735,7 +2727,7 @@ static struct clk gpio5_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2746,7 +2738,7 @@ static struct clk mdm_intc_ick = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2757,7 +2749,7 @@ static struct clk mmchsdb1_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2769,7 +2761,7 @@ static struct clk mmchsdb2_fck = {
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP243X,
.clkdm = { .name = "core_l4_clkdm" },
- .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
.recalc = &followparent_recalc,
};
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 0c8d88e..c3c8537 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -66,10 +66,10 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
dd = clk->dpll_data;
- v = __raw_readl(dd->control_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
- __raw_writel(v, dd->control_reg);
+ cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
}
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -83,7 +83,8 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
state <<= __ffs(dd->idlest_mask);
- while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+ while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
+ & dd->idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) {
i++;
udelay(1);
@@ -348,17 +349,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
_omap3_noncore_dpll_bypass(clk);
/* Set jitter correction */
- v = __raw_readl(dd->control_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
- __raw_writel(v, dd->control_reg);
+ cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
/* Set DPLL multiplier, divider */
- v = __raw_readl(dd->mult_div1_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= m << __ffs(dd->mult_mask);
v |= (n - 1) << __ffs(dd->div1_mask);
- __raw_writel(v, dd->mult_div1_reg);
+ cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
/* We let the clock framework set the other output dividers later */
@@ -454,7 +455,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
dd = clk->dpll_data;
- v = __raw_readl(dd->autoidle_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
@@ -485,10 +486,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
* by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode.
*/
- v = __raw_readl(dd->autoidle_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
- __raw_writel(v, dd->autoidle_reg);
+ cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
}
/**
@@ -507,10 +508,10 @@ static void omap3_dpll_deny_idle(struct clk *clk)
dd = clk->dpll_data;
- v = __raw_readl(dd->autoidle_reg);
+ v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
- __raw_writel(v, dd->autoidle_reg);
+ cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
}
/* Clock control for DPLL outputs */
@@ -540,7 +541,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
- v = __raw_readl(dd->control_reg) & dd->enable_mask;
+ v = cm_read_mod_reg(pclk->prcm_mod, dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if (v != OMAP3XXX_EN_DPLL_LOCKED)
clk->rate = clk->parent->rate;
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e0cb6c3..aef5049 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -57,15 +57,6 @@ static struct clk dpll2_fck;
#define DPLL_LOW_POWER_BYPASS 0x5
#define DPLL_LOCKED 0x7
-#define OMAP3430_PRM_CLKSRC_CTRL \
- OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
-
-#define OMAP3430_PRM_CLKSEL \
- OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
-
-#define OMAP3430_PRM_CLKOUT_CTRL \
- OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
-
/* PRM CLOCKS */
/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -188,7 +179,7 @@ static struct clk osc_sys_ck = {
.name = "osc_sys_ck",
.prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_PRM_CLKSEL,
+ .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
.clksel = osc_sys_clksel,
/* REVISIT: deal with autoextclkmode? */
@@ -216,7 +207,7 @@ static struct clk sys_ck = {
.parent = &osc_sys_ck,
.prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
+ .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -249,7 +240,7 @@ static struct clk sys_clkout1 = {
.name = "sys_clkout1",
.parent = &osc_sys_ck,
.prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
- .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
+ .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -280,26 +271,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
{ .div = 0 }
};
-#define _OMAP34XX_CM_REGADDR(module, reg) \
- ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
-
/* DPLL1 */
/* MPU clock source */
/* Type: DPLL */
static struct dpll_data dpll1_dd = {
- .mult_div1_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
.mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
.div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
.freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
- .control_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+ .control_reg = OMAP3430_CM_CLKEN_PLL,
.enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
- .autoidle_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+ .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
.autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
- .idlest_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+ .idlest_reg = OMAP3430_CM_IDLEST_PLL,
.idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
.bypass_clk = &dpll1_fck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -348,7 +336,7 @@ static struct clk dpll1_x2m2_ck = {
.parent = &dpll1_x2_ck,
.prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+ .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
.clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll1_x2m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -362,20 +350,20 @@ static struct clk dpll1_x2m2_ck = {
/* Type: DPLL */
static struct dpll_data dpll2_dd = {
- .mult_div1_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
.mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
.div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
.freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
- .control_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+ .control_reg = OMAP3430_CM_CLKEN_PLL,
.enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
(1 << DPLL_LOW_POWER_BYPASS),
.auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
- .autoidle_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+ .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
.autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
- .idlest_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+ .idlest_reg = OMAP3430_CM_IDLEST_PLL,
.idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
.bypass_clk = &dpll2_fck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -412,8 +400,7 @@ static struct clk dpll2_m2_ck = {
.parent = &dpll2_ck,
.prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
- OMAP3430_CM_CLKSEL2_PLL),
+ .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
.clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll2_m2x2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -428,18 +415,18 @@ static struct clk dpll2_m2_ck = {
* REVISIT: Also supports fast relock bypass - not included below
*/
static struct dpll_data dpll3_dd = {
- .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_div1_reg = CM_CLKSEL1,
.mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
.div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
.freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
- .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .control_reg = CM_CLKEN,
.enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
.auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
- .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+ .autoidle_reg = CM_AUTOIDLE,
.autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
- .idlest_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .idlest_reg = CM_IDLEST,
.idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
.bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -522,7 +509,7 @@ static struct clk dpll3_m2_ck = {
.parent = &dpll3_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
.clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -561,7 +548,7 @@ static struct clk dpll3_m3_ck = {
.parent = &dpll3_ck,
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_DIV_DPLL3_MASK,
.clksel = div16_dpll3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -575,7 +562,7 @@ static struct clk dpll3_m3x2_ck = {
.name = "dpll3_m3x2_ck",
.parent = &dpll3_m3_ck,
.prcm_mod = PLL_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll3_clkdm" },
@@ -595,19 +582,19 @@ static struct clk emu_core_alwon_ck = {
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
/* Type: DPLL */
static struct dpll_data dpll4_dd = {
- .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+ .mult_div1_reg = CM_CLKSEL2,
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
.freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
- .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .control_reg = CM_CLKEN,
.enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
- .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+ .autoidle_reg = CM_AUTOIDLE,
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
- .idlest_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .idlest_reg = CM_IDLEST,
.idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -655,7 +642,7 @@ static struct clk dpll4_m2_ck = {
.parent = &dpll4_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+ .clksel_reg = OMAP3430_CM_CLKSEL3,
.clksel_mask = OMAP3430_DIV_96M_MASK,
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -669,7 +656,7 @@ static struct clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
.parent = &dpll4_m2_ck,
.prcm_mod = PLL_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll4_clkdm" },
@@ -721,7 +708,7 @@ static struct clk omap_96m_fck = {
.parent = &sys_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_SOURCE_96M_MASK,
.clksel = omap_96m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -736,7 +723,7 @@ static struct clk dpll4_m3_ck = {
.parent = &dpll4_ck,
.prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -751,7 +738,7 @@ static struct clk dpll4_m3x2_ck = {
.parent = &dpll4_m3_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll4_clkdm" },
@@ -778,7 +765,7 @@ static struct clk omap_54m_fck = {
.name = "omap_54m_fck",
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_SOURCE_54M_MASK,
.clksel = omap_54m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -807,7 +794,7 @@ static struct clk omap_48m_fck = {
.name = "omap_48m_fck",
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_SOURCE_48M_MASK,
.clksel = omap_48m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -832,7 +819,7 @@ static struct clk dpll4_m4_ck = {
.parent = &dpll4_ck,
.prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -848,8 +835,8 @@ static struct clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
.parent = &dpll4_m4_ck,
.prcm_mod = PLL_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
- .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .enable_reg = CM_CLKEN,
+ .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
@@ -861,7 +848,7 @@ static struct clk dpll4_m5_ck = {
.parent = &dpll4_ck,
.prcm_mod = OMAP3430_CAM_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -875,7 +862,7 @@ static struct clk dpll4_m5x2_ck = {
.name = "dpll4_m5x2_ck",
.parent = &dpll4_m5_ck,
.prcm_mod = PLL_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll4_clkdm" },
@@ -888,7 +875,7 @@ static struct clk dpll4_m6_ck = {
.parent = &dpll4_ck,
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -903,7 +890,7 @@ static struct clk dpll4_m6x2_ck = {
.parent = &dpll4_m6_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_reg = CM_CLKEN,
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.clkdm = { .name = "dpll4_clkdm" },
@@ -924,19 +911,19 @@ static struct clk emu_per_alwon_ck = {
/* Type: DPLL */
/* 3430ES2 only */
static struct dpll_data dpll5_dd = {
- .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+ .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
.mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
.div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
.freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
- .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+ .control_reg = OMAP3430ES2_CM_CLKEN2,
.enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
- .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+ .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
.autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
- .idlest_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+ .idlest_reg = CM_IDLEST2,
.idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
.bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -969,7 +956,7 @@ static struct clk dpll5_m2_ck = {
.parent = &dpll5_ck,
.prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+ .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
.clksel = div16_dpll5_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
@@ -1012,9 +999,9 @@ static struct clk clkout2_src_ck = {
.name = "clkout2_src_ck",
.prcm_mod = OMAP3430_CCR_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+ .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
.enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
- .clksel_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1040,7 +1027,7 @@ static struct clk sys_clkout2 = {
.name = "sys_clkout2",
.prcm_mod = OMAP3430_CCR_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1078,7 +1065,7 @@ static struct clk dpll1_fck = {
.parent = &core_ck,
.prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
.clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1113,7 +1100,7 @@ static struct clk arm_fck = {
.parent = &mpu_ck,
.prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+ .clksel_reg = OMAP3430_CM_IDLEST_PLL,
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
.clksel = arm_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1142,7 +1129,7 @@ static struct clk dpll2_fck = {
.parent = &core_ck,
.prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
.clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1156,7 +1143,7 @@ static struct clk iva2_ck = {
.parent = &dpll2_m2_ck,
.prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.clkdm = { .name = "iva2_clkdm" },
@@ -1175,7 +1162,7 @@ static struct clk l3_ick = {
.parent = &core_ck,
.prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_L3_MASK,
.clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1194,7 +1181,7 @@ static struct clk l4_ick = {
.parent = &l3_ick,
.prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_L4_MASK,
.clksel = div2_l3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1214,7 +1201,7 @@ static struct clk rm_ick = {
.parent = &l4_ick,
.prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
.clksel = div2_l4_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1237,7 +1224,7 @@ static struct clk gfx_l3_ck = {
.parent = &l3_ick,
.prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP_EN_GFX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "gfx_3430es1_clkdm" },
@@ -1249,7 +1236,7 @@ static struct clk gfx_l3_fck = {
.parent = &gfx_l3_ck,
.prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel,
.flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
@@ -1270,7 +1257,7 @@ static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.prcm_mod = GFX_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "gfx_3430es1_clkdm" },
@@ -1281,7 +1268,7 @@ static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.prcm_mod = GFX_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "gfx_3430es1_clkdm" },
@@ -1312,9 +1299,9 @@ static struct clk sgx_fck = {
.name = "sgx_fck",
.init = &omap2_init_clksel_parent,
.prcm_mod = OMAP3430ES2_SGX_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1326,7 +1313,7 @@ static struct clk sgx_ick = {
.name = "sgx_ick",
.parent = &l3_ick,
.prcm_mod = OMAP3430ES2_SGX_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "sgx_clkdm" },
@@ -1339,7 +1326,7 @@ static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck",
.parent = &sys_ck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "d2d_clkdm" },
@@ -1357,9 +1344,9 @@ static struct clk gpt10_fck = {
.parent = &sys_ck,
.prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -1372,9 +1359,9 @@ static struct clk gpt11_fck = {
.parent = &sys_ck,
.prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -1386,7 +1373,7 @@ static struct clk cpefuse_fck = {
.name = "cpefuse_fck",
.parent = &sys_ck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_reg = OMAP3430ES2_CM_FCLKEN3,
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "cm_clkdm" },
@@ -1397,7 +1384,7 @@ static struct clk ts_fck = {
.name = "ts_fck",
.parent = &omap_32k_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_reg = OMAP3430ES2_CM_FCLKEN3,
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1408,7 +1395,7 @@ static struct clk usbtll_fck = {
.name = "usbtll_fck",
.parent = &dpll5_m2_ck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_reg = OMAP3430ES2_CM_FCLKEN3,
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1431,7 +1418,7 @@ static struct clk mmchs3_fck = {
.id = 2,
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1443,7 +1430,7 @@ static struct clk mmchs2_fck = {
.id = 1,
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1454,7 +1441,7 @@ static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1465,7 +1452,7 @@ static struct clk mmchs1_fck = {
.name = "mmchs_fck",
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1477,7 +1464,7 @@ static struct clk i2c3_fck = {
.id = 3,
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1489,7 +1476,7 @@ static struct clk i2c2_fck = {
.id = 2,
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1501,7 +1488,7 @@ static struct clk i2c1_fck = {
.id = 1,
.parent = &core_96m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1533,7 +1520,7 @@ static struct clk mcbsp5_src_fck = {
.id = 5,
.prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -1546,7 +1533,7 @@ static struct clk mcbsp5_fck = {
.id = 5,
.parent = &mcbsp5_src_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1558,7 +1545,7 @@ static struct clk mcbsp1_src_fck = {
.id = 1,
.prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_reg = OMAP2_CONTROL_DEVCONF0,
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -1571,7 +1558,7 @@ static struct clk mcbsp1_fck = {
.id = 1,
.parent = &mcbsp1_src_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1594,7 +1581,7 @@ static struct clk mcspi4_fck = {
.id = 4,
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1606,7 +1593,7 @@ static struct clk mcspi3_fck = {
.id = 3,
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1618,7 +1605,7 @@ static struct clk mcspi2_fck = {
.id = 2,
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1630,7 +1617,7 @@ static struct clk mcspi1_fck = {
.id = 1,
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1641,7 +1628,7 @@ static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1652,7 +1639,7 @@ static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1663,7 +1650,7 @@ static struct clk fshostusb_fck = {
.name = "fshostusb_fck",
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1685,7 +1672,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &core_12m_fck,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1713,9 +1700,9 @@ static struct clk ssi_ssr_fck = {
.name = "ssi_ssr_fck",
.init = &omap2_init_clksel_parent,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_SSI_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1753,7 +1740,7 @@ static struct clk hsotgusb_ick = {
.name = "hsotgusb_ick",
.parent = &core_l3_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l3_clkdm" },
@@ -1764,7 +1751,7 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &core_l3_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
.clkdm = { .name = "core_l3_clkdm" },
@@ -1795,7 +1782,7 @@ static struct clk pka_ick = {
.name = "pka_ick",
.parent = &security_l3_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_PKA_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l3_clkdm" },
@@ -1817,7 +1804,7 @@ static struct clk usbtll_ick = {
.name = "usbtll_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_reg = CM_ICLKEN3,
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1829,7 +1816,7 @@ static struct clk mmchs3_ick = {
.id = 2,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1841,7 +1828,7 @@ static struct clk icr_ick = {
.name = "icr_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_ICR_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1852,7 +1839,7 @@ static struct clk aes2_ick = {
.name = "aes2_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_AES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1863,7 +1850,7 @@ static struct clk sha12_ick = {
.name = "sha12_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1874,7 +1861,7 @@ static struct clk des2_ick = {
.name = "des2_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_DES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1886,7 +1873,7 @@ static struct clk mmchs2_ick = {
.id = 1,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1897,7 +1884,7 @@ static struct clk mmchs1_ick = {
.name = "mmchs_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1908,7 +1895,7 @@ static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1919,7 +1906,7 @@ static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1931,7 +1918,7 @@ static struct clk mcspi4_ick = {
.id = 4,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1943,7 +1930,7 @@ static struct clk mcspi3_ick = {
.id = 3,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1955,7 +1942,7 @@ static struct clk mcspi2_ick = {
.id = 2,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1967,7 +1954,7 @@ static struct clk mcspi1_ick = {
.id = 1,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1979,7 +1966,7 @@ static struct clk i2c3_ick = {
.id = 3,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -1991,7 +1978,7 @@ static struct clk i2c2_ick = {
.id = 2,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2003,7 +1990,7 @@ static struct clk i2c1_ick = {
.id = 1,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2014,7 +2001,7 @@ static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2025,7 +2012,7 @@ static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2036,7 +2023,7 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2047,7 +2034,7 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2059,7 +2046,7 @@ static struct clk mcbsp5_ick = {
.id = 5,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2071,7 +2058,7 @@ static struct clk mcbsp1_ick = {
.id = 1,
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2082,7 +2069,7 @@ static struct clk fac_ick = {
.name = "fac_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2093,7 +2080,7 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2104,7 +2091,7 @@ static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &core_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2126,7 +2113,7 @@ static struct clk ssi_ick = {
.name = "ssi_ick",
.parent = &ssi_l4_ick,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2146,9 +2133,9 @@ static struct clk usb_l4_ick = {
.parent = &l4_ick,
.prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -2173,7 +2160,7 @@ static struct clk aes1_ick = {
.name = "aes1_ick",
.parent = &security_l4_ick2,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_AES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2184,7 +2171,7 @@ static struct clk rng_ick = {
.name = "rng_ick",
.parent = &security_l4_ick2,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_RNG_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2195,7 +2182,7 @@ static struct clk sha11_ick = {
.name = "sha11_ick",
.parent = &security_l4_ick2,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2206,7 +2193,7 @@ static struct clk des1_ick = {
.name = "des1_ick",
.parent = &security_l4_ick2,
.prcm_mod = CORE_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_DES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2218,7 +2205,7 @@ static struct clk dss1_alwon_fck = {
.name = "dss1_alwon_fck",
.parent = &dpll4_m4x2_ck,
.prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "dss_clkdm" },
@@ -2229,7 +2216,7 @@ static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
.parent = &omap_54m_fck,
.prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
@@ -2240,7 +2227,7 @@ static struct clk dss_96m_fck = {
.name = "dss_96m_fck",
.parent = &omap_96m_fck,
.prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "dss_clkdm" },
@@ -2251,7 +2238,7 @@ static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.parent = &sys_ck,
.prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "dss_clkdm" },
@@ -2263,7 +2250,7 @@ static struct clk dss_ick = {
.name = "dss_ick",
.parent = &l4_ick,
.prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "dss_clkdm" },
@@ -2276,7 +2263,7 @@ static struct clk cam_mclk = {
.name = "cam_mclk",
.parent = &dpll4_m5x2_ck,
.prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "cam_clkdm" },
@@ -2288,7 +2275,7 @@ static struct clk cam_ick = {
.name = "cam_ick",
.parent = &l4_ick,
.prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "cam_clkdm" },
@@ -2299,7 +2286,7 @@ static struct clk csi2_96m_fck = {
.name = "csi2_96m_fck",
.parent = &core_96m_fck,
.prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "cam_clkdm" },
@@ -2312,7 +2299,7 @@ static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.parent = &dpll5_m2_ck,
.prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "usbhost_clkdm" },
@@ -2323,7 +2310,7 @@ static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.parent = &omap_48m_fck,
.prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "usbhost_clkdm" },
@@ -2335,7 +2322,7 @@ static struct clk usbhost_ick = {
.name = "usbhost_ick",
.parent = &l4_ick,
.prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "usbhost_clkdm" },
@@ -2372,9 +2359,9 @@ static struct clk usim_fck = {
.name = "usim_fck",
.prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
.clksel = usim_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2387,9 +2374,9 @@ static struct clk gpt1_fck = {
.name = "gpt1_fck",
.prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2409,7 +2396,7 @@ static struct clk gpio1_dbck = {
.name = "gpio1_dbck",
.parent = &wkup_32k_fck,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2420,7 +2407,7 @@ static struct clk wdt2_fck = {
.name = "wdt2_fck",
.parent = &wkup_32k_fck,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2441,7 +2428,7 @@ static struct clk usim_ick = {
.name = "usim_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.clkdm = { .name = "prm_clkdm" },
@@ -2452,7 +2439,7 @@ static struct clk wdt2_ick = {
.name = "wdt2_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2463,7 +2450,7 @@ static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2474,7 +2461,7 @@ static struct clk gpio1_ick = {
.name = "gpio1_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2485,7 +2472,7 @@ static struct clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2496,7 +2483,7 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2507,7 +2494,7 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "prm_clkdm" },
@@ -2540,7 +2527,7 @@ static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &per_48m_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2551,9 +2538,9 @@ static struct clk gpt2_fck = {
.name = "gpt2_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2565,9 +2552,9 @@ static struct clk gpt3_fck = {
.name = "gpt3_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2579,9 +2566,9 @@ static struct clk gpt4_fck = {
.name = "gpt4_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2593,9 +2580,9 @@ static struct clk gpt5_fck = {
.name = "gpt5_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2607,9 +2594,9 @@ static struct clk gpt6_fck = {
.name = "gpt6_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2621,9 +2608,9 @@ static struct clk gpt7_fck = {
.name = "gpt7_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2635,9 +2622,9 @@ static struct clk gpt8_fck = {
.name = "gpt8_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2649,9 +2636,9 @@ static struct clk gpt9_fck = {
.name = "gpt9_fck",
.prcm_mod = OMAP3430_PER_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2671,7 +2658,7 @@ static struct clk gpio6_dbck = {
.name = "gpio6_dbck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2682,7 +2669,7 @@ static struct clk gpio5_dbck = {
.name = "gpio5_dbck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2693,7 +2680,7 @@ static struct clk gpio4_dbck = {
.name = "gpio4_dbck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2704,7 +2691,7 @@ static struct clk gpio3_dbck = {
.name = "gpio3_dbck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2715,7 +2702,7 @@ static struct clk gpio2_dbck = {
.name = "gpio2_dbck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2726,7 +2713,7 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &per_32k_alwon_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2746,7 +2733,7 @@ static struct clk gpio6_ick = {
.name = "gpio6_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2757,7 +2744,7 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2768,7 +2755,7 @@ static struct clk gpio4_ick = {
.name = "gpio4_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2779,7 +2766,7 @@ static struct clk gpio3_ick = {
.name = "gpio3_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2790,7 +2777,7 @@ static struct clk gpio2_ick = {
.name = "gpio2_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2801,7 +2788,7 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2812,7 +2799,7 @@ static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2823,7 +2810,7 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2834,7 +2821,7 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2845,7 +2832,7 @@ static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2856,7 +2843,7 @@ static struct clk gpt6_ick = {
.name = "gpt6_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2867,7 +2854,7 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2878,7 +2865,7 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2889,7 +2876,7 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2900,7 +2887,7 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2912,7 +2899,7 @@ static struct clk mcbsp2_ick = {
.id = 2,
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2924,7 +2911,7 @@ static struct clk mcbsp3_ick = {
.id = 3,
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2936,7 +2923,7 @@ static struct clk mcbsp4_ick = {
.id = 4,
.parent = &per_l4_ick,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2954,7 +2941,7 @@ static struct clk mcbsp2_src_fck = {
.id = 2,
.prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_reg = OMAP2_CONTROL_DEVCONF0,
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2967,7 +2954,7 @@ static struct clk mcbsp2_fck = {
.id = 2,
.parent = &mcbsp2_src_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -2979,7 +2966,7 @@ static struct clk mcbsp3_src_fck = {
.id = 3,
.prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -2992,7 +2979,7 @@ static struct clk mcbsp3_fck = {
.id = 3,
.parent = &mcbsp3_src_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -3004,7 +2991,7 @@ static struct clk mcbsp4_src_fck = {
.id = 4,
.prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
@@ -3017,7 +3004,7 @@ static struct clk mcbsp4_fck = {
.id = 4,
.parent = &mcbsp4_src_fck,
.prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.clkdm = { .name = "per_clkdm" },
@@ -3065,7 +3052,7 @@ static struct clk emu_src_ck = {
.name = "emu_src_ck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3090,7 +3077,7 @@ static struct clk pclk_fck = {
.name = "pclk_fck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
.clksel = pclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3114,7 +3101,7 @@ static struct clk pclkx2_fck = {
.name = "pclkx2_fck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
.clksel = pclkx2_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3131,7 +3118,7 @@ static struct clk atclk_fck = {
.name = "atclk_fck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
.clksel = atclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3143,7 +3130,7 @@ static struct clk traceclk_src_fck = {
.name = "traceclk_src_fck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3167,7 +3154,7 @@ static struct clk traceclk_fck = {
.name = "traceclk_fck",
.prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
.clksel = traceclk_clksel,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
@@ -3182,7 +3169,7 @@ static struct clk sr1_fck = {
.name = "sr1_fck",
.parent = &sys_ck,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_SR1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.clkdm = { .name = "prm_clkdm" },
@@ -3194,7 +3181,7 @@ static struct clk sr2_fck = {
.name = "sr2_fck",
.parent = &sys_ck,
.prcm_mod = WKUP_MOD,
- .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_SR2_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.clkdm = { .name = "prm_clkdm" },
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index bacadcb..7750bec 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -33,8 +33,7 @@
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
-#define OMAP3430_CM_CLKOUT_CTRL \
- OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+#define OMAP3430_CM_CLKOUT_CTRL_OFFSET 0x0070
/*
* Module specific CM registers from CM_BASE + domain offset
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 314b145..0843b88 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -252,7 +252,6 @@ static void __init __omap2_set_globals(void)
omap2_set_globals_memory(omap2_globals);
omap2_set_globals_control(omap2_globals);
omap2_set_globals_prcm(omap2_globals);
- omap2_set_globals_clock24xx(omap2_globals);
}
#endif
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 22db786..847b122 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -31,7 +31,7 @@ struct clksel {
};
struct dpll_data {
- void __iomem *mult_div1_reg;
+ u16 mult_div1_reg;
u32 mult_mask;
u32 div1_mask;
u16 last_rounded_m;
@@ -43,17 +43,17 @@ struct dpll_data {
u8 max_divider;
u32 max_tolerance;
struct clk *bypass_clk;
- void __iomem *control_reg;
+ u16 control_reg;
u32 enable_mask;
# if defined(CONFIG_ARCH_OMAP3)
- void __iomem *idlest_reg;
+ u16 idlest_reg;
u32 idlest_mask;
u32 freqsel_mask;
u8 modes;
u8 auto_recal_bit;
u8 recal_en_bit;
u8 recal_st_bit;
- void __iomem *autoidle_reg;
+ u16 autoidle_reg;
u32 autoidle_mask;
# endif
};
@@ -68,7 +68,7 @@ struct clk {
struct clk *parent;
unsigned long rate;
__u32 flags;
- void __iomem *enable_reg;
+ u16 enable_reg;
__u8 enable_bit;
__s8 usecount;
void (*recalc)(struct clk *);
@@ -79,7 +79,7 @@ struct clk {
void (*disable)(struct clk *);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
u8 fixed_div;
- void __iomem *clksel_reg;
+ u16 clksel_reg;
u32 clksel_mask;
const struct clksel *clksel;
struct dpll_data *dpll_data;
@@ -143,9 +143,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define DELAYED_APP (1 << 9) /* Delay application of clock */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
-#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
-#define OFFSET_GR_MOD (1 << 13) /* 24xx GR_MOD reg as offset */
-/* bits 14-20 are currently free */
+#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
+/* bits 13-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23)
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 09/11] OMAP2/3 clock: encode target IDLEST bits
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (7 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 08/11] OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 10/11] OMAP2/3 clock: clean up omap2_clk_wait_ready() Paul Walmsley
2009-01-28 19:18 ` [PATCH D 11/11] Fix omap1 clock issues Paul Walmsley
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: linux-omap, Paul Walmsley, Tony Lindgren, Rajendra Nayak
For each OMAP module that has a target IDLEST bit, add the appropriate
bits to the clock tree on both the module interface clock and the appropriate
functional clock. Add a new clock bit, "WAIT_READY", that indicates that
the clock code must wait for the clock's module to come out of idle after
both the target functional clock and interface clocks are enabled. Fix
some clock flag comments while there to indicate that clocks marked
as "3430ES2" clocks also are valid for later 3430 revisions.
Several OMAP3xxx clocks must be split into platform-specific variants,
since some early silicon revisions do not have target idle state bits
available. DSS, HSOTGUSB, and SSI clocks are affected. In the future, it
would be ideal to #ifdef out those clocks for kernels that don't need to
run on 3430ES1 chips to save memory.
This patch also includes a later fix for a bug that caused the clock
code to not wait for the DSS to come out of idle. Reported by Rajendra
Nayak <rnayak@ti.com>.
linux-omap source commits are e9ea612457bbf244d1a6fc38b08453d5a4ec7bf6,
a63efb1547ac35dcb0f007090396a3c7510eb691, and part of
9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock24xx.h | 194 +++++++++----
arch/arm/mach-omap2/clock34xx.h | 447 ++++++++++++++++++++++---------
arch/arm/mach-omap2/cm-regbits-24xx.h | 1
arch/arm/plat-omap/include/mach/clock.h | 8 -
4 files changed, 453 insertions(+), 197 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 178f46d..929a257 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -1233,10 +1233,11 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.parent = &core_l3_ck,
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- DELAYED_APP | CONFIG_PARTICIPANT,
+ DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .idlest_bit = OMAP24XX_ST_USB_SHIFT,
.clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
.clksel = usb_l4_ick_clksel,
@@ -1306,11 +1307,12 @@ static struct clk ssi_ssr_sst_fck = {
.name = "ssi_fck",
.parent = &core_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .idlest_bit = OMAP24XX_ST_SSI_SHIFT,
.clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_sst_fck_clksel,
@@ -1328,9 +1330,10 @@ static struct clk ssi_l4_ick = {
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .idlest_bit = OMAP24XX_ST_SSI_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1573,10 +1576,11 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &l4_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1601,10 +1605,11 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1627,10 +1632,11 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1653,10 +1659,11 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1679,10 +1686,11 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1705,10 +1713,11 @@ static struct clk gpt6_ick = {
.name = "gpt6_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT6_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1731,10 +1740,11 @@ static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT7_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1757,10 +1767,11 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT8_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1783,10 +1794,11 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT9_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1809,10 +1821,11 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT10_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1835,10 +1848,11 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT11_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1861,10 +1875,11 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPT12_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1888,10 +1903,11 @@ static struct clk mcbsp1_ick = {
.id = 1,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MCBSP1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1912,10 +1928,11 @@ static struct clk mcbsp2_ick = {
.id = 2,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MCBSP2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1936,10 +1953,11 @@ static struct clk mcbsp3_ick = {
.id = 3,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
+ .idlest_bit = OMAP2430_ST_MCBSP3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1960,10 +1978,11 @@ static struct clk mcbsp4_ick = {
.id = 4,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
+ .idlest_bit = OMAP2430_ST_MCBSP4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1984,10 +2003,11 @@ static struct clk mcbsp5_ick = {
.id = 5,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
+ .idlest_bit = OMAP2430_ST_MCBSP5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2009,9 +2029,10 @@ static struct clk mcspi1_ick = {
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
.clkdm = { .name = "core_l4_clkdm" },
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MCSPI1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2032,10 +2053,11 @@ static struct clk mcspi2_ick = {
.id = 2,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2056,10 +2078,11 @@ static struct clk mcspi3_ick = {
.id = 3,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .idlest_bit = OMAP2430_ST_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2079,10 +2102,11 @@ static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .idlest_bit = OMAP24XX_ST_UART1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2101,10 +2125,11 @@ static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .idlest_bit = OMAP24XX_ST_UART2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2123,10 +2148,11 @@ static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .idlest_bit = OMAP24XX_ST_UART3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2145,10 +2171,11 @@ static struct clk gpios_ick = {
.name = "gpios_ick",
.parent = &l4_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2156,10 +2183,11 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2168,10 +2196,11 @@ static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2180,10 +2209,11 @@ static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2192,10 +2222,11 @@ static struct clk sync_32k_ick = {
.parent = &l4_ck,
.prcm_mod = WKUP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ENABLE_ON_INIT,
+ ENABLE_ON_INIT | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .idlest_bit = OMAP24XX_ST_32KSYNC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2208,6 +2239,7 @@ static struct clk wdt1_ick = {
.clkdm = { .name = "prm_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .idlest_bit = OMAP24XX_ST_WDT1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2220,6 +2252,7 @@ static struct clk omapctrl_ick = {
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .idlest_bit = OMAP24XX_ST_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2227,10 +2260,11 @@ static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
.prcm_mod = WKUP_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP2430_EN_ICR_SHIFT,
+ .idlest_bit = OMAP2430_ST_ICR_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2265,10 +2299,11 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2276,10 +2311,11 @@ static struct clk wdt4_ick = {
.name = "wdt4_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .idlest_bit = OMAP24XX_ST_WDT4_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2298,10 +2334,11 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .idlest_bit = OMAP2420_ST_WDT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2309,10 +2346,11 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &func_32k_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .enable_bit = OMAP2420_ST_WDT3_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2320,10 +2358,11 @@ static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2331,10 +2370,11 @@ static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &func_96m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2342,10 +2382,11 @@ static struct clk mmc_ick = {
.name = "mmc_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .idlest_bit = OMAP2420_ST_MMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2353,10 +2394,11 @@ static struct clk mmc_fck = {
.name = "mmc_fck",
.parent = &func_96m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .idlest_bit = OMAP2420_ST_MMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2364,10 +2406,11 @@ static struct clk fac_ick = {
.name = "fac_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .idlest_bit = OMAP24XX_ST_FAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2375,10 +2418,11 @@ static struct clk fac_fck = {
.name = "fac_fck",
.parent = &func_12m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .idlest_bit = OMAP24XX_ST_FAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2386,10 +2430,11 @@ static struct clk eac_ick = {
.name = "eac_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .idlest_bit = OMAP2420_ST_EAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2397,10 +2442,11 @@ static struct clk eac_fck = {
.name = "eac_fck",
.parent = &func_96m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .idlest_bit = OMAP2420_ST_EAC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2408,10 +2454,11 @@ static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .idlest_bit = OMAP24XX_ST_HDQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2419,10 +2466,11 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &func_12m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .idlest_bit = OMAP24XX_ST_HDQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2431,10 +2479,11 @@ static struct clk i2c2_ick = {
.id = 2,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .idlest_bit = OMAP2420_ST_I2C2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2443,10 +2492,11 @@ static struct clk i2c2_fck = {
.id = 2,
.parent = &func_12m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .idlest_bit = OMAP2420_ST_I2C2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2467,10 +2517,11 @@ static struct clk i2c1_ick = {
.id = 1,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .idlest_bit = OMAP2420_ST_I2C1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2479,10 +2530,11 @@ static struct clk i2c1_fck = {
.id = 1,
.parent = &func_12m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .idlest_bit = OMAP2420_ST_I2C1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2527,10 +2579,11 @@ static struct clk vlynq_ick = {
.name = "vlynq_ick",
.parent = &core_l3_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2563,10 +2616,11 @@ static struct clk vlynq_fck = {
.name = "vlynq_fck",
.parent = &func_96m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
+ .flags = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT,
.init = &omap2_init_clksel_parent,
.clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
@@ -2580,10 +2634,11 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN3,
.enable_bit = OMAP2430_EN_SDRC_SHIFT,
+ .idlest_bit = OMAP2430_ST_SDRC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2591,10 +2646,11 @@ static struct clk des_ick = {
.name = "des_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_DES_SHIFT,
+ .idlest_bit = OMAP24XX_ST_DES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2602,10 +2658,11 @@ static struct clk sha_ick = {
.name = "sha_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_SHA_SHIFT,
+ .idlest_bit = OMAP24XX_ST_SHA_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2613,10 +2670,11 @@ static struct clk rng_ick = {
.name = "rng_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_RNG_SHIFT,
+ .idlest_bit = OMAP24XX_ST_RNG_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2624,10 +2682,11 @@ static struct clk aes_ick = {
.name = "aes_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_AES_SHIFT,
+ .idlest_bit = OMAP24XX_ST_AES_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2635,10 +2694,11 @@ static struct clk pka_ick = {
.name = "pka_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = OMAP24XX_CM_ICLKEN4,
.enable_bit = OMAP24XX_EN_PKA_SHIFT,
+ .idlest_bit = OMAP24XX_ST_PKA_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2646,10 +2706,11 @@ static struct clk usb_fck = {
.name = "usb_fck",
.parent = &func_48m_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = OMAP24XX_CM_FCLKEN2,
.enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .idlest_bit = OMAP24XX_ST_USB_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2657,10 +2718,11 @@ static struct clk usbhs_ick = {
.name = "usbhs_ick",
.parent = &core_l3_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_USBHS_SHIFT,
+ .idlest_bit = OMAP2430_ST_USBHS_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2668,10 +2730,11 @@ static struct clk mmchs1_ick = {
.name = "mmchs_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .idlest_bit = OMAP2430_ST_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2691,10 +2754,11 @@ static struct clk mmchs2_ick = {
.id = 1,
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .idlest_bit = OMAP2430_ST_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2714,10 +2778,11 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .idlest_bit = OMAP2430_ST_GPIO5_SHIFT,
.recalc = &followparent_recalc,
};
@@ -2736,10 +2801,11 @@ static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.parent = &l4_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP243X,
+ .flags = CLOCK_IN_OMAP243X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
+ .idlest_bit = OMAP2430_ST_MDM_INTC_SHIFT,
.recalc = &followparent_recalc,
};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index aef5049..70a1532 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1346,10 +1346,11 @@ static struct clk gpt10_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1361,10 +1362,11 @@ static struct clk gpt11_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1375,7 +1377,8 @@ static struct clk cpefuse_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = OMAP3430ES2_CM_FCLKEN3,
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1397,7 +1400,8 @@ static struct clk usbtll_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = OMAP3430ES2_CM_FCLKEN3,
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1420,7 +1424,8 @@ static struct clk mmchs3_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1432,7 +1437,8 @@ static struct clk mmchs2_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1443,7 +1449,8 @@ static struct clk mspro_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1454,7 +1461,8 @@ static struct clk mmchs1_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1466,7 +1474,8 @@ static struct clk i2c3_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1478,7 +1487,8 @@ static struct clk i2c2_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1490,7 +1500,8 @@ static struct clk i2c1_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1535,7 +1546,8 @@ static struct clk mcbsp5_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1560,7 +1572,8 @@ static struct clk mcbsp1_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1583,7 +1596,8 @@ static struct clk mcspi4_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1595,7 +1609,8 @@ static struct clk mcspi3_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1607,7 +1622,8 @@ static struct clk mcspi2_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1619,7 +1635,8 @@ static struct clk mcspi1_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1630,7 +1647,8 @@ static struct clk uart2_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_UART2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1641,18 +1659,21 @@ static struct clk uart1_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_UART1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
+/* XXX doublecheck: is this idle or standby? */
static struct clk fshostusb_fck = {
.name = "fshostusb_fck",
.parent = &core_48m_fck,
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
+ .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1674,7 +1695,8 @@ static struct clk hdq_fck = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_FCLKEN1,
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1696,7 +1718,7 @@ static const struct clksel ssi_ssr_clksel[] = {
{ .parent = NULL }
};
-static struct clk ssi_ssr_fck = {
+static struct clk ssi_ssr_fck_3430es1 = {
.name = "ssi_ssr_fck",
.init = &omap2_init_clksel_parent,
.prcm_mod = CORE_MOD,
@@ -1705,16 +1727,41 @@ static struct clk ssi_ssr_fck = {
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
-static struct clk ssi_sst_fck = {
+static struct clk ssi_ssr_fck_3430es2 = {
+ .name = "ssi_ssr_fck",
+ .init = &omap2_init_clksel_parent,
+ .prcm_mod = CORE_MOD,
+ .enable_reg = CM_FCLKEN1,
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
+ .clksel_reg = CM_CLKSEL,
+ .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
+ .clksel = ssi_ssr_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
+ .clkdm = { .name = "core_l4_clkdm" },
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* It's unfortunate that we need to duplicate this clock. */
+static struct clk ssi_sst_fck_3430es1 = {
.name = "ssi_sst_fck",
- .parent = &ssi_ssr_fck,
+ .parent = &ssi_ssr_fck_3430es1,
.fixed_div = 2,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "core_l4_clkdm" },
+ .recalc = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+ .name = "ssi_sst_fck",
+ .parent = &ssi_ssr_fck_3430es2,
+ .fixed_div = 2,
+ .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
@@ -1736,13 +1783,25 @@ static struct clk core_l3_ick = {
.recalc = &followparent_recalc,
};
-static struct clk hsotgusb_ick = {
+static struct clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick",
.parent = &core_l3_ick,
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "core_l3_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+ .name = "hsotgusb_ick",
+ .parent = &core_l3_ick,
+ .prcm_mod = CORE_MOD,
+ .enable_reg = CM_ICLKEN1,
+ .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1753,7 +1812,8 @@ static struct clk sdrc_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
- .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+ .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1784,7 +1844,8 @@ static struct clk pka_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_PKA_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_PKA_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1806,7 +1867,8 @@ static struct clk usbtll_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN3,
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1818,7 +1880,8 @@ static struct clk mmchs3_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1830,7 +1893,8 @@ static struct clk icr_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_ICR_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_ICR_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1841,7 +1905,8 @@ static struct clk aes2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_AES2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_AES2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1852,7 +1917,8 @@ static struct clk sha12_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1863,7 +1929,8 @@ static struct clk des2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_DES2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_DES2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1875,7 +1942,8 @@ static struct clk mmchs2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1886,7 +1954,8 @@ static struct clk mmchs1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1897,7 +1966,8 @@ static struct clk mspro_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1908,7 +1978,8 @@ static struct clk hdq_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1920,7 +1991,8 @@ static struct clk mcspi4_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1932,7 +2004,8 @@ static struct clk mcspi3_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1944,7 +2017,8 @@ static struct clk mcspi2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1956,7 +2030,8 @@ static struct clk mcspi1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1968,7 +2043,8 @@ static struct clk i2c3_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1980,7 +2056,8 @@ static struct clk i2c2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1992,7 +2069,8 @@ static struct clk i2c1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2003,7 +2081,8 @@ static struct clk uart2_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_UART2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2014,7 +2093,8 @@ static struct clk uart1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_UART1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2025,7 +2105,8 @@ static struct clk gpt11_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2036,7 +2117,8 @@ static struct clk gpt10_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2048,7 +2130,8 @@ static struct clk mcbsp5_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2060,7 +2143,8 @@ static struct clk mcbsp1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2071,7 +2155,8 @@ static struct clk fac_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
+ .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2082,7 +2167,8 @@ static struct clk mailboxes_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2093,7 +2179,8 @@ static struct clk omapctrl_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
- .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+ .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2109,20 +2196,33 @@ static struct clk ssi_l4_ick = {
.recalc = &followparent_recalc,
};
-static struct clk ssi_ick = {
+static struct clk ssi_ick_3430es1 = {
.name = "ssi_ick",
.parent = &ssi_l4_ick,
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430_EN_SSI_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
-/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
- * but l4_ick makes more sense to me */
+static struct clk ssi_ick_3430es2 = {
+ .name = "ssi_ick",
+ .parent = &ssi_l4_ick,
+ .prcm_mod = CORE_MOD,
+ .enable_reg = CM_ICLKEN1,
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
+ .clkdm = { .name = "core_l4_clkdm" },
+ .recalc = &followparent_recalc,
+};
+/*
+ * REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me
+ */
static const struct clksel usb_l4_clksel[] = {
{ .parent = &l4_ick, .rates = div2_rates },
{ .parent = NULL },
@@ -2135,10 +2235,11 @@ static struct clk usb_l4_ick = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_ICLKEN1,
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+ .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
- .flags = CLOCK_IN_OMAP3430ES1,
+ .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2162,7 +2263,8 @@ static struct clk aes1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_AES1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_AES1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2173,7 +2275,8 @@ static struct clk rng_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_RNG_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_RNG_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2184,7 +2287,8 @@ static struct clk sha11_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2195,19 +2299,33 @@ static struct clk des1_ick = {
.prcm_mod = CORE_MOD,
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP3430_EN_DES1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_DES1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
/* DSS */
-static struct clk dss1_alwon_fck = {
+static struct clk dss1_alwon_fck_3430es1 = {
.name = "dss1_alwon_fck",
.parent = &dpll4_m4x2_ck,
.prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "dss_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss1_alwon_fck_3430es2 = {
+ .name = "dss1_alwon_fck",
+ .parent = &dpll4_m4x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .prcm_mod = OMAP3430_DSS_MOD,
+ .enable_reg = CM_FCLKEN,
+ .enable_bit = OMAP3430_EN_DSS1_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2245,14 +2363,27 @@ static struct clk dss2_alwon_fck = {
.recalc = &followparent_recalc,
};
-static struct clk dss_ick = {
+static struct clk dss_ick_3430es1 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.parent = &l4_ick,
.prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "dss_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss_ick_3430es2 = {
+ /* Handles both L3 and L4 clocks */
+ .name = "dss_ick",
+ .parent = &l4_ick,
+ .prcm_mod = OMAP3430_DSS_MOD,
+ .enable_reg = CM_ICLKEN,
+ .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2312,7 +2443,8 @@ static struct clk usbhost_48m_fck = {
.prcm_mod = OMAP3430ES2_USBHOST_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2324,7 +2456,8 @@ static struct clk usbhost_ick = {
.prcm_mod = OMAP3430ES2_USBHOST_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2361,10 +2494,11 @@ static struct clk usim_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+ .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
.clksel = usim_clksel,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2376,10 +2510,11 @@ static struct clk gpt1_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2398,7 +2533,8 @@ static struct clk gpio1_dbck = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2409,7 +2545,8 @@ static struct clk wdt2_fck = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2422,15 +2559,14 @@ static struct clk wkup_l4_ick = {
.recalc = &followparent_recalc,
};
-/* 3430ES2 only */
-/* Never specifically named in the TRM, so we have to infer a likely name */
static struct clk usim_ick = {
.name = "usim_ick",
.parent = &wkup_l4_ick,
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
+ .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2441,7 +2577,8 @@ static struct clk wdt2_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2452,7 +2589,8 @@ static struct clk wdt1_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2463,7 +2601,8 @@ static struct clk gpio1_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2474,7 +2613,8 @@ static struct clk omap_32ksync_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2485,7 +2625,8 @@ static struct clk gpt12_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2496,7 +2637,8 @@ static struct clk gpt1_ick = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2529,7 +2671,8 @@ static struct clk uart3_fck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_UART3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2540,10 +2683,11 @@ static struct clk gpt2_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2554,10 +2698,11 @@ static struct clk gpt3_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2568,10 +2713,11 @@ static struct clk gpt4_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2582,10 +2728,11 @@ static struct clk gpt5_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2596,10 +2743,11 @@ static struct clk gpt6_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2610,10 +2758,11 @@ static struct clk gpt7_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2624,10 +2773,11 @@ static struct clk gpt8_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2638,10 +2788,11 @@ static struct clk gpt9_fck = {
.init = &omap2_init_clksel_parent,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
+ .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2660,7 +2811,8 @@ static struct clk gpio6_dbck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2671,7 +2823,8 @@ static struct clk gpio5_dbck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2682,7 +2835,8 @@ static struct clk gpio4_dbck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2693,7 +2847,8 @@ static struct clk gpio3_dbck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2704,7 +2859,8 @@ static struct clk gpio2_dbck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2715,7 +2871,8 @@ static struct clk wdt3_fck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2735,7 +2892,8 @@ static struct clk gpio6_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2746,7 +2904,8 @@ static struct clk gpio5_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2757,7 +2916,8 @@ static struct clk gpio4_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2768,7 +2928,8 @@ static struct clk gpio3_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2779,7 +2940,8 @@ static struct clk gpio2_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2790,7 +2952,8 @@ static struct clk wdt3_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2801,7 +2964,8 @@ static struct clk uart3_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_UART3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_UART3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2812,7 +2976,8 @@ static struct clk gpt9_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2823,7 +2988,8 @@ static struct clk gpt8_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2834,7 +3000,8 @@ static struct clk gpt7_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2845,7 +3012,8 @@ static struct clk gpt6_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2856,7 +3024,8 @@ static struct clk gpt5_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2867,7 +3036,8 @@ static struct clk gpt4_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2878,7 +3048,8 @@ static struct clk gpt3_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2889,7 +3060,8 @@ static struct clk gpt2_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2901,7 +3073,8 @@ static struct clk mcbsp2_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2913,7 +3086,8 @@ static struct clk mcbsp3_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2925,7 +3099,8 @@ static struct clk mcbsp4_ick = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2956,7 +3131,8 @@ static struct clk mcbsp2_fck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2981,7 +3157,8 @@ static struct clk mcbsp3_fck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -3006,7 +3183,8 @@ static struct clk mcbsp4_fck = {
.prcm_mod = OMAP3430_PER_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | WAIT_READY,
.clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -3171,7 +3349,8 @@ static struct clk sr1_fck = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_SR1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .idlest_bit = OMAP3430_ST_SR1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3183,7 +3362,8 @@ static struct clk sr2_fck = {
.prcm_mod = WKUP_MOD,
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_SR2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .idlest_bit = OMAP3430_ST_SR2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3198,11 +3378,12 @@ static struct clk sr_l4_ick = {
/* SECURE_32K_FCK clocks */
-/* XXX This clock no longer exists in 3430 TRM rev F */
+/* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
static struct clk gpt12_fck = {
.name = "gpt12_fck",
.parent = &secure_32k_fck,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
.clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3309,10 +3490,13 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&fshostusb_fck,
&core_12m_fck,
&hdq_fck,
- &ssi_ssr_fck,
- &ssi_sst_fck,
+ &ssi_ssr_fck_3430es1,
+ &ssi_ssr_fck_3430es2,
+ &ssi_sst_fck_3430es1,
+ &ssi_sst_fck_3430es2,
&core_l3_ick,
- &hsotgusb_ick,
+ &hsotgusb_ick_3430es1,
+ &hsotgusb_ick_3430es2,
&sdrc_ick,
&gpmc_fck,
&security_l3_ick,
@@ -3345,18 +3529,21 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&mailboxes_ick,
&omapctrl_ick,
&ssi_l4_ick,
- &ssi_ick,
+ &ssi_ick_3430es1,
+ &ssi_ick_3430es2,
&usb_l4_ick,
&security_l4_ick2,
&aes1_ick,
&rng_ick,
&sha11_ick,
&des1_ick,
- &dss1_alwon_fck,
+ &dss1_alwon_fck_3430es1,
+ &dss1_alwon_fck_3430es2,
&dss_tv_fck,
&dss_96m_fck,
&dss2_alwon_fck,
- &dss_ick,
+ &dss_ick_3430es1,
+ &dss_ick_3430es2,
&cam_mclk,
&cam_ick,
&csi2_96m_fck,
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 297a2fe..a9a0df5 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -147,6 +147,7 @@
/* CM_IDLEST3_CORE */
/* 2430 only */
+#define OMAP2430_ST_SDRC_SHIFT 2
#define OMAP2430_ST_SDRC_MASK (1 << 2)
/* CM_IDLEST4_CORE */
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 847b122..1b74119 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -71,6 +71,7 @@ struct clk {
u16 enable_reg;
__u8 enable_bit;
__s8 usecount;
+ u8 idlest_bit;
void (*recalc)(struct clk *);
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
@@ -144,7 +145,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
-/* bits 13-20 are currently free */
+#define WAIT_READY (1 << 13) /* wait for dev to leave idle */
+/* bits 14-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23)
@@ -154,14 +156,14 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
#define PARENT_CONTROLS_CLOCK (1 << 28)
#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
-#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
+#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2+ clocks only */
/* Clksel_rate flags */
#define DEFAULT_RATE (1 << 0)
#define RATE_IN_242X (1 << 1)
#define RATE_IN_243X (1 << 2)
#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
-#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
+#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2+ rates only */
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 10/11] OMAP2/3 clock: clean up omap2_clk_wait_ready()
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (8 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 09/11] OMAP2/3 clock: encode target IDLEST bits Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-28 19:18 ` [PATCH D 11/11] Fix omap1 clock issues Paul Walmsley
10 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: linux-omap, Paul Walmsley, Tony Lindgren, Anand Gadiyar,
Koen Kooi, Dirk Behme, Igor Stoppa, Richard Woodruff,
Jouni Högander
Simplify omap2_clk_wait_ready() to use the new idlest_bit field in
struct clk, rather than a hunk of conditionals.
Others who have contributed to the patches in this rollup by reporting
bugs, testing, or reviewing include:
- Anand Gadiyar <gadiyar@ti.com>
- Koen Kooi <k.kooi@student.utwente.nl>
- Dirk Behme <dirk.behme@googlemail.com>
- Igor Stoppa <igor.stoppa@nokia.com>
- Richard Woodruff <r-woodruff2@ti.com>
- Jouni Högander <jouni.hogander@nokia.com>
More information can be found at the original source commits below.
linux-omap source commits are 999ccb505e4fa5720add74589fe747affcd7aa81,
f4c458db2b615037f7c1fd91d238f6420e7b8f77,
e2d8a430aab87fdc47b7f01de804e17b8960042d,
201fb6b950b41a798aa54ee78588ac68aed28a0a,
205f37af718984ec67444bccc888cd575531bce1,
0fe3bd3fb03ab35063b1d17070b24bfa007896c3,
3fa8636974ca1c04797781fb300c2e29ec18c3a8,
6f55ed7c13d655189da305207cf323041e4bcc4d, and
fd183f64d5325d727124d88c50b401a7da9c89c1.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Anand Gadiyar <gadiyar@ti.com>
Cc: Koen Kooi <k.kooi@student.utwente.nl>
Cc: Dirk Behme <dirk.behme@googlemail.com>
Cc: Igor Stoppa <igor.stoppa@nokia.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
---
arch/arm/mach-omap2/clock.c | 93 ++++++++++++++++++++-------------------
arch/arm/mach-omap2/clock.h | 3 +
arch/arm/mach-omap2/clock24xx.c | 10 ----
3 files changed, 51 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index dff4eaa..0cd4761 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -70,6 +70,13 @@
#define DPLL_FINT_UNDERFLOW -1
#define DPLL_FINT_INVALID -2
+/* Bitmask to isolate the register type of clk.enable_reg */
+#define PRCM_REGTYPE_MASK 0xf0
+/* various CM register type options */
+#define CM_FCLKEN_REGTYPE 0x00
+#define CM_ICLKEN_REGTYPE 0x10
+#define CM_IDLEST_REGTYPE 0x20
+
u8 cpu_mask;
/*-------------------------------------------------------------------------
@@ -300,17 +307,18 @@ void omap2_fixed_divisor_recalc(struct clk *clk)
/**
* omap2_wait_clock_ready - wait for clock to enable
- * @reg: physical address of clock IDLEST register
+ * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
+ * @reg_index: offset of CM register address from prcm_mod
* @mask: value to mask against to determine if the clock is active
* @name: name of the clock (for printk)
*
* Returns 1 if the clock enabled in time, or 0 if it failed to enable
* in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
*/
-int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
+int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
+ const char *name)
{
- int i = 0;
- int ena = 0;
+ int i = 0, ena = 0;
/*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
@@ -322,7 +330,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
ena = 0;
/* Wait for lock */
- while (((__raw_readl(reg) & mask) != ena) &&
+ while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
(i++ < MAX_CLOCK_ENABLE_WAIT)) {
udelay(1);
}
@@ -333,61 +341,56 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
name, MAX_CLOCK_ENABLE_WAIT);
-
return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
};
/*
- * Note: We don't need special code here for INVERT_ENABLE
- * for the time being since INVERT_ENABLE only applies to clocks enabled by
- * CM_CLKEN_PLL
+ * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
+ * @clk: struct clk * recently enabled to indicate the module to test
+ *
+ * Wait for an OMAP module with a target idle state bit to come out of
+ * idle once both its interface clock and primary functional clock are
+ * both enabled. Any register read or write to the device before it
+ * returns from idle will cause an abort. Not all modules have target
+ * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
+ * wait for those. No return value.
+ *
+ * We don't need special code here for INVERT_ENABLE for the time
+ * being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL.
+ *
+ * REVISIT: This function is misnamed: it should be something like
+ * "omap2_module_wait_ready", and in the long-term, it does not belong
+ * in the clock framework. It also shouldn't be doing register
+ * arithmetic to determine the companion clock.
*/
static void omap2_clk_wait_ready(struct clk *clk)
{
- void __iomem *other_reg, *st_reg;
- u16 reg;
- u32 bit;
+ u16 other_reg, idlest_reg;
+ u32 other_bit;
- /*
- * REVISIT: This code is pretty ugly. It would be nice to generalize
- * it and pull it into struct clk itself somehow.
- */
- reg = clk->enable_reg;
- if (((reg & 0xff) >= CM_FCLKEN1) &&
- ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
- other_reg = (void __iomem *)((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
- else if (((reg & 0xff) >= CM_ICLKEN1) &&
- ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
- other_reg = (void __iomem *)((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
- else
+ if (!(clk->flags & WAIT_READY))
return;
- /* REVISIT: What are the appropriate exclusions for 34XX? */
- /* No check for DSS or cam clocks */
- if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
- if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
- clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
- clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
- return;
- }
+ /* If we are enabling an iclk, also test the fclk; and vice versa */
+ other_bit = 1 << clk->enable_bit;
+ other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
- /* REVISIT: What are the appropriate exclusions for 34XX? */
- /* OMAP3: ignore DSS-mod clocks */
- if (cpu_is_omap34xx() &&
- ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
- (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
- clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
- return;
+ if (clk->enable_reg & CM_ICLKEN_REGTYPE)
+ other_reg |= CM_FCLKEN_REGTYPE;
+ else
+ other_reg |= CM_ICLKEN_REGTYPE;
- /* Check if both functional and interface clocks
- * are running. */
- bit = 1 << clk->enable_bit;
- if (!(__raw_readl(other_reg) & bit))
+ /* Ensure functional and interface clocks are running. */
+ if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
return;
- st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
- omap2_wait_clock_ready(st_reg, bit, clk->name);
+ idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
+ idlest_reg |= CM_IDLEST_REGTYPE;
+
+ omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
+ clk->name);
}
/* Enables clock without considering parent dependencies or use count
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4dbd582..faff95e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -64,7 +64,8 @@ void omap2_fixed_divisor_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk);
-int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+int omap2_wait_clock_ready(s16 prcm_mod, u16 idlest_reg, u32 cval,
+ const char *name);
void omap2_clk_prepare_for_reboot(void);
extern u8 cpu_mask;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 2047c06..e66287f 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -107,7 +107,6 @@ static void omap2_disable_osc_ck(struct clk *clk)
static int omap2_clk_fixed_enable(struct clk *clk)
{
u32 cval, apll_mask;
- void __iomem *idlest;
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
@@ -125,14 +124,7 @@ static int omap2_clk_fixed_enable(struct clk *clk)
else if (clk == &apll54_ck)
cval = OMAP24XX_ST_54M_APLL;
- if (cpu_is_omap242x())
- idlest = (__force void __iomem *)OMAP2420_CM_REGADDR(PLL_MOD,
- CM_IDLEST);
- else
- idlest = (__force void __iomem *)OMAP2430_CM_REGADDR(PLL_MOD,
- CM_IDLEST);
-
- omap2_wait_clock_ready(idlest, cval, clk->name);
+ omap2_wait_clock_ready(PLL_MOD, CM_IDLEST, cval, clk->name);
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH D 11/11] Fix omap1 clock issues
2009-01-28 19:18 [PATCH D 00/11] OMAP clock, D of F: clock code cleanup Paul Walmsley
` (9 preceding siblings ...)
2009-01-28 19:18 ` [PATCH D 10/11] OMAP2/3 clock: clean up omap2_clk_wait_ready() Paul Walmsley
@ 2009-01-28 19:18 ` Paul Walmsley
2009-01-29 14:37 ` Russell King - ARM Linux
10 siblings, 1 reply; 25+ messages in thread
From: Paul Walmsley @ 2009-01-28 19:18 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: linux-omap, Tony Lindgren, Paul Walmsley
From: Tony Lindgren <tony@atomide.com>
This fixes booting, and is a step toward fixing things properly:
- Make enable_reg u32 instead of u16
- Get rid of VIRTUAL_IO_ADDRESS for clocks
- Use __raw_read/write instead of omap_read/write for clock registers
This patch adds a bunch of compile warnings until omap1 clock
also uses offsets.
linux-omap source commit is 9d1dff8638c9e96a401e1885f9948662e9ff9636.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap1/clock.c | 77 +++++++++----------------------
arch/arm/mach-omap1/clock.h | 76 +++++++++++++++----------------
arch/arm/plat-omap/include/mach/clock.h | 4 +-
3 files changed, 62 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5fba207..4d0c444 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -41,7 +41,7 @@ static void omap1_watchdog_recalc(struct clk * clk)
static void omap1_uart_recalc(struct clk * clk)
{
- unsigned int val = omap_readl(clk->enable_reg);
+ unsigned int val = __raw_readl(clk->enable_reg);
if (val & clk->enable_bit)
clk->rate = 48000000;
else
@@ -372,14 +372,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
{
unsigned int val;
- val = omap_readl(clk->enable_reg);
+ val = __raw_readl(clk->enable_reg);
if (rate == 12000000)
val &= ~(1 << clk->enable_bit);
else if (rate == 48000000)
val |= (1 << clk->enable_bit);
else
return -EINVAL;
- omap_writel(val, clk->enable_reg);
+ __raw_writel(val, clk->enable_reg);
clk->rate = rate;
return 0;
@@ -398,8 +398,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
else
ratio_bits = (dsor - 2) << 2;
- ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
+ __raw_writew(ratio_bits, clk->enable_reg);
return 0;
}
@@ -440,8 +440,8 @@ static void omap1_init_ext_clk(struct clk * clk)
__u16 ratio_bits;
/* Determine current rate and ensure clock is based on 96MHz APLL */
- ratio_bits = omap_readw(clk->enable_reg) & ~1;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits = __raw_readw(clk->enable_reg) & ~1;
+ __raw_writew(ratio_bits, clk->enable_reg);
ratio_bits = (ratio_bits & 0xfc) >> 2;
if (ratio_bits > 6)
@@ -506,25 +506,13 @@ static int omap1_clk_enable_generic(struct clk *clk)
}
if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
+ regval32 = __raw_readl(clk->enable_reg);
+ regval32 |= (1 << clk->enable_bit);
+ __raw_writel(regval32, clk->enable_reg);
} else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
+ regval16 = __raw_readw(clk->enable_reg);
+ regval16 |= (1 << clk->enable_bit);
+ __raw_writew(regval16, clk->enable_reg);
}
return 0;
@@ -539,25 +527,13 @@ static void omap1_clk_disable_generic(struct clk *clk)
return;
if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
+ regval32 = __raw_readl(clk->enable_reg);
+ regval32 &= ~(1 << clk->enable_bit);
+ __raw_writel(regval32, clk->enable_reg);
} else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
+ regval16 = __raw_readw(clk->enable_reg);
+ regval16 &= ~(1 << clk->enable_bit);
+ __raw_writew(regval16, clk->enable_reg);
}
}
@@ -632,17 +608,10 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
}
/* Is the clock already disabled? */
- if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readl(clk->enable_reg);
- else
- regval32 = omap_readl(clk->enable_reg);
- } else {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readw(clk->enable_reg);
- else
- regval32 = omap_readw(clk->enable_reg);
- }
+ if (clk->flags & ENABLE_REG_32BIT)
+ regval32 = __raw_readl(clk->enable_reg);
+ else
+ regval32 = __raw_readw(clk->enable_reg);
if ((regval32 & (1 << clk->enable_bit)) == 0)
return;
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index c1dcdf1..43f6ce8 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -174,7 +174,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
ENABLE_REG_32BIT | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -188,7 +188,7 @@ static struct clk sossi_ck = {
.parent = &ck_dpll1out.clk,
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
.enable_bit = 16,
.recalc = &omap1_sossi_recalc,
.set_rate = &omap1_set_sossi_rate,
@@ -215,7 +215,7 @@ static struct arm_idlect1_clk armper_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_CKCTL |
CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -229,7 +229,7 @@ static struct clk arm_gpio_ck = {
.name = "arm_gpio_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_GPIOCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -242,7 +242,7 @@ static struct arm_idlect1_clk armxor_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -257,7 +257,7 @@ static struct arm_idlect1_clk armtim_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_TIMCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -272,7 +272,7 @@ static struct arm_idlect1_clk armwdt_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_WDTCK,
.recalc = &omap1_watchdog_recalc,
.enable = &omap1_clk_enable_generic,
@@ -300,7 +300,7 @@ static struct clk dsp_ck = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
- .enable_reg = (void __iomem *)ARM_CKCTL,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
.enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -323,8 +323,8 @@ static struct clk dspper_ck = {
.name = "dspper_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- RATE_CKCTL | VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ RATE_CKCTL,
+ .enable_reg = IOMEM(DSP_IDLECT2),
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc_dsp_domain,
@@ -336,9 +336,8 @@ static struct clk dspper_ck = {
static struct clk dspxor_ck = {
.name = "dspxor_ck",
.parent = &ck_ref,
- .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+ .enable_reg = IOMEM(DSP_IDLECT2),
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_dsp_domain,
@@ -348,9 +347,8 @@ static struct clk dspxor_ck = {
static struct clk dsptim_ck = {
.name = "dsptim_ck",
.parent = &ck_ref,
- .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+ .enable_reg = IOMEM(DSP_IDLECT2),
.enable_bit = EN_DSPTIMCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_dsp_domain,
@@ -404,7 +402,7 @@ static struct clk l3_ocpi_ck = {
.name = "l3_ocpi_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_OCPI_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -415,7 +413,7 @@ static struct clk tc1_ck = {
.name = "tc1_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC1_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -426,7 +424,7 @@ static struct clk tc2_ck = {
.name = "tc2_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC2_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -459,7 +457,7 @@ static struct arm_idlect1_clk api_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_APICK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -474,7 +472,7 @@ static struct arm_idlect1_clk lb_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LBCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -505,7 +503,7 @@ static struct clk lcd_ck_16xx = {
.name = "lcd_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -519,7 +517,7 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
RATE_CKCTL | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -537,7 +535,7 @@ static struct clk uart1_1510 = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
@@ -553,7 +551,7 @@ static struct uart_clk uart1_16xx = {
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 29,
.enable = &omap1_clk_enable_uart_functional,
.disable = &omap1_clk_disable_uart_functional,
@@ -569,7 +567,7 @@ static struct clk uart2_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
@@ -585,7 +583,7 @@ static struct clk uart3_1510 = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
@@ -601,7 +599,7 @@ static struct uart_clk uart3_16xx = {
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 31,
.enable = &omap1_clk_enable_uart_functional,
.disable = &omap1_clk_disable_uart_functional,
@@ -615,7 +613,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
.rate = 6000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
+ .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
.enable_bit = USB_MCLK_EN_BIT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -627,7 +625,7 @@ static struct clk usb_hhc_ck1510 = {
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = USB_HOST_HHC_UHOST_EN,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -640,7 +638,7 @@ static struct clk usb_hhc_ck16xx = {
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
.flags = CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
+ .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
.enable_bit = 8 /* UHOST_EN */,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -651,7 +649,7 @@ static struct clk usb_dc_ck = {
/* Direct from ULPD, no parent */
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
- .enable_reg = (void __iomem *)SOFT_REQ_REG,
+ .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 4,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -661,9 +659,9 @@ static struct clk mclk_1510 = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
- .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
- .enable_reg = (void __iomem *)SOFT_REQ_REG,
- .enable_bit = 6,
+ .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
+ .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+ .enable_bit = 6,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
@@ -672,7 +670,7 @@ static struct clk mclk_16xx = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
+ .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
.enable_bit = COM_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
@@ -694,7 +692,7 @@ static struct clk bclk_16xx = {
.name = "bclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
+ .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
@@ -711,7 +709,7 @@ static struct clk mmc1_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 23,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -725,7 +723,7 @@ static struct clk mmc2_ck = {
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 20,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 1b74119..e793616 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -68,7 +68,7 @@ struct clk {
struct clk *parent;
unsigned long rate;
__u32 flags;
- u16 enable_reg;
+ u32 enable_reg;
__u8 enable_bit;
__s8 usecount;
u8 idlest_bit;
@@ -138,7 +138,7 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
+
#define CLOCK_IDLE_CONTROL (1 << 7)
#define CLOCK_NO_IDLE_PARENT (1 << 8)
#define DELAYED_APP (1 << 9) /* Delay application of clock */
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH D 11/11] Fix omap1 clock issues
2009-01-28 19:18 ` [PATCH D 11/11] Fix omap1 clock issues Paul Walmsley
@ 2009-01-29 14:37 ` Russell King - ARM Linux
2009-01-30 7:58 ` Paul Walmsley
2009-02-06 21:19 ` Paul Walmsley
0 siblings, 2 replies; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-01-29 14:37 UTC (permalink / raw)
To: Paul Walmsley; +Cc: linux-arm-kernel, linux-kernel, linux-omap, Tony Lindgren
On Wed, Jan 28, 2009 at 12:18:48PM -0700, Paul Walmsley wrote:
> From: Tony Lindgren <tony@atomide.com>
>
> This fixes booting, and is a step toward fixing things properly:
>
> - Make enable_reg u32 instead of u16
No, you're passing this to __raw_read/write, so it needs to be
void __iomem *, not u32. If there's another patch doing that it
needs to be combined with this one. The miniscule details of
fixes upon fixes aren't interesting for submission purposes, and
just adds extra unnecessary review load for upstream people.
Ditto for anything else which is passed to __raw_read/write*.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 11/11] Fix omap1 clock issues
2009-01-29 14:37 ` Russell King - ARM Linux
@ 2009-01-30 7:58 ` Paul Walmsley
2009-02-06 21:19 ` Paul Walmsley
1 sibling, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-01-30 7:58 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel, linux-kernel, linux-omap, Tony Lindgren
On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
> On Wed, Jan 28, 2009 at 12:18:48PM -0700, Paul Walmsley wrote:
> > From: Tony Lindgren <tony@atomide.com>
> >
> > This fixes booting, and is a step toward fixing things properly:
> >
> > - Make enable_reg u32 instead of u16
>
> No, you're passing this to __raw_read/write, so it needs to be
> void __iomem *, not u32. If there's another patch doing that it
> needs to be combined with this one. The miniscule details of
> fixes upon fixes aren't interesting for submission purposes, and
> just adds extra unnecessary review load for upstream people.
>
> Ditto for anything else which is passed to __raw_read/write*.
Will build a revised patch for this and pass it to Tony for a boot test,
then repost.
- Paul
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 11/11] Fix omap1 clock issues
2009-01-29 14:37 ` Russell King - ARM Linux
2009-01-30 7:58 ` Paul Walmsley
@ 2009-02-06 21:19 ` Paul Walmsley
2009-02-06 21:44 ` Russell King - ARM Linux
1 sibling, 1 reply; 25+ messages in thread
From: Paul Walmsley @ 2009-02-06 21:19 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel, linux-kernel, linux-omap, Tony Lindgren
Hello Russell,
On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
> On Wed, Jan 28, 2009 at 12:18:48PM -0700, Paul Walmsley wrote:
> > From: Tony Lindgren <tony@atomide.com>
> >
> > This fixes booting, and is a step toward fixing things properly:
> >
> > - Make enable_reg u32 instead of u16
>
> No, you're passing this to __raw_read/write, so it needs to be
> void __iomem *, not u32. If there's another patch doing that it
> needs to be combined with this one. The miniscule details of
> fixes upon fixes aren't interesting for submission purposes, and
> just adds extra unnecessary review load for upstream people.
>
> Ditto for anything else which is passed to __raw_read/write*.
The patch below is a replacement for D 11. Thanks to Tony for helping
debug this patch.
- Paul
From: Tony Lindgren <tony@atomide.com>
Date: Fri, 6 Feb 2009 12:14:14 -0700
Subject: [PATCH] Fix omap1 clock issues
This fixes booting, and is a step toward fixing things properly:
- Get rid of VIRTUAL_IO_ADDRESS for clocks
- Use __raw_read/write instead of omap_read/write for clock registers
[paul@pwsan.com: This patch has been updated to use offsets for OMAP1
clock enable registers, to resolve all current sparse warnings with the
clock code, and to convert most magic constants into symbolic macros.
This revision based on review feedback from Russell King
<linux@arm.linux.org.uk>]
linux-omap source commit is 9d1dff8638c9e96a401e1885f9948662e9ff9636.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
arch/arm/mach-omap1/clock.c | 175 +++++++++++++++------------
arch/arm/mach-omap1/clock.h | 163 ++++++++++++++++----------
arch/arm/plat-omap/include/mach/clock.h | 8 +-
arch/arm/plat-omap/include/mach/hardware.h | 67 ++++++++---
arch/arm/plat-omap/include/mach/io.h | 3 +
arch/arm/plat-omap/include/mach/usb.h | 4 +-
6 files changed, 263 insertions(+), 157 deletions(-)
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5fba207..274a07c 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -30,10 +30,84 @@
__u32 arm_idlect1_mask;
+/*
+ * OMAP1_MPU_BASE_TO_MOD_OFFS is an additional offset for enable_reg
+ * address computation. It allows us to keep mod_offs short (16 bits)
+ * while keeping OMAP1_MPU_BASE consistent with the OMAP1
+ * documentation.
+ */
+#define OMAP1_MPU_BASE_TO_MOD_OFFS 0x0ff00000
+
/*-------------------------------------------------------------------------
* Omap1 specific clock functions
*-------------------------------------------------------------------------*/
+/**
+ * omap1_clk_get_enable_addr - return enable_reg IO addr from offsets in clk
+ * @clk: struct clk * to return an enable_reg address for
+ *
+ * Return the virtual address of the clock enable register for the clock
+ * @clk.
+ */
+static void __iomem *omap1_clk_get_enable_addr(struct clk *clk)
+{
+ u32 b;
+
+ WARN(!clk->mod_offs, "clock: %s: missing mod_offs\n", clk->name);
+
+ if (clk->flags & OMAP1_DSP_CLOCK)
+ b = OMAP1_DSP_IO_BASE;
+ else
+ b = OMAP1_MPU_BASE + OMAP1_MPU_BASE_TO_MOD_OFFS;
+
+ b += (clk->mod_offs << 8);
+ b += clk->enable_reg;
+
+ return OMAP1_IO_ADDRESS(b);
+}
+
+/**
+ * omap1_read_enable_reg - return contents of the clk's enable_reg register
+ * @clk: struct clk *
+ *
+ * Return the contents of the enable_reg register for clk @clk.
+ * Always returns a 32-bit value. For clock registers that are only
+ * 16 bits wide, the register value will be in the lower 16 bits of
+ * the return value.
+ */
+static u32 omap1_read_enable_reg(struct clk *clk)
+{
+ void __iomem *r;
+
+ r = omap1_clk_get_enable_addr(clk);
+
+ if (clk->flags & ENABLE_REG_32BIT)
+ return __raw_readl(r);
+ else
+ return __raw_readw(r);
+}
+
+/**
+ * omap1_write_enable_reg - write a value to the clk's enable_reg
+ * @v: value to write (32 bits)
+ * @clk: struct clk *
+ *
+ * Write @v to the register referenced by the @clk enable_reg. For
+ * 16-bit wide clock registers, the lower 16 bits of @v .are written.
+ * No return value.
+ */
+static void omap1_write_enable_reg(u32 v, struct clk *clk)
+{
+ void __iomem *r;
+
+ r = omap1_clk_get_enable_addr(clk);
+
+ if (clk->flags & ENABLE_REG_32BIT)
+ __raw_writel(v, r);
+ else
+ __raw_writew((v & 0xffff), r);
+}
+
static void omap1_watchdog_recalc(struct clk * clk)
{
clk->rate = clk->parent->rate / 14;
@@ -41,7 +115,7 @@ static void omap1_watchdog_recalc(struct clk * clk)
static void omap1_uart_recalc(struct clk * clk)
{
- unsigned int val = omap_readl(clk->enable_reg);
+ unsigned int val = omap1_read_enable_reg(clk);
if (val & clk->enable_bit)
clk->rate = 48000000;
else
@@ -372,14 +446,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
{
unsigned int val;
- val = omap_readl(clk->enable_reg);
+ val = omap1_read_enable_reg(clk);
if (rate == 12000000)
val &= ~(1 << clk->enable_bit);
else if (rate == 48000000)
val |= (1 << clk->enable_bit);
else
return -EINVAL;
- omap_writel(val, clk->enable_reg);
+ omap1_write_enable_reg(val, clk);
clk->rate = rate;
return 0;
@@ -398,8 +472,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
else
ratio_bits = (dsor - 2) << 2;
- ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits |= omap1_read_enable_reg(clk) & ~0xfd;
+ omap1_write_enable_reg(ratio_bits, clk);
return 0;
}
@@ -440,8 +514,8 @@ static void omap1_init_ext_clk(struct clk * clk)
__u16 ratio_bits;
/* Determine current rate and ensure clock is based on 96MHz APLL */
- ratio_bits = omap_readw(clk->enable_reg) & ~1;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits = omap1_read_enable_reg(clk) & ~1;
+ omap1_write_enable_reg(ratio_bits, clk);
ratio_bits = (ratio_bits & 0xfc) >> 2;
if (ratio_bits > 6)
@@ -493,72 +567,28 @@ static void omap1_clk_disable(struct clk *clk)
static int omap1_clk_enable_generic(struct clk *clk)
{
- __u16 regval16;
- __u32 regval32;
+ u32 v;
if (clk->flags & ALWAYS_ENABLED)
return 0;
- if (unlikely(clk->enable_reg == NULL)) {
- printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
- clk->name);
- return -EINVAL;
- }
-
- if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
- } else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
- }
+ v = omap1_read_enable_reg(clk);
+ v |= (1 << clk->enable_bit);
+ omap1_write_enable_reg(v, clk);
return 0;
}
static void omap1_clk_disable_generic(struct clk *clk)
{
- __u16 regval16;
- __u32 regval32;
+ u32 v;
- if (clk->enable_reg == NULL)
- return;
+ if (clk->flags & ALWAYS_ENABLED)
+ return 0;
- if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
- } else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
- }
+ v = omap1_read_enable_reg(clk);
+ v &= ~(1 << clk->enable_bit);
+ omap1_write_enable_reg(v, clk);
}
static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
@@ -621,30 +651,19 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
static void __init omap1_clk_disable_unused(struct clk *clk)
{
- __u32 regval32;
+ u32 v;
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
- if (clk->enable_reg == DSP_IDLECT2) {
+ if (clk->enable_reg == DSP_IDLECT2_OFFSET) {
printk(KERN_INFO "Skipping reset check for DSP domain "
"clock \"%s\"\n", clk->name);
return;
}
/* Is the clock already disabled? */
- if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readl(clk->enable_reg);
- else
- regval32 = omap_readl(clk->enable_reg);
- } else {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readw(clk->enable_reg);
- else
- regval32 = omap_readw(clk->enable_reg);
- }
-
- if ((regval32 & (1 << clk->enable_bit)) == 0)
+ v = omap1_read_enable_reg(clk);
+ if ((v & (1 << clk->enable_bit)) == 0)
return;
/* FIXME: This clock seems to be necessary but no-one
@@ -690,8 +709,8 @@ int __init omap1_clk_init(void)
#endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
- reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
- omap_writew(reg, SOFT_REQ_REG);
+ reg = omap_readw(ULPD_SOFT_REQ) & (1 << 4);
+ omap_writew(reg, ULPD_SOFT_REQ);
if (!cpu_is_omap15xx())
omap_writew(0, SOFT_REQ_REG2);
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index c1dcdf1..016d7eb 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -98,9 +98,19 @@ struct arm_idlect1_clk {
#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
-#define SOFT_REQ_REG 0xfffe0834
#define SOFT_REQ_REG2 0xfffe0880
+/* Offsets for OMAP1 modules that contain clock control registers */
+
+/* DSP offsets are shifted left 8 and added to OMAP1_DSP_IO_BASE */
+#define DSP_CONFIG_OFFS 0x0080 /* = e1008000 */
+
+/* MPU offsets are shifted left 8 and added to OMAP1_MPU_BASE + 0x0ff00000 */
+#define MPU_OTG_OFFS 0x0b04 /* = fffb0400 */
+#define MPU_ULPD_OFFS 0x0e08 /* = fffe0800 */
+#define MPU_CONF_OFFS 0x0e10 /* = fffe1000 */
+#define MPU_CLKGEN_OFFS 0x0ece /* = fffece00 */
+
/*-------------------------------------------------------------------------
* Omap1 MPU rate table
*-------------------------------------------------------------------------*/
@@ -174,13 +184,14 @@ static struct arm_idlect1_clk ck_dpll1out = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
ENABLE_REG_32BIT | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 12,
+ .idlect_shift = IDL_CLKOUT_ARM_SHIFT, /* XXX duplicate? */
};
static struct clk sossi_ck = {
@@ -188,8 +199,9 @@ static struct clk sossi_ck = {
.parent = &ck_dpll1out.clk,
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
- .enable_bit = 16,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_1_OFFSET,
+ .enable_bit = CONF_MOD_SOSSI_CLK_EN_R_SHIFT,
.recalc = &omap1_sossi_recalc,
.set_rate = &omap1_set_sossi_rate,
.enable = &omap1_clk_enable_generic,
@@ -215,21 +227,23 @@ static struct arm_idlect1_clk armper_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_CKCTL |
CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 2,
+ .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
};
static struct clk arm_gpio_ck = {
.name = "arm_gpio_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_GPIOCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -242,13 +256,14 @@ static struct arm_idlect1_clk armxor_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 1,
+ .idlect_shift = IDLXORP_ARM_SHIFT,
};
static struct arm_idlect1_clk armtim_ck = {
@@ -257,13 +272,14 @@ static struct arm_idlect1_clk armtim_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_TIMCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 9,
+ .idlect_shift = IDLTIM_ARM_SHIFT,
};
static struct arm_idlect1_clk armwdt_ck = {
@@ -272,13 +288,14 @@ static struct arm_idlect1_clk armwdt_ck = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_WDTCK,
.recalc = &omap1_watchdog_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 0,
+ .idlect_shift = IDLWDT_ARM_SHIFT,
};
static struct clk arminth_ck16xx = {
@@ -300,7 +317,8 @@ static struct clk dsp_ck = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
- .enable_reg = (void __iomem *)ARM_CKCTL,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_CKCTL_OFFSET,
.enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -323,8 +341,9 @@ static struct clk dspper_ck = {
.name = "dspper_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- RATE_CKCTL | VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ RATE_CKCTL | OMAP1_DSP_CLOCK,
+ .mod_offs = DSP_CONFIG_OFFS,
+ .enable_reg = DSP_IDLECT2_OFFSET,
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc_dsp_domain,
@@ -337,8 +356,9 @@ static struct clk dspxor_ck = {
.name = "dspxor_ck",
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ OMAP1_DSP_CLOCK,
+ .mod_offs = DSP_CONFIG_OFFS,
+ .enable_reg = DSP_IDLECT2_OFFSET,
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_dsp_domain,
@@ -349,8 +369,9 @@ static struct clk dsptim_ck = {
.name = "dsptim_ck",
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
- VIRTUAL_IO_ADDRESS,
- .enable_reg = DSP_IDLECT2,
+ OMAP1_DSP_CLOCK,
+ .mod_offs = DSP_CONFIG_OFFS,
+ .enable_reg = DSP_IDLECT2_OFFSET,
.enable_bit = EN_DSPTIMCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_dsp_domain,
@@ -371,7 +392,7 @@ static struct arm_idlect1_clk tc_ck = {
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 6,
+ .idlect_shift = IDLIF_ARM_SHIFT,
};
static struct clk arminth_ck1510 = {
@@ -404,7 +425,8 @@ static struct clk l3_ocpi_ck = {
.name = "l3_ocpi_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT3_OFFSET,
.enable_bit = EN_OCPI_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -415,7 +437,8 @@ static struct clk tc1_ck = {
.name = "tc1_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT3_OFFSET,
.enable_bit = EN_TC1_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -426,7 +449,8 @@ static struct clk tc2_ck = {
.name = "tc2_ck",
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)ARM_IDLECT3,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT3_OFFSET,
.enable_bit = EN_TC2_CK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
@@ -459,13 +483,14 @@ static struct arm_idlect1_clk api_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_APICK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 8,
+ .idlect_shift = IDLAPI_ARM_SHIFT,
};
static struct arm_idlect1_clk lb_ck = {
@@ -474,13 +499,14 @@ static struct arm_idlect1_clk lb_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_LBCK,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 4,
+ .idlect_shift = IDLLB_ARM_SHIFT,
};
static struct clk rhea1_ck = {
@@ -505,7 +531,8 @@ static struct clk lcd_ck_16xx = {
.name = "lcd_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -519,14 +546,15 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
RATE_CKCTL | CLOCK_IDLE_CONTROL,
- .enable_reg = (void __iomem *)ARM_IDLECT2,
+ .mod_offs = MPU_CLKGEN_OFFS,
+ .enable_reg = ARM_IDLECT2_OFFSET,
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
},
- .idlect_shift = 3,
+ .idlect_shift = IDLLCD_ARM_SHIFT,
};
static struct clk uart1_1510 = {
@@ -537,8 +565,9 @@ static struct clk uart1_1510 = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_UART1_CLK_MODE_R_SHIFT, /* 12MHz or 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
.enable = &omap1_clk_enable_generic,
@@ -553,8 +582,9 @@ static struct uart_clk uart1_16xx = {
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 29,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_UART1_CLK_MODE_R_SHIFT, /* 12MHz or 48MHz */
.enable = &omap1_clk_enable_uart_functional,
.disable = &omap1_clk_disable_uart_functional,
},
@@ -569,8 +599,9 @@ static struct clk uart2_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_UART2_CLK_MODE_R_SHIFT, /* 12MHz or 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
.enable = &omap1_clk_enable_generic,
@@ -585,8 +616,9 @@ static struct clk uart3_1510 = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_UART3_CLK_MODE_R_SHIFT, /* 12MHz or 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
.enable = &omap1_clk_enable_generic,
@@ -601,8 +633,9 @@ static struct uart_clk uart3_16xx = {
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 31,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_UART3_CLK_MODE_R_SHIFT, /* 12MHz or 48MHz */
.enable = &omap1_clk_enable_uart_functional,
.disable = &omap1_clk_disable_uart_functional,
},
@@ -615,7 +648,8 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
.rate = 6000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
+ .mod_offs = MPU_ULPD_OFFS,
+ .enable_reg = ULPD_CLOCK_CTRL_OFFSET,
.enable_bit = USB_MCLK_EN_BIT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -627,7 +661,8 @@ static struct clk usb_hhc_ck1510 = {
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
.enable_bit = USB_HOST_HHC_UHOST_EN,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
@@ -638,10 +673,10 @@ static struct clk usb_hhc_ck16xx = {
/* Direct from ULPD, no parent */
.rate = 48000000,
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
- .flags = CLOCK_IN_OMAP16XX |
- RATE_FIXED | ENABLE_REG_32BIT,
- .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
- .enable_bit = 8 /* UHOST_EN */,
+ .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
+ .mod_offs = MPU_OTG_OFFS,
+ .enable_reg = OTG_SYSCON_2_OFFSET,
+ .enable_bit = UHOST_EN_SHIFT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
@@ -651,8 +686,9 @@ static struct clk usb_dc_ck = {
/* Direct from ULPD, no parent */
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
- .enable_reg = (void __iomem *)SOFT_REQ_REG,
- .enable_bit = 4,
+ .mod_offs = MPU_ULPD_OFFS,
+ .enable_reg = ULPD_SOFT_REQ_OFFSET,
+ .enable_bit = SOFT_UDC_REQ_SHIFT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
@@ -661,9 +697,10 @@ static struct clk mclk_1510 = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
- .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
- .enable_reg = (void __iomem *)SOFT_REQ_REG,
- .enable_bit = 6,
+ .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
+ .mod_offs = MPU_ULPD_OFFS,
+ .enable_reg = ULPD_SOFT_REQ_OFFSET,
+ .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
@@ -672,7 +709,8 @@ static struct clk mclk_16xx = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
+ .mod_offs = MPU_ULPD_OFFS,
+ .enable_reg = ULPD_COM_CLK_DIV_CTRL_SEL_OFFSET,
.enable_bit = COM_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
@@ -694,7 +732,8 @@ static struct clk bclk_16xx = {
.name = "bclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX,
- .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
+ .mod_offs = MPU_ULPD_OFFS,
+ .enable_reg = ULPD_SDW_CLK_DIV_CTRL_SEL_OFFSET,
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
@@ -711,8 +750,9 @@ static struct clk mmc1_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 23,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R_SHIFT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
@@ -723,10 +763,11 @@ static struct clk mmc2_ck = {
/* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck.clk,
.rate = 48000000,
- .flags = CLOCK_IN_OMAP16XX |
- RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
- .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
- .enable_bit = 20,
+ .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT |
+ CLOCK_NO_IDLE_PARENT,
+ .mod_offs = MPU_CONF_OFFS,
+ .enable_reg = MOD_CONF_CTRL_0_OFFSET,
+ .enable_bit = CONF_MOD_MMC_SD2_CLK_REQ_R_SHIFT,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index e58dac1..565fe84 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -90,6 +90,7 @@ struct clk {
} clkdm;
s16 prcm_mod;
#else
+ u16 mod_offs;
__u8 rate_offset;
__u8 src_offset;
#endif
@@ -130,6 +131,11 @@ extern void clk_enable_init_clocks(void);
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
+#ifdef CONFIG_ARCH_OMAP1
+extern __u32 arm_idlect1_mask;
+extern int omap1_clk_init(void);
+#endif
+
/* Clock flags */
#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
#define RATE_FIXED (1 << 1) /* Fixed clock rate */
@@ -137,7 +143,7 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
+#define OMAP1_DSP_CLOCK (1 << 6) /* Registers in DSP space */
#define CLOCK_IDLE_CONTROL (1 << 7)
#define CLOCK_NO_IDLE_PARENT (1 << 8)
#define DELAYED_APP (1 << 9) /* Delay application of clock */
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 6589ddb..ecb30b6 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -70,14 +70,30 @@
* ----------------------------------------------------------------------------
*/
#define CLKGEN_REG_BASE (0xfffece00)
-#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
+#define ARM_CKCTL_OFFSET 0x00
+#define ARM_CKCTL (CLKGEN_REG_BASE + ARM_CKCTL_OFFSET)
+#define ARM_IDLECT1_OFFSET 0x04
+#define ARM_IDLECT1 (CLKGEN_REG_BASE + ARM_IDLECT1_OFFSET)
+# define IDL_CLKOUT_ARM_SHIFT 12
+# define IDLTIM_ARM_SHIFT 9
+# define IDLAPI_ARM_SHIFT 8
+# define IDLIF_ARM_SHIFT 6
+# define IDLLB_ARM_SHIFT 4
+# define IDLLCD_ARM_SHIFT 3
+# define IDLXORP_ARM_SHIFT 1
+# define IDLWDT_ARM_SHIFT 0
+#define ARM_IDLECT2_OFFSET 0x08
+#define ARM_IDLECT2 (CLKGEN_REG_BASE + ARM_IDLECT2_OFFSET)
+#define ARM_EWUPCT_OFFSET 0x0c
+#define ARM_EWUPCT (CLKGEN_REG_BASE + ARM_EWUPCT_OFFSET)
+#define ARM_RSTCT1_OFFSET 0x10
+#define ARM_RSTCT1 (CLKGEN_REG_BASE + ARM_RSTCT1_OFFSET)
+#define ARM_RSTCT2_OFFSET 0x14
+#define ARM_RSTCT2 (CLKGEN_REG_BASE + ARM_RSTCT2_OFFSET)
+#define ARM_SYSST_OFFSET 0x18
+#define ARM_SYSST (CLKGEN_REG_BASE + ARM_SYSST_OFFSET)
+#define ARM_IDLECT3_OFFSET 0x24
+#define ARM_IDLECT3 (CLKGEN_REG_BASE + ARM_IDLECT3_OFFSET)
#define CK_RATEF 1
#define CK_IDLEF 2
@@ -89,11 +105,15 @@
#define DPLL_CTL (0xfffecf00)
/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
-#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
+#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
+#define DSP_CKCTL_OFFSET 0x0
+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + DSP_CKCTL_OFFSET)
+#define DSP_IDLECT1_OFFSET 0x4
+#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + DSP_IDLECT1_OFFSET)
+#define DSP_IDLECT2_OFFSET 0x8
+#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + DSP_IDLECT2_OFFSET)
+#define DSP_RSTCT2_OFFSET 0x14
+#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + DSP_RSTCT2_OFFSET)
/*
* ---------------------------------------------------------------------------
@@ -103,10 +123,14 @@
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL_OFFSET 0x30
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
+#define ULPD_SOFT_REQ_OFFSET 0x34
+#define ULPD_SOFT_REQ (ULPD_REG_BASE + ULPD_SOFT_REQ_OFFSET)
+# define SOFT_COM_MCKO_REQ_SHIFT 6
+# define SOFT_UDC_REQ_SHIFT 4
# define SOFT_UDC_REQ (1 << 4)
# define SOFT_USB_CLK_REQ (1 << 3)
# define SOFT_DPLL_REQ (1 << 0)
@@ -121,7 +145,9 @@
# define DIS_UART2_DPLL_REQ (1 << 8)
# define DIS_UART1_DPLL_REQ (1 << 7)
# define DIS_USB_HOST_DPLL_REQ (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL_OFFSET 0x74
#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
+#define ULPD_COM_CLK_DIV_CTRL_SEL_OFFSET 0x78
#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
/*
@@ -184,8 +210,17 @@
* System control registers
* ----------------------------------------------------------------------------
*/
-#define MOD_CONF_CTRL_0 0xfffe1080
-#define MOD_CONF_CTRL_1 0xfffe1110
+#define MOD_CONF_REG_BASE 0xfffe1000
+#define MOD_CONF_CTRL_0_OFFSET 0x080
+#define MOD_CONF_CTRL_0 (MOD_CONF_REG_BASE + MOD_CONF_CTRL_0_OFFSET)
+# define CONF_MOD_UART3_CLK_MODE_R_SHIFT 31
+# define CONF_MOD_UART2_CLK_MODE_R_SHIFT 30
+# define CONF_MOD_UART1_CLK_MODE_R_SHIFT 29
+# define CONF_MOD_MMC_SD_CLK_REQ_R_SHIFT 23
+# define CONF_MOD_MMC_SD2_CLK_REQ_R_SHIFT 20
+#define MOD_CONF_CTRL_1_OFFSET 0x110
+#define MOD_CONF_CTRL_1 (MOD_CONF_REG_BASE + MOD_CONF_CTRL_1_OFFSET)
+# define CONF_MOD_SOSSI_CLK_EN_R_SHIFT 16
/*
* ----------------------------------------------------------------------------
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index d92bf79..61d43f9 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -61,6 +61,9 @@
#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
#define io_v2p(va) ((va) + IO_OFFSET)
+#define OMAP1_DSP_IO_BASE 0xe1000000
+#define OMAP1_MPU_BASE 0xf0000000
+
#elif defined(CONFIG_ARCH_OMAP2)
/* We map both L3 and L4 on OMAP2 */
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
index a56a610..59dbbae 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -44,7 +44,8 @@
# define DEV_IDLE_EN (1 << 13)
# define OTG_RESET_DONE (1 << 2)
# define OTG_SOFT_RESET (1 << 1)
-#define OTG_SYSCON_2 (OTG_BASE + 0x08)
+#define OTG_SYSCON_2_OFFSET 0x08
+#define OTG_SYSCON_2 (OTG_BASE + OTG_SYSCON_2_OFFSET)
# define OTG_EN (1 << 31)
# define USBX_SYNCHRO (1 << 30)
# define OTG_MST16 (1 << 29)
@@ -58,6 +59,7 @@
# define SRP_VBUS (1 << 12)
# define OTG_PADEN (1 << 10)
# define HMC_PADEN (1 << 9)
+# define UHOST_EN_SHIFT 8
# define UHOST_EN (1 << 8)
# define HMC_TLLSPEED (1 << 7)
# define HMC_TLLATTACH (1 << 6)
--
1.6.0.2.GIT
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH D 11/11] Fix omap1 clock issues
2009-02-06 21:19 ` Paul Walmsley
@ 2009-02-06 21:44 ` Russell King - ARM Linux
2009-02-06 23:04 ` Paul Walmsley
0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2009-02-06 21:44 UTC (permalink / raw)
To: Paul Walmsley; +Cc: linux-arm-kernel, linux-kernel, linux-omap, Tony Lindgren
On Fri, Feb 06, 2009 at 02:19:34PM -0700, Paul Walmsley wrote:
> [paul@pwsan.com: This patch has been updated to use offsets for OMAP1
> clock enable registers, to resolve all current sparse warnings with the
> clock code, and to convert most magic constants into symbolic macros.
Wish you hadn't; I've been avoiding the patches changing the way registers
are accessed for the time being - until I have an opportunity to think
about them for a bit.
As can be seen in the OMAP2 updates, this approach causes additional
struct clk's to appear for mcbsp clocks because they have controlling
registers split across two subsystems. This is contary to one of your
other statements about wanting the struct clk's to reflect the real
clock structure without virtual clocks.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH D 11/11] Fix omap1 clock issues
2009-02-06 21:44 ` Russell King - ARM Linux
@ 2009-02-06 23:04 ` Paul Walmsley
0 siblings, 0 replies; 25+ messages in thread
From: Paul Walmsley @ 2009-02-06 23:04 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel, linux-kernel, linux-omap, Tony Lindgren
Hi Russell,
On Fri, 6 Feb 2009, Russell King - ARM Linux wrote:
> On Fri, Feb 06, 2009 at 02:19:34PM -0700, Paul Walmsley wrote:
> > [paul@pwsan.com: This patch has been updated to use offsets for OMAP1
> > clock enable registers, to resolve all current sparse warnings with the
> > clock code, and to convert most magic constants into symbolic macros.
>
> Wish you hadn't;
If it's the patch that is problematic, I'm certainly open to comments to
revise it.
As you've probably seen, the OMAP1 clock control registers and memory map
are structured quite differently than the OMAP2/3 PRCM and module layout.
> I've been avoiding the patches changing the way registers
> are accessed for the time being - until I have an opportunity to think
> about them for a bit.
>
> As can be seen in the OMAP2 updates, this approach causes additional
> struct clk's to appear for mcbsp clocks because they have controlling
> registers split across two subsystems. This is contary to one of your
> other statements about wanting the struct clk's to reflect the real
> clock structure without virtual clocks.
I think we're just using the term "virtual clock" differently.
"Virtual clocks" in my usage are clocks that have no direct connection to
a particular clock tree entity in the hardware, such as a gate, divider,
source multiplexer, or oscillator source. Examples of these virtual
clocks are those that were created simply for convenience to switch a
group of hardware clocks on and off (as the old McBSP clocks were).
In the medium-term, the plan here is to modify the OMAP clk_set_parent()
and clk_set_rate() functions to walk up the clock tree if the device
driver-supplied clock does not support parent/rate selection. This is a
relatively minor fix that should make parent and rate selection
transparent for device drivers (e.g., drivers shouldn't need
clk_get_parent() at that point).
- Paul
^ permalink raw reply [flat|nested] 25+ messages in thread