Disable L1/L2/L3 cache and MTRR

Disable L1/L2/L3 cache and MTRR

[Andev]

Hello,

You need to set the 30th bit of CR0 register to disable the cache.
I've tried disabling the L1/L2/L3 cache in an intel processor as follows.

#include <linux/init.h>
#include <linux/module.h>
MODULE_LICENSE("Dual BSD/GPL");
static int hello_init(void)
{
        printk(KERN_ALERT "Hello, world\n");
        __asm__("push   %rax\n\t"
                "mov    %cr0,%rax;\n\t"
                "or     $(1 << 30),%rax;\n\t"
                "mov    %rax,%cr0;\n\t"
                "wbinvd\n\t"
                "pop    %rax"
);
        return 0;
}
static void hello_exit(void)
{
        printk(KERN_ALERT "Goodbye, cruel world\n");
        __asm__("push   %rax\n\t"
                "mov    %cr0,%rax;\n\t"
                "and     $~(1 << 30),%rax;\n\t"
                "mov    %rax,%cr0;\n\t"
                "pop    %rax"
);
}
module_init(hello_init);
module_exit(hello_exit);

When I try to remove this module, the system hangs! Any help?

In Intel software developers manual, it is mentioned that apart from the
above you need to disable MTRR. I did that using the following command:

echo "disable=00" >| /proc/mtrr

Now when I run some sample benchmarks they show a slowdown of almost 1000x!!

This is not reasonable since the max. The slowdown I was expecting is 200x
considering that it will take 200 cycles to read from DRAM.

Thanks,
Andev.

Re: Disable L1/L2/L3 cache and MTRR

[Sitsofe Wheeler]

Hi,

On Thu, Oct 21, 2010 at 12:21:15PM -0400, Andev wrote:
> 
> In Intel software developers manual, it is mentioned that apart from the
> above you need to disable MTRR. I did that using the following command:
> 
> echo "disable=00" >| /proc/mtrr
> 
> Now when I run some sample benchmarks they show a slowdown of almost 1000x!!
> 
> This is not reasonable since the max. The slowdown I was expecting is 200x
> considering that it will take 200 cycles to read from DRAM.

Assuming the cache was completely disabled, won't the impact be
cumulative? E.g. imagine a memory read takes one cycle from cache and
100 from main memory. If you read 5 instructions from cache that will
take 5 cycles. If you read 5 instructions from main memory that will be
5*100 so 500 cycles. If it is 10 instructions then it is 10 vs 1000 and
so on...

Are you searching for an improvement in determinism?

-- 
Sitsofe | http://sucs.org/~sits/

Re: Disable L1/L2/L3 cache and MTRR

[Andev]

On Thu, Oct 21, 2010 at 4:23 PM, Sitsofe Wheeler <sitsofe@yahoo.com> wrote:

>> Now when I run some sample benchmarks they show a slowdown of almost 1000x!!
>>
>> This is not reasonable since the max. The slowdown I was expecting is 200x
>> considering that it will take 200 cycles to read from DRAM.
>
> Assuming the cache was completely disabled, won't the impact be
> cumulative? E.g. imagine a memory read takes one cycle from cache and
> 100 from main memory. If you read 5 instructions from cache that will
> take 5 cycles. If you read 5 instructions from main memory that will be
> 5*100 so 500 cycles. If it is 10 instructions then it is 10 vs 1000 and
> so on...
>
> Are you searching for an improvement in determinism?

Yes, if that was so, the slowdown is still 100x.

In my test case, I removed all the entries from /proc/mtrr and also
disabled L1/L2/L3 caches.
When I run a benchmark which runs for 4 sec with cache, it takes
almost 3000 secs without cache.

I think I am messing up the /proc/mtrr file.

Regards,
Andev.