Re: [PATCH] Quirk to fix suspend/resume on Lenovo Edge 11,13,14,15

[Andreas Herrmann <andreas.herrmann3@amd.com>]

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On Fri, Jan 14, 2011 at 02:55:30PM -0500, Manoj Iyer wrote:
> Borislav,
> 
> Any more thoughts on this one ?

Seems that we've identified the root cause.

I wondered why systems with the problem have configured IOAPIC pin
with polarity=1 (low active).  That was different to what the working
systems used.

Switching the configuration to the usual polarity=0 (high active)
fixed the issue.

The explanation is that when hpet interrupt is triggerd, signal goes
from low to high. (AFAIK HPET spec even mentions that HPET interrupts
are all active high.)

Now if IO-APIC pin is configured as low active it just ignores this
signal change. It just triggers later when for next interrupt signal
will go from high to low and high again. (That happens the first time
after resume when the HPET counter wrapped around.) 

Setting the correct polarity fixes the detection of the first hpet
interrupt after resume.

To confirm that your systems behave similar you should boot with
"apic=debug" kernel parameter. The output for IO APIC should show
polarity=1 for IO APIC pin 2, e.g.

  [    0.158179] IO APIC #2......
   ...
  [    0.158205]  NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
  [    0.158210]  00 000 1    0    0   0   0    0    0    00
  [    0.158217]  01 003 0    0    0   0   0    1    1    31
  [    0.158224]  02 003 0    0    0   1   0    1    1    30

Furthermore you can check with attached test patch whether changing
the polarity fixes the problem on your system. IO APIC debug output
with this patch should change to

  [    0.156170] IO APIC #2......
   ...
  [    0.156197]  NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
  [    0.156202]  00 000 1    0    0   0   0    0    0    00
  [    0.156209]  01 003 0    0    0   0   0    1    1    31
  [    0.156216]  02 003 0    0    0   0   0    1    1    30


I'll come up with an SB800 quirk asap. (Of course we'll also try to
fix the respective BIOSes but too often BIOS updates are only
available for a limited time period.)


Regards,

Andreas

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diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 697dc34..9bf2b87 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1365,6 +1365,10 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
 		    apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
 		    irq, trigger, polarity);
 
+	if (pin == 2) {
+		polarity = 0;
+		trigger = 0;
+	}
 
 	if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
 			       dest, trigger, polarity, cfg->vector, pin)) {