From: Cyrill Gorcunov <gorcunov@openvz.org>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Vince Weaver <vincent.weaver@maine.edu>,
linux-kernel@vger.kernel.org, Paul Mackerras <paulus@samba.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
eranian@gmail.com, "Meadows,
Lawrence F" <lawrence.f.meadows@intel.com>
Subject: Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU
Date: Tue, 25 Sep 2012 15:42:25 +0400 [thread overview]
Message-ID: <20120925114225.GF14490@moon> (raw)
In-Reply-To: <1348572758.3881.24.camel@twins>
On Tue, Sep 25, 2012 at 01:32:38PM +0200, Peter Zijlstra wrote:
> On Thu, 2012-09-20 at 13:03 -0400, Vince Weaver wrote:
> > One additional complication: some of the cache events map to
> > event "0". This causes problems because the generic events code
> > assumes "0" means not-available. I'm not sure the best way to address
> > that problem.
>
> For all except P4 we could remap the 0 value to -2, that has all high
> bits set (like the -1) which aren't used by hardware.
>
> P4 is stuffing two registers in the 64bit config space and actually has
> them all in use I think.. Cyrill?
Yeah, we use almost all 64 bits in config. I tried to describe the bitmaps
in perf_event_p4.h (see Notes on internal configuration of ESCR+CCCR tuples).
Guys, letme re-read this whole mail thread first since I have no clue
what this remapping about ;)
next prev parent reply other threads:[~2012-09-25 11:42 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-20 17:03 [PATCH 1/1] perf, Add support for Xeon-Phi PMU Vince Weaver
2012-09-24 17:48 ` Meadows, Lawrence F
2012-09-25 11:32 ` Peter Zijlstra
2012-09-25 11:42 ` Cyrill Gorcunov [this message]
2012-09-25 11:51 ` Cyrill Gorcunov
2012-09-25 12:01 ` Peter Zijlstra
2012-09-25 12:05 ` stephane eranian
2012-09-25 12:22 ` Cyrill Gorcunov
2012-09-25 12:23 ` Cyrill Gorcunov
2012-09-25 13:27 ` Cyrill Gorcunov
2012-09-25 14:45 ` Vince Weaver
2012-09-25 14:53 ` Cyrill Gorcunov
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