* [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues
@ 2012-11-20 17:28 Johan Meiring
2012-11-20 17:28 ` [PATCH 02/10] staging: cxt1e1: musycc.h: fixes coding style issues Johan Meiring
` (8 more replies)
0 siblings, 9 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit fixes indentation issues that were reported by the
checkpatch.pl tool.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.h | 226 +++++++++++++++++++--------------------
1 file changed, 113 insertions(+), 113 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.h b/drivers/staging/cxt1e1/musycc.h
index cf6b54e..b6a282b 100644
--- a/drivers/staging/cxt1e1/musycc.h
+++ b/drivers/staging/cxt1e1/musycc.h
@@ -50,56 +50,56 @@
/* RAM image of MUSYCC registers laid out as a C structure */
struct musycc_groupr
{
- VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
- VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
- VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
- VINT32 rmp[32]; /* Receive Message Pointer [5-30] */
- VINT8 ttsm[128]; /* Time Slot Map [5-22] */
- VINT8 tscm[256]; /* Subchannel Map [5-24] */
- VINT32 tcct[32]; /* Channel Configuration [5-26] */
- VINT8 rtsm[128]; /* Time Slot Map [5-22] */
- VINT8 rscm[256]; /* Subchannel Map [5-24] */
- VINT32 rcct[32]; /* Channel Configuration [5-26] */
- VINT32 __glcd; /* Global Configuration Descriptor [5-10] */
- VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */
- VINT32 __iql; /* Interrupt Queue Length [5-36] */
- VINT32 grcd; /* Group Configuration Descriptor [5-16] */
- VINT32 mpd; /* Memory Protection Descriptor [5-18] */
- VINT32 mld; /* Message Length Descriptor [5-20] */
- VINT32 pcd; /* Port Configuration Descriptor [5-19] */
+ VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
+ VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
+ VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
+ VINT32 rmp[32]; /* Receive Message Pointer [5-30] */
+ VINT8 ttsm[128]; /* Time Slot Map [5-22] */
+ VINT8 tscm[256]; /* Subchannel Map [5-24] */
+ VINT32 tcct[32]; /* Channel Configuration [5-26] */
+ VINT8 rtsm[128]; /* Time Slot Map [5-22] */
+ VINT8 rscm[256]; /* Subchannel Map [5-24] */
+ VINT32 rcct[32]; /* Channel Configuration [5-26] */
+ VINT32 __glcd; /* Global Configuration Descriptor [5-10] */
+ VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */
+ VINT32 __iql; /* Interrupt Queue Length [5-36] */
+ VINT32 grcd; /* Group Configuration Descriptor [5-16] */
+ VINT32 mpd; /* Memory Protection Descriptor [5-18] */
+ VINT32 mld; /* Message Length Descriptor [5-20] */
+ VINT32 pcd; /* Port Configuration Descriptor [5-19] */
};
/* hardware MUSYCC registers laid out as a C structure */
struct musycc_globalr
{
- VINT32 gbp; /* Group Base Pointer */
- VINT32 dacbp; /* Dual Address Cycle Base Pointer */
- VINT32 srd; /* Service Request Descriptor */
- VINT32 isd; /* Interrupt Service Descriptor */
- /*
- * adjust __thp due to above 4 registers, which are not contained
- * within musycc_groupr[]. All __XXX[] are just place holders,
- * anyhow.
- */
- VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */
- VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */
- VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */
- VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */
- VINT8 ttsm[128]; /* Time Slot Map [5-22] */
- VINT8 tscm[256]; /* Subchannel Map [5-24] */
- VINT32 tcct[32]; /* Channel Configuration [5-26] */
- VINT8 rtsm[128]; /* Time Slot Map [5-22] */
- VINT8 rscm[256]; /* Subchannel Map [5-24] */
- VINT32 rcct[32]; /* Channel Configuration [5-26] */
- VINT32 glcd; /* Global Configuration Descriptor [5-10] */
- VINT32 iqp; /* Interrupt Queue Pointer [5-36] */
- VINT32 iql; /* Interrupt Queue Length [5-36] */
- VINT32 grcd; /* Group Configuration Descriptor [5-16] */
- VINT32 mpd; /* Memory Protection Descriptor [5-18] */
- VINT32 mld; /* Message Length Descriptor [5-20] */
- VINT32 pcd; /* Port Configuration Descriptor [5-19] */
- VINT32 rbist; /* Receive BIST status [5-4] */
- VINT32 tbist; /* Receive BIST status [5-4] */
+ VINT32 gbp; /* Group Base Pointer */
+ VINT32 dacbp; /* Dual Address Cycle Base Pointer */
+ VINT32 srd; /* Service Request Descriptor */
+ VINT32 isd; /* Interrupt Service Descriptor */
+ /*
+ * adjust __thp due to above 4 registers, which are not contained
+ * within musycc_groupr[]. All __XXX[] are just place holders,
+ * anyhow.
+ */
+ VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */
+ VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */
+ VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */
+ VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */
+ VINT8 ttsm[128]; /* Time Slot Map [5-22] */
+ VINT8 tscm[256]; /* Subchannel Map [5-24] */
+ VINT32 tcct[32]; /* Channel Configuration [5-26] */
+ VINT8 rtsm[128]; /* Time Slot Map [5-22] */
+ VINT8 rscm[256]; /* Subchannel Map [5-24] */
+ VINT32 rcct[32]; /* Channel Configuration [5-26] */
+ VINT32 glcd; /* Global Configuration Descriptor [5-10] */
+ VINT32 iqp; /* Interrupt Queue Pointer [5-36] */
+ VINT32 iql; /* Interrupt Queue Length [5-36] */
+ VINT32 grcd; /* Group Configuration Descriptor [5-16] */
+ VINT32 mpd; /* Memory Protection Descriptor [5-18] */
+ VINT32 mld; /* Message Length Descriptor [5-20] */
+ VINT32 pcd; /* Port Configuration Descriptor [5-19] */
+ VINT32 rbist; /* Receive BIST status [5-4] */
+ VINT32 tbist; /* Receive BIST status [5-4] */
};
/* Global Config Descriptor bit macros */
@@ -108,18 +108,18 @@
#define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */
#define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */
#define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit
- * field */
+ * field */
#define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit
- * field */
+ * field */
#define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit
- * field */
+ * field */
#define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */
#define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp
- * 4,5,6,7 */
+ * 4,5,6,7 */
#define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3,
- * etc... */
+ * etc... */
#define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2,
- * etc... */
+ * etc... */
/* and board specific assignments... */
#ifdef SBE_WAN256T3_ENABLE
@@ -137,57 +137,57 @@
#endif
#define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \
- ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \
- ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \
- (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL)
+ ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \
+ ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \
+ (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL)
/* Group Config Descriptor bit macros */
#define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */
#define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */
#define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for
- * subchanneling */
+ * subchanneling */
#define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message
- * processing disabled all
- * channels */
+ * processing disabled all
+ * channels */
#define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs
- * disabled */
+ * disabled */
#define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment
- * irq disabled */
+ * irq disabled */
#define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status
- * overwrite disabled */
+ * overwrite disabled */
#define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status
- * overwrite disabled */
+ * overwrite disabled */
#define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */
#define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits
- * copy enable. Conexant sez
- * turn this on */
+ * copy enable. Conexant sez
+ * turn this on */
#define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */
#define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */
#define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */
#define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle
- * bit field */
+ * bit field */
#define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM
- * count threshold */
+ * count threshold */
/* Port Config Descriptor bit macros */
#define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */
#define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */
#define MUSYCC_PCD_NX64_MODE 4
#define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK
- * rising edge */
+ * rising edge */
#define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on
- * TCLK rising edge */
+ * TCLK rising edge */
#define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK
- * rising edge */
+ * rising edge */
#define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on
- * RCLK rising edge */
+ * RCLK rising edge */
#define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame
- * signal on RCLK rising edge */
+ * signal on RCLK rising edge */
#define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes
- * logic 1 on output, else
- * tristate */
+ * logic 1 on output, else
+ * tristate */
#define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode
- * between E1 and T1 */
+ * between E1 and T1 */
/* Time Slot Descriptor bit macros */
#define MUSYCC_TSD_MODE_64KBPS 4
@@ -202,17 +202,17 @@
#define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */
#define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */
#define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT
- * irqs disabled */
+ * irqs disabled */
#define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs
- * disabled */
+ * disabled */
#define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */
#define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */
#define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */
#define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */
#define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with
- * received data */
+ * received data */
#define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit
- * field */
+ * field */
#define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */
#define MUSYCC_CCD_SS7 1
#define MUSYCC_CCD_HDLC_FCS16 2
@@ -220,11 +220,11 @@
#define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */
#define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */
#define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit
- * field */
+ * field */
#define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data
- * buffer length */
+ * buffer length */
#define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data
- * buffer starting location */
+ * buffer starting location */
/****************************************************************************
* Interrupt Descriptor Information */
@@ -266,7 +266,7 @@
#define INTRPT_GRP_S 29
#define INTRPT_GRP_MSB_S 12
#define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \
- ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S))
+ ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S))
#define INTRPT_CH_M 0x1F000000
#define INTRPT_CH_S 24
@@ -295,82 +295,82 @@
/* Buffer Descriptor bit macros */
#define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host
- * owner on receive */
+ * owner on receive */
#define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */
#define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */
#define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */
#define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */
#define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer
- * for ownership */
+ * for ownership */
#define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of
- * the message */
+ * the message */
#define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */
#define PADFILL_ENABLE 0x01000000 /* Enable padfill */
#define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */
#define LENGTH_MASK 0X3fff /* This part of status descriptor is
- * length */
+ * length */
#define IDLE_CODE 25 /* Position index for idle code (2
- * bits) */
+ * bits) */
#define EXTRA_FLAGS 16 /* Position index for minimum flags
- * between messages (8 bits) */
+ * between messages (8 bits) */
#define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the
- * pattern is OR'd in */
+ * pattern is OR'd in */
#define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the
- * pattern is OR'd in */
+ * pattern is OR'd in */
#define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on
- * the polled mode descriptor */
+ * the polled mode descriptor */
/* Service Request Descriptor bit macros */
#define SREQ 8 /* Position index for service request bit
- * field */
+ * field */
#define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */
#define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */
#define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */
#define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global
- * config deswc and interrupt
- * queue desc */
+ * config deswc and interrupt
+ * queue desc */
#define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot
- * and Subchannel maps,
- * Channel Config, */
+ * and Subchannel maps,
+ * Channel Config, */
/*
* Group Config, Memory Protect, Message Length, and Port Config
* Descriptors
*/
#define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head
- * Pointer, process first
- * Message Descriptor */
+ * Pointer, process first
+ * Message Descriptor */
#define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */
#define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */
#define SR_JUMP (10<<(SREQ)) /* a: Process new Message
- * List */
+ * List */
#define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel
- * Configuration Descriptor */
+ * Configuration Descriptor */
#define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global
- * Configuration Descriptor */
+ * Configuration Descriptor */
#define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue
- * Descriptor */
+ * Descriptor */
#define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group
- * Configuration Descriptor */
+ * Configuration Descriptor */
#define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection
- * Descriptor */
+ * Descriptor */
#define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length
- * Descriptor */
+ * Descriptor */
#define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port
- * Configuration Descriptor */
+ * Configuration Descriptor */
#define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */
#define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */
#define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel
- * Configuration Table for
- * the group */
+ * Configuration Table for
+ * the group */
#define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit.
- * Bit off indicates receive
- * direction */
+ * Bit off indicates receive
+ * direction */
#define SR_RX_DIRECTION 0x00000000
/* Interrupt Descriptor bit macros */
#define GROUP10 29 /* Position index for the 2 LS group
- * bits */
+ * bits */
#define CHANNEL 24 /* Position index for channel bits */
#define INT_IQD_TX 0x80000000
#define INT_IQD_GRP 0x60000000
@@ -384,7 +384,7 @@
/* Interrupt Descriptor Events */
#define EVE_EVENT 20 /* Position index for event bits */
#define EVE_NONE 0 /* No event to report in this
- * interrupt */
+ * interrupt */
#define EVE_SACK 1 /* Service Request acknowledge */
#define EVE_EOB 2 /* End of Buffer */
#define EVE_EOM 3 /* End of Message */
@@ -411,12 +411,12 @@
#define ERR_PERR 15 /* PCI Parity Error */
/* Other Stuff */
#define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off
- * indicates receive direction */
+ * indicates receive direction */
#define ILOST 0x00008000 /* Interrupt Lost */
#define GROUPMSB 0x00004000 /* Group number MSB */
#define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */
#define INITIAL_STATUS 0x10000 /* IRQ status should be this after
- * reset */
+ * reset */
/* This must be defined on an entire channel group (Port) basis */
#define SUERM_THRESHOLD 0x1f
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 02/10] staging: cxt1e1: musycc.h: fixes coding style issues
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 03/10] staging: cxt1e1: musycc.h: fixes brace placement Johan Meiring
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit fixes instances of spaces being used for indentation
instead of tabs.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.h b/drivers/staging/cxt1e1/musycc.h
index b6a282b..7deb607 100644
--- a/drivers/staging/cxt1e1/musycc.h
+++ b/drivers/staging/cxt1e1/musycc.h
@@ -48,8 +48,8 @@
#define INT_QUEUE_SIZE MUSYCC_NIQD
/* RAM image of MUSYCC registers laid out as a C structure */
- struct musycc_groupr
- {
+struct musycc_groupr
+{
VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
@@ -67,11 +67,11 @@
VINT32 mpd; /* Memory Protection Descriptor [5-18] */
VINT32 mld; /* Message Length Descriptor [5-20] */
VINT32 pcd; /* Port Configuration Descriptor [5-19] */
- };
+};
/* hardware MUSYCC registers laid out as a C structure */
- struct musycc_globalr
- {
+struct musycc_globalr
+{
VINT32 gbp; /* Group Base Pointer */
VINT32 dacbp; /* Dual Address Cycle Base Pointer */
VINT32 srd; /* Service Request Descriptor */
@@ -100,7 +100,7 @@
VINT32 pcd; /* Port Configuration Descriptor [5-19] */
VINT32 rbist; /* Receive BIST status [5-4] */
VINT32 tbist; /* Receive BIST status [5-4] */
- };
+};
/* Global Config Descriptor bit macros */
#define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 03/10] staging: cxt1e1: musycc.h: fixes brace placement
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
2012-11-20 17:28 ` [PATCH 02/10] staging: cxt1e1: musycc.h: fixes coding style issues Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 04/10] staging: cxt1e1: musycc.c: uses tabs for indentation Johan Meiring
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit fixes incorrect brace placement.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.h | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.h b/drivers/staging/cxt1e1/musycc.h
index 7deb607..56fb42f 100644
--- a/drivers/staging/cxt1e1/musycc.h
+++ b/drivers/staging/cxt1e1/musycc.h
@@ -48,8 +48,7 @@
#define INT_QUEUE_SIZE MUSYCC_NIQD
/* RAM image of MUSYCC registers laid out as a C structure */
-struct musycc_groupr
-{
+struct musycc_groupr {
VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
@@ -70,8 +69,7 @@ struct musycc_groupr
};
/* hardware MUSYCC registers laid out as a C structure */
-struct musycc_globalr
-{
+struct musycc_globalr {
VINT32 gbp; /* Group Base Pointer */
VINT32 dacbp; /* Dual Address Cycle Base Pointer */
VINT32 srd; /* Service Request Descriptor */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 04/10] staging: cxt1e1: musycc.c: uses tabs for indentation
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
2012-11-20 17:28 ` [PATCH 02/10] staging: cxt1e1: musycc.h: fixes coding style issues Johan Meiring
2012-11-20 17:28 ` [PATCH 03/10] staging: cxt1e1: musycc.h: fixes brace placement Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 05/10] staging: cxt1e1: musycc.c: fixes brace placement Johan Meiring
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit converts several instances of space usage for
indentation to tabs.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.c | 1842 +++++++++++++++++++--------------------
1 file changed, 921 insertions(+), 921 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
index ba721c6..5feac8a 100644
--- a/drivers/staging/cxt1e1/musycc.c
+++ b/drivers/staging/cxt1e1/musycc.c
@@ -55,7 +55,7 @@ extern int cxt1e1_max_mtu;
extern int max_rxdesc_used;
extern int max_txdesc_used;
extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
- * USAGE */
+ * USAGE */
/*******************************************************************/
@@ -84,62 +84,62 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
if (lockit)
{
- spin_lock_irqsave (&ch->ch_rxlock, flags);
+ spin_lock_irqsave (&ch->ch_rxlock, flags);
}
if (ch->rxd_num == 0)
{
- pr_info(" ZERO receive buffers allocated for this channel.");
+ pr_info(" ZERO receive buffers allocated for this channel.");
} else
{
- FLUSH_MEM_READ ();
- m = &ch->mdr[ch->rxix_irq_srv];
- for (n = ch->rxd_num; n; n--)
- {
- status = le32_to_cpu (m->status);
- {
- pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
- (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
- (unsigned long) m, n,
- status,
- m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
- status & POLL_DISABLED ? 'P' : '-',
- status & EOBIRQ_ENABLE ? 'b' : '-',
- status & EOMIRQ_ENABLE ? 'm' : '-',
- status & LENGTH_MASK,
- le32_to_cpu (m->data), le32_to_cpu (m->next));
+ FLUSH_MEM_READ ();
+ m = &ch->mdr[ch->rxix_irq_srv];
+ for (n = ch->rxd_num; n; n--)
+ {
+ status = le32_to_cpu (m->status);
+ {
+ pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
+ (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
+ (unsigned long) m, n,
+ status,
+ m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
+ status & POLL_DISABLED ? 'P' : '-',
+ status & EOBIRQ_ENABLE ? 'b' : '-',
+ status & EOMIRQ_ENABLE ? 'm' : '-',
+ status & LENGTH_MASK,
+ le32_to_cpu (m->data), le32_to_cpu (m->next));
#ifdef RLD_DUMP_BUFDATA
- {
- u_int32_t *dp;
- int len = status & LENGTH_MASK;
+ {
+ u_int32_t *dp;
+ int len = status & LENGTH_MASK;
#if 1
- if (m->data && (status & HOST_RX_OWNED))
+ if (m->data && (status & HOST_RX_OWNED))
#else
- if (m->data) /* always dump regardless of valid RX
- * data */
+ if (m->data) /* always dump regardless of valid RX
+ * data */
#endif
- {
- dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
- if (len >= 0x10)
- pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
- *dp, *(dp + 1), *(dp + 2), *(dp + 3));
- else if (len >= 0x08)
- pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
- *dp, *(dp + 1));
- else
- pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
- }
- }
+ {
+ dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
+ if (len >= 0x10)
+ pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
+ *dp, *(dp + 1), *(dp + 2), *(dp + 3));
+ else if (len >= 0x08)
+ pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
+ *dp, *(dp + 1));
+ else
+ pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
+ }
+ }
#endif
- }
- m = m->snext;
- }
+ }
+ m = m->snext;
+ }
} /* -for- */
pr_info("\n");
if (lockit)
{
- spin_unlock_irqrestore (&ch->ch_rxlock, flags);
+ spin_unlock_irqrestore (&ch->ch_rxlock, flags);
}
return 0;
}
@@ -156,58 +156,58 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
if (lockit)
{
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave (&ch->ch_txlock, flags);
}
if (ch->txd_num == 0)
{
- pr_info(" ZERO transmit buffers allocated for this channel.");
+ pr_info(" ZERO transmit buffers allocated for this channel.");
} else
{
- FLUSH_MEM_READ ();
- m = ch->txd_irq_srv;
- for (n = ch->txd_num; n; n--)
- {
- status = le32_to_cpu (m->status);
- {
- pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
- (m == ch->txd_usr_add) ? 'F' : ' ',
- (m == ch->txd_irq_srv) ? 'L' : ' ',
- (unsigned long) m, n,
- status,
- m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
- status & POLL_DISABLED ? 'P' : '-',
- status & EOBIRQ_ENABLE ? 'b' : '-',
- status & EOMIRQ_ENABLE ? 'm' : '-',
- status & LENGTH_MASK,
- le32_to_cpu (m->data), le32_to_cpu (m->next));
+ FLUSH_MEM_READ ();
+ m = ch->txd_irq_srv;
+ for (n = ch->txd_num; n; n--)
+ {
+ status = le32_to_cpu (m->status);
+ {
+ pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
+ (m == ch->txd_usr_add) ? 'F' : ' ',
+ (m == ch->txd_irq_srv) ? 'L' : ' ',
+ (unsigned long) m, n,
+ status,
+ m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
+ status & POLL_DISABLED ? 'P' : '-',
+ status & EOBIRQ_ENABLE ? 'b' : '-',
+ status & EOMIRQ_ENABLE ? 'm' : '-',
+ status & LENGTH_MASK,
+ le32_to_cpu (m->data), le32_to_cpu (m->next));
#ifdef RLD_DUMP_BUFDATA
- {
- u_int32_t *dp;
- int len = status & LENGTH_MASK;
-
- if (m->data)
- {
- dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
- if (len >= 0x10)
- pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
- *dp, *(dp + 1), *(dp + 2), *(dp + 3));
- else if (len >= 0x08)
- pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
- *dp, *(dp + 1));
- else
- pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
- }
- }
+ {
+ u_int32_t *dp;
+ int len = status & LENGTH_MASK;
+
+ if (m->data)
+ {
+ dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
+ if (len >= 0x10)
+ pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
+ *dp, *(dp + 1), *(dp + 2), *(dp + 3));
+ else if (len >= 0x08)
+ pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
+ *dp, *(dp + 1));
+ else
+ pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
+ }
+ }
#endif
- }
- m = m->snext;
- }
+ }
+ m = m->snext;
+ }
} /* -for- */
pr_info("\n");
if (lockit)
{
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore (&ch->ch_txlock, flags);
}
return 0;
}
@@ -226,39 +226,39 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
if (chan >= MAX_CHANS_USED)
{
- return SBE_DRVR_FAIL; /* E2BIG */
+ return SBE_DRVR_FAIL; /* E2BIG */
}
{
- int bh;
-
- bh = atomic_read (&ci->bh_pending);
- pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
- bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
- ci->intlog.drvr_intr_thcount,
- ci->intlog.drvr_intr_bhcount,
- ci->wdcount, ci->wd_notify);
- max_bh = 0; /* reset counter */
- max_intcnt = 0; /* reset counter */
+ int bh;
+
+ bh = atomic_read (&ci->bh_pending);
+ pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
+ bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
+ ci->intlog.drvr_intr_thcount,
+ ci->intlog.drvr_intr_bhcount,
+ ci->wdcount, ci->wd_notify);
+ max_bh = 0; /* reset counter */
+ max_intcnt = 0; /* reset counter */
}
if (!(ch = sd_find_chan (dummy, chan)))
{
- pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
- return ENOENT;
+ pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
+ return ENOENT;
}
pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n", ci, chan, ch, ch->state,
- ch->status, ch->p.status);
+ ch->status, ch->p.status);
pr_info("--------------------------------\nTX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
- chan, ch->txd_num,
- (u_int32_t) atomic_read (&ci->tx_pending), (u_int32_t) atomic_read (&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
+ chan, ch->txd_num,
+ (u_int32_t) atomic_read (&ci->tx_pending), (u_int32_t) atomic_read (&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
- ch->user, ch->txd_irq_srv, ch->txd_usr_add,
- sd_queue_stopped (ch->user),
- ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
+ ch->user, ch->txd_irq_srv, ch->txd_usr_add,
+ sd_queue_stopped (ch->user),
+ ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
musycc_dump_txbuffer_ring (ch, 1);
pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
- chan, ch->rxd_num, ch->rxix_irq_srv,
- &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
+ chan, ch->rxd_num, ch->rxix_irq_srv,
+ &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
musycc_dump_rxbuffer_ring (ch, 1);
return SBE_DRVR_SUCCESS;
@@ -271,7 +271,7 @@ musycc_dump_rings (ci_t * ci, unsigned int start_chan)
unsigned int chan;
for (chan = start_chan; chan < (start_chan + 5); chan++)
- musycc_dump_ring (ci, chan);
+ musycc_dump_ring (ci, chan);
return SBE_DRVR_SUCCESS;
}
@@ -300,7 +300,7 @@ musycc_init_mdt (mpi_t * pi)
for (i = 0; i < 32; addr++, i++)
{
- pci_write_32 (addr, cfg);
+ pci_write_32 (addr, cfg);
}
}
@@ -316,26 +316,26 @@ musycc_update_tx_thp (mch_t * ch)
spin_lock_irqsave (&ch->ch_txlock, flags);
while (1)
{
- md = ch->txd_irq_srv;
- FLUSH_MEM_READ ();
- if (!md->data)
- {
- /* No MDs with buffers to process */
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
- return;
- }
- if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)
- {
- /* this is the MD to restart TX with */
- break;
- }
- /*
- * Otherwise, we have a valid, host-owned message descriptor which
- * has been successfully transmitted and whose buffer can be freed,
- * so... process this MD, it's owned by the host. (This might give
- * as a new, updated txd_irq_srv.)
- */
- musycc_bh_tx_eom (ch->up, ch->gchan);
+ md = ch->txd_irq_srv;
+ FLUSH_MEM_READ ();
+ if (!md->data)
+ {
+ /* No MDs with buffers to process */
+ spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ return;
+ }
+ if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)
+ {
+ /* this is the MD to restart TX with */
+ break;
+ }
+ /*
+ * Otherwise, we have a valid, host-owned message descriptor which
+ * has been successfully transmitted and whose buffer can be freed,
+ * so... process this MD, it's owned by the host. (This might give
+ * as a new, updated txd_irq_srv.)
+ */
+ musycc_bh_tx_eom (ch->up, ch->gchan);
}
md = ch->txd_irq_srv;
ch->up->regram->thp[ch->gchan] = cpu_to_le32 (OS_vtophys (md));
@@ -343,10 +343,10 @@ musycc_update_tx_thp (mch_t * ch)
if (ch->tx_full)
{
- ch->tx_full = 0;
- ch->txd_required = 0;
- sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
- * channel */
+ ch->tx_full = 0;
+ ch->txd_required = 0;
+ sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
+ * channel */
}
spin_unlock_irqrestore (&ch->ch_txlock, flags);
@@ -380,7 +380,7 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
#ifdef RLD_TRANS_DEBUG
pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
- ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
+ ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
#endif
@@ -391,30 +391,30 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
if ((ch->ch_start_rx) && (ch->status & RX_ENABLED))
{
- ch->ch_start_rx = 0;
+ ch->ch_start_rx = 0;
#if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
- {
- static int hereb4 = 7;
+ {
+ static int hereb4 = 7;
- if (hereb4) /* RLD DEBUG */
- {
- hereb4--;
+ if (hereb4) /* RLD DEBUG */
+ {
+ hereb4--;
#ifdef RLD_TRANS_DEBUG
- md = &ch->mdr[ch->rxix_irq_srv];
- pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
- ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
- ch->s.rx_packets);
+ md = &ch->mdr[ch->rxix_irq_srv];
+ pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
+ ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
+ ch->s.rx_packets);
#elif defined(RLD_RXACT_DEBUG)
- md = &ch->mdr[ch->rxix_irq_srv];
- pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
- ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
- ch->s.rx_packets);
- musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
+ md = &ch->mdr[ch->rxix_irq_srv];
+ pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
+ ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
+ ch->s.rx_packets);
+ musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
#endif
- }
- }
+ }
+ }
#endif
- musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
+ musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
}
/**********************************/
/** check for TX restart request **/
@@ -422,46 +422,46 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
if ((ch->ch_start_tx) && (ch->status & TX_ENABLED))
{
- /* find next unprocessed message, then set TX thp to it */
- musycc_update_tx_thp (ch);
+ /* find next unprocessed message, then set TX thp to it */
+ musycc_update_tx_thp (ch);
#if 0
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave (&ch->ch_txlock, flags);
#endif
- md = ch->txd_irq_srv;
- if (!md)
- {
+ md = ch->txd_irq_srv;
+ if (!md)
+ {
#ifdef RLD_TRANS_DEBUG
- pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
+ pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
#endif
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore (&ch->ch_txlock, flags);
#endif
- } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
- {
- ch->ch_start_tx = 0;
+ } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
+ {
+ ch->ch_start_tx = 0;
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
+ spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
#endif
#ifdef RLD_TRANS_DEBUG
- pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
- ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
+ pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
+ ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
#endif
- musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
- }
+ musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
+ }
#ifdef RLD_RESTART_DEBUG
- else
- {
- /* retain request to start until retried and we have data to xmit */
- pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
- ch->channum, md,
- le32_to_cpu (md->status),
- le32_to_cpu (md->data), ch->ch_start_tx);
- musycc_dump_txbuffer_ring (ch, 0);
+ else
+ {
+ /* retain request to start until retried and we have data to xmit */
+ pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
+ ch->channum, md,
+ le32_to_cpu (md->status),
+ le32_to_cpu (md->data), ch->ch_start_tx);
+ musycc_dump_txbuffer_ring (ch, 0);
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
+ spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
#endif
- }
+ }
#endif
}
}
@@ -477,7 +477,7 @@ musycc_chan_restart (mch_t * ch)
{
#ifdef RLD_RESTART_DEBUG
pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
- ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
+ ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
#endif
/* 2.6 - find next unprocessed message, then set TX thp to it */
@@ -485,7 +485,7 @@ musycc_chan_restart (mch_t * ch)
pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n", ch->channum, &ch->ch_work);
#endif
c4_wk_chan_restart (ch); /* work queue mechanism fires off: Ref:
- * musycc_wq_chan_restart () */
+ * musycc_wq_chan_restart () */
}
@@ -496,9 +496,9 @@ rld_put_led (mpi_t * pi, u_int32_t ledval)
static u_int32_t led = 0;
if (ledval == 0)
- led = 0;
+ led = 0;
else
- led |= ledval;
+ led |= ledval;
pci_write_32 ((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
}
@@ -521,42 +521,42 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
*/
SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
- * group */
+ * group */
if (pi->sr_last == req)
{
#ifdef RLD_TRANS_DEBUG
- pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
+ pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
#endif
- /*
- * The most likely repeated request is the channel activation command
- * which follows the occurrence of a Transparent mode TX ONR or a
- * BUFF error. If the previous command was a CHANNEL ACTIVATE,
- * precede it with a NOOP command in order maintain coherent control
- * of this current (re)ACTIVATE.
- */
-
- r = (pi->sr_last & ~SR_GCHANNEL_MASK);
- if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
- (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION)))
- {
+ /*
+ * The most likely repeated request is the channel activation command
+ * which follows the occurrence of a Transparent mode TX ONR or a
+ * BUFF error. If the previous command was a CHANNEL ACTIVATE,
+ * precede it with a NOOP command in order maintain coherent control
+ * of this current (re)ACTIVATE.
+ */
+
+ r = (pi->sr_last & ~SR_GCHANNEL_MASK);
+ if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
+ (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION)))
+ {
#ifdef RLD_TRANS_DEBUG
- pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
+ pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
#endif
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
- musycc_serv_req (pi, SR_NOOP);
- SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
- * original req */
- } else if (req == SR_NOOP)
- {
- /* no need to issue back-to-back SR_NOOP commands at this time */
+ SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
+ musycc_serv_req (pi, SR_NOOP);
+ SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
+ * original req */
+ } else if (req == SR_NOOP)
+ {
+ /* no need to issue back-to-back SR_NOOP commands at this time */
#ifdef RLD_TRANS_DEBUG
- pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
+ pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
#endif
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
- return;
- }
+ SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
+ return;
+ }
}
rcnt = 0;
pi->sr_last = req;
@@ -573,41 +573,41 @@ rewrite:
* the same address."
*/
r = pci_read_32 ((u_int32_t *) &pi->reg->srd); /* adhere to write
- * timing imposition */
+ * timing imposition */
if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT))
{
- if (cxt1e1_log_level >= LOG_MONITOR)
- pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
- pi->up->devname, rcnt, req, pi->sr_last, r,
- (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
- OS_uwait_dummy (); /* this delay helps reduce reissue counts
- * (reason not yet researched) */
- goto rewrite;
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
+ pi->up->devname, rcnt, req, pi->sr_last, r,
+ (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
+ OS_uwait_dummy (); /* this delay helps reduce reissue counts
+ * (reason not yet researched) */
+ goto rewrite;
}
if (rcnt > MUSYCC_SR_RETRY_CNT)
{
- pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
- pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
- return;
+ pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
+ pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
+ SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
+ return;
}
if (req == SR_CHIP_RESET)
{
- /*
- * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
- * the upcoming delay is used. Though the MUSYCC documentation
- * suggests a read-after-write would supply the required delay, it's
- * unclear what CPU/BUS clock speeds might have been assumed when
- * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
- */
- OS_uwait (100000, "icard"); /* 100ms */
+ /*
+ * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
+ * the upcoming delay is used. Though the MUSYCC documentation
+ * suggests a read-after-write would supply the required delay, it's
+ * unclear what CPU/BUS clock speeds might have been assumed when
+ * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
+ */
+ OS_uwait (100000, "icard"); /* 100ms */
} else
{
- FLUSH_MEM_READ ();
- SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
- * interrupt occurs */
+ FLUSH_MEM_READ ();
+ SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
+ * interrupt occurs */
}
SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
}
@@ -622,56 +622,56 @@ musycc_update_timeslots (mpi_t * pi)
for (i = 0; i < 32; i++)
{
- int usedby = 0, last = 0, ts, j, bits[8];
-
- u_int8_t lastval = 0;
-
- if (((i == 0) && e1mode) || /* disable if E1 mode */
- ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
- || ((i > 23) && (!e1mode))) /* disable if T1 mode */
- {
- pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
- } else
- {
- pi->tsm[i] = 0x00; /* make tslot available for assignment */
- }
- for (j = 0; j < 8; j++)
- bits[j] = -1;
- for (ch = 0; ch < MUSYCC_NCHANS; ch++)
- {
- if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i]))
- {
- usedby++;
- last = ch;
- lastval = pi->chan[ch]->p.bitmask[i];
- for (j = 0; j < 8; j++)
- if (lastval & (1 << j))
- bits[j] = ch;
- pi->tsm[i] |= lastval;
- }
- }
- if (!usedby)
- ts = 0;
- else if ((usedby == 1) && (lastval == 0xff))
- ts = (4 << 5) | last;
- else if ((usedby == 1) && (lastval == 0x7f))
- ts = (5 << 5) | last;
- else
- {
- int idx;
-
- if (bits[0] < 0)
- ts = (6 << 5) | (idx = last);
- else
- ts = (7 << 5) | (idx = bits[0]);
- for (j = 1; j < 8; j++)
- {
- pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
- pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
- }
- }
- pi->regram->rtsm[i] = ts;
- pi->regram->ttsm[i] = ts;
+ int usedby = 0, last = 0, ts, j, bits[8];
+
+ u_int8_t lastval = 0;
+
+ if (((i == 0) && e1mode) || /* disable if E1 mode */
+ ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
+ || ((i > 23) && (!e1mode))) /* disable if T1 mode */
+ {
+ pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
+ } else
+ {
+ pi->tsm[i] = 0x00; /* make tslot available for assignment */
+ }
+ for (j = 0; j < 8; j++)
+ bits[j] = -1;
+ for (ch = 0; ch < MUSYCC_NCHANS; ch++)
+ {
+ if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i]))
+ {
+ usedby++;
+ last = ch;
+ lastval = pi->chan[ch]->p.bitmask[i];
+ for (j = 0; j < 8; j++)
+ if (lastval & (1 << j))
+ bits[j] = ch;
+ pi->tsm[i] |= lastval;
+ }
+ }
+ if (!usedby)
+ ts = 0;
+ else if ((usedby == 1) && (lastval == 0xff))
+ ts = (4 << 5) | last;
+ else if ((usedby == 1) && (lastval == 0x7f))
+ ts = (5 << 5) | last;
+ else
+ {
+ int idx;
+
+ if (bits[0] < 0)
+ ts = (6 << 5) | (idx = last);
+ else
+ ts = (7 << 5) | (idx = bits[0]);
+ for (j = 1; j < 8; j++)
+ {
+ pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
+ pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
+ }
+ }
+ pi->regram->rtsm[i] = ts;
+ pi->regram->ttsm[i] = ts;
}
FLUSH_MEM_WRITE ();
@@ -701,15 +701,15 @@ musycc_update_timeslots (mpi_t * pi)
#endif
for (i = 0; i < 128; i++)
{
- gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
- ch = pi->chan[gchan];
- if (ch->p.mode_56k)
- tsen = MODE_56KBPS;
- else
- tsen = MODE_64KBPS; /* also the default */
- ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
- pi->regram->rtsm[i] = ts;
- pi->regram->ttsm[i] = ts;
+ gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
+ ch = pi->chan[gchan];
+ if (ch->p.mode_56k)
+ tsen = MODE_56KBPS;
+ else
+ tsen = MODE_64KBPS; /* also the default */
+ ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
+ pi->regram->rtsm[i] = ts;
+ pi->regram->ttsm[i] = ts;
}
FLUSH_MEM_WRITE ();
musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
@@ -730,19 +730,19 @@ musycc_chan_proto (int proto)
switch (proto)
{
case CFG_CH_PROTO_TRANS: /* 0 */
- reg = MUSYCC_CCD_TRANS;
- break;
+ reg = MUSYCC_CCD_TRANS;
+ break;
case CFG_CH_PROTO_SS7: /* 1 */
- reg = MUSYCC_CCD_SS7;
- break;
+ reg = MUSYCC_CCD_SS7;
+ break;
default:
case CFG_CH_PROTO_ISLP_MODE: /* 4 */
case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
- reg = MUSYCC_CCD_HDLC_FCS16;
- break;
+ reg = MUSYCC_CCD_HDLC_FCS16;
+ break;
case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
- reg = MUSYCC_CCD_HDLC_FCS32;
- break;
+ reg = MUSYCC_CCD_HDLC_FCS32;
+ break;
}
return reg;
@@ -755,19 +755,19 @@ musycc_init_port (mpi_t * pi)
pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
pi->regram->grcd =
- __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
- MUSYCC_GRCD_TX_ENABLE |
- MUSYCC_GRCD_SF_ALIGN |
- MUSYCC_GRCD_SUBCHAN_DISABLE |
- MUSYCC_GRCD_OOFMP_DISABLE |
- MUSYCC_GRCD_COFAIRQ_DISABLE |
- MUSYCC_GRCD_MC_ENABLE |
- (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
+ __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
+ MUSYCC_GRCD_TX_ENABLE |
+ MUSYCC_GRCD_SF_ALIGN |
+ MUSYCC_GRCD_SUBCHAN_DISABLE |
+ MUSYCC_GRCD_OOFMP_DISABLE |
+ MUSYCC_GRCD_COFAIRQ_DISABLE |
+ MUSYCC_GRCD_MC_ENABLE |
+ (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
pi->regram->pcd =
- __constant_cpu_to_le32 (MUSYCC_PCD_E1X4_MODE |
- MUSYCC_PCD_TXDATA_RISING |
- MUSYCC_PCD_TX_DRIVEN);
+ __constant_cpu_to_le32 (MUSYCC_PCD_E1X4_MODE |
+ MUSYCC_PCD_TXDATA_RISING |
+ MUSYCC_PCD_TX_DRIVEN);
/* Message length descriptor */
pi->regram->mld = __constant_cpu_to_le32 (cxt1e1_max_mru | (cxt1e1_max_mru << 16));
@@ -800,43 +800,43 @@ musycc_init (ci_t * ci)
regaddr = OS_kmalloc ((INT_QUEUE_SIZE + 1) * sizeof (u_int32_t));
if (regaddr == 0)
- return ENOMEM;
+ return ENOMEM;
ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
ci->iqd_p = (u_int32_t *) ((unsigned long) (regaddr + INT_QUEUE_BOUNDARY - 1) &
- (~(INT_QUEUE_BOUNDARY - 1))); /* this calculates
- * closest boundary */
+ (~(INT_QUEUE_BOUNDARY - 1))); /* this calculates
+ * closest boundary */
for (i = 0; i < INT_QUEUE_SIZE; i++)
{
- ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
+ ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
}
for (i = 0; i < ci->max_port; i++)
{
- mpi_t *pi = &ci->port[i];
+ mpi_t *pi = &ci->port[i];
- /*
- * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
- * bound memory segment for Channel Group 0."
- */
+ /*
+ * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
+ * bound memory segment for Channel Group 0."
+ */
#define GROUP_BOUNDARY 0x800
- regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
- if (regaddr == 0)
- {
- for (gchan = 0; gchan < i; gchan++)
- {
- pi = &ci->port[gchan];
- OS_kfree (pi->reg);
- pi->reg = 0;
- }
- return ENOMEM;
- }
- pi->regram_saved = regaddr; /* save orig value for free's usage */
- pi->regram = (struct musycc_groupr *) ((unsigned long) (regaddr + GROUP_BOUNDARY - 1) &
- (~(GROUP_BOUNDARY - 1))); /* this calculates
- * closest boundary */
+ regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
+ if (regaddr == 0)
+ {
+ for (gchan = 0; gchan < i; gchan++)
+ {
+ pi = &ci->port[gchan];
+ OS_kfree (pi->reg);
+ pi->reg = 0;
+ }
+ return ENOMEM;
+ }
+ pi->regram_saved = regaddr; /* save orig value for free's usage */
+ pi->regram = (struct musycc_groupr *) ((unsigned long) (regaddr + GROUP_BOUNDARY - 1) &
+ (~(GROUP_BOUNDARY - 1))); /* this calculates
+ * closest boundary */
}
/* any board centric MUSYCC commands will use group ZERO as its "home" */
@@ -858,7 +858,7 @@ musycc_init (ci_t * ci)
FLUSH_MEM_WRITE ();
ci->state = C_RUNNING; /* mark as full interrupt processing
- * available */
+ * available */
musycc_serv_req (&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
@@ -866,19 +866,19 @@ musycc_init (ci_t * ci)
if (cxt1e1_max_mru > 0xffe)
{
- pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
- cxt1e1_max_mru, 0xffe);
- cxt1e1_max_mru = 0xffe;
+ pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
+ cxt1e1_max_mru, 0xffe);
+ cxt1e1_max_mru = 0xffe;
}
if (cxt1e1_max_mtu > 0xffe)
{
- pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
- cxt1e1_max_mtu, 0xffe);
- cxt1e1_max_mtu = 0xffe;
+ pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
+ cxt1e1_max_mtu, 0xffe);
+ cxt1e1_max_mtu = 0xffe;
}
#ifdef SBE_WAN256T3_ENABLE
for (i = 0; i < MUSYCC_NPORTS; i++)
- musycc_init_port (&ci->port[i]);
+ musycc_init_port (&ci->port[i]);
#endif
return SBE_DRVR_SUCCESS; /* no error */
@@ -902,13 +902,13 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
ch = pi->chan[gchan];
if (ch == 0 || ch->state != UP)
{
- if (cxt1e1_log_level >= LOG_ERROR)
- pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
- pi->up->devname, gchan);
+ if (cxt1e1_log_level >= LOG_ERROR)
+ pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
+ pi->up->devname, gchan);
}
if (ch == 0 || ch->mdt == 0)
- return; /* note: mdt==0 implies a malloc()
- * failure w/in chan_up() routine */
+ return; /* note: mdt==0 implies a malloc()
+ * failure w/in chan_up() routine */
#if 0
#ifdef SBE_ISR_INLINE
@@ -919,107 +919,107 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
#endif
do
{
- FLUSH_MEM_READ ();
- md = ch->txd_irq_srv;
- status = le32_to_cpu (md->status);
-
- /*
- * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
- * Transmit Buffer Descriptor during Transparent Mode.
- */
- if (status & MUSYCC_TX_OWNED)
- {
- int readCount, loopCount;
-
- /***********************************************************/
- /* HW Bug Fix */
- /* ---------- */
- /* Under certain PCI Bus loading conditions, the data */
- /* associated with an update of Shared Memory is delayed */
- /* relative to its PCI Interrupt. This is caught when */
- /* the host determines it does not yet OWN the descriptor. */
- /***********************************************************/
-
- readCount = 0;
- while (status & MUSYCC_TX_OWNED)
- {
- for (loopCount = 0; loopCount < 0x30; loopCount++)
- OS_uwait_dummy (); /* use call to avoid optimization
- * removal of dummy delay */
- FLUSH_MEM_READ ();
- status = le32_to_cpu (md->status);
- if (readCount++ > 40)
- break; /* don't wait any longer */
- }
- if (status & MUSYCC_TX_OWNED)
- {
- if (cxt1e1_log_level >= LOG_MONITOR)
- {
- pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
- pi->up->devname, pi->portnum, ch->channum,
- md, status);
- pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
- ch->user, ch->txd_irq_srv, ch->txd_usr_add,
- sd_queue_stopped (ch->user),
- ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
- musycc_dump_txbuffer_ring (ch, 0);
- }
- break; /* Not our mdesc, done */
- } else
- {
- if (cxt1e1_log_level >= LOG_MONITOR)
- pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
- pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
- }
- }
- ch->txd_irq_srv = md->snext;
-
- md->data = 0;
- if (md->mem_token != 0)
- {
- /* upcount channel */
- atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
- /* upcount card */
- atomic_sub (OS_mem_token_tlen (md->mem_token), &pi->up->tx_pending);
+ FLUSH_MEM_READ ();
+ md = ch->txd_irq_srv;
+ status = le32_to_cpu (md->status);
+
+ /*
+ * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
+ * Transmit Buffer Descriptor during Transparent Mode.
+ */
+ if (status & MUSYCC_TX_OWNED)
+ {
+ int readCount, loopCount;
+
+ /***********************************************************/
+ /* HW Bug Fix */
+ /* ---------- */
+ /* Under certain PCI Bus loading conditions, the data */
+ /* associated with an update of Shared Memory is delayed */
+ /* relative to its PCI Interrupt. This is caught when */
+ /* the host determines it does not yet OWN the descriptor. */
+ /***********************************************************/
+
+ readCount = 0;
+ while (status & MUSYCC_TX_OWNED)
+ {
+ for (loopCount = 0; loopCount < 0x30; loopCount++)
+ OS_uwait_dummy (); /* use call to avoid optimization
+ * removal of dummy delay */
+ FLUSH_MEM_READ ();
+ status = le32_to_cpu (md->status);
+ if (readCount++ > 40)
+ break; /* don't wait any longer */
+ }
+ if (status & MUSYCC_TX_OWNED)
+ {
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ {
+ pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
+ pi->up->devname, pi->portnum, ch->channum,
+ md, status);
+ pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
+ ch->user, ch->txd_irq_srv, ch->txd_usr_add,
+ sd_queue_stopped (ch->user),
+ ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
+ musycc_dump_txbuffer_ring (ch, 0);
+ }
+ break; /* Not our mdesc, done */
+ } else
+ {
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
+ pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
+ }
+ }
+ ch->txd_irq_srv = md->snext;
+
+ md->data = 0;
+ if (md->mem_token != 0)
+ {
+ /* upcount channel */
+ atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
+ /* upcount card */
+ atomic_sub (OS_mem_token_tlen (md->mem_token), &pi->up->tx_pending);
#ifdef SBE_WAN256T3_ENABLE
- if (!atomic_read (&pi->up->tx_pending))
- wan256t3_led (pi->up, LED_TX, 0);
+ if (!atomic_read (&pi->up->tx_pending))
+ wan256t3_led (pi->up, LED_TX, 0);
#endif
#ifdef CONFIG_SBE_WAN256T3_NCOMM
- /* callback that our packet was sent */
- {
- int hdlcnum = (pi->portnum * 32 + gchan);
-
- if (hdlcnum >= 228)
- {
- if (nciProcess_TX_complete)
- (*nciProcess_TX_complete) (hdlcnum,
- getuserbychan (gchan));
- }
- }
+ /* callback that our packet was sent */
+ {
+ int hdlcnum = (pi->portnum * 32 + gchan);
+
+ if (hdlcnum >= 228)
+ {
+ if (nciProcess_TX_complete)
+ (*nciProcess_TX_complete) (hdlcnum,
+ getuserbychan (gchan));
+ }
+ }
#endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
- OS_mem_token_free_irq (md->mem_token);
- md->mem_token = 0;
- }
- md->status = 0;
+ OS_mem_token_free_irq (md->mem_token);
+ md->mem_token = 0;
+ }
+ md->status = 0;
#ifdef RLD_TXFULL_DEBUG
- if (cxt1e1_log_level >= LOG_MONITOR2)
- pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
- ch->tx_full, ch->txd_free, ch->txd_free + 1);
+ if (cxt1e1_log_level >= LOG_MONITOR2)
+ pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
+ ch->tx_full, ch->txd_free, ch->txd_free + 1);
#endif
- ++ch->txd_free;
- FLUSH_MEM_WRITE ();
-
- if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE))
- {
- if (cxt1e1_log_level >= LOG_MONITOR)
- pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
- pi->up->devname, ch->p.chan_mode, status);
- if ((status & EOMIRQ_ENABLE) == 0)
- break;
- }
+ ++ch->txd_free;
+ FLUSH_MEM_WRITE ();
+
+ if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE))
+ {
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
+ pi->up->devname, ch->p.chan_mode, status);
+ if ((status & EOMIRQ_ENABLE) == 0)
+ break;
+ }
}
while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
/*
@@ -1036,33 +1036,33 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
*/
if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2)))
{
- /*
- * Then, only releave task stoppage if we actually have enough
- * buffers to service the last requested packet. It may require MORE
- * than half the available!
- */
- if (ch->txd_free >= ch->txd_required)
- {
+ /*
+ * Then, only releave task stoppage if we actually have enough
+ * buffers to service the last requested packet. It may require MORE
+ * than half the available!
+ */
+ if (ch->txd_free >= ch->txd_required)
+ {
#ifdef RLD_TXFULL_DEBUG
- if (cxt1e1_log_level >= LOG_MONITOR2)
- pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
- ch->channum,
- ch->txd_free, ch->txd_num / 2);
+ if (cxt1e1_log_level >= LOG_MONITOR2)
+ pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
+ ch->channum,
+ ch->txd_free, ch->txd_num / 2);
#endif
- ch->tx_full = 0;
- ch->txd_required = 0;
- sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
- * channel */
- }
+ ch->tx_full = 0;
+ ch->txd_required = 0;
+ sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
+ * channel */
+ }
}
#ifdef RLD_TXFULL_DEBUG
else if (ch->tx_full)
{
- if (cxt1e1_log_level >= LOG_MONITOR2)
- pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
- ch->channum,
- ch->txd_free, ch->txd_num / 2);
+ if (cxt1e1_log_level >= LOG_MONITOR2)
+ pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
+ ch->channum,
+ ch->txd_free, ch->txd_num / 2);
}
#endif
@@ -1089,81 +1089,81 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
ch = pi->chan[gchan];
if (ch == 0 || ch->state != UP)
{
- if (cxt1e1_log_level > LOG_ERROR)
- pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
- pi->up->devname, gchan);
- return;
+ if (cxt1e1_log_level > LOG_ERROR)
+ pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
+ pi->up->devname, gchan);
+ return;
}
if (ch->mdr == 0)
- return; /* can this happen ? */
+ return; /* can this happen ? */
for (;;)
{
- FLUSH_MEM_READ ();
- md = &ch->mdr[ch->rxix_irq_srv];
- status = le32_to_cpu (md->status);
- if (!(status & HOST_RX_OWNED))
- break; /* Not our mdesc, done */
- m = md->mem_token;
- error = (status >> 16) & 0xf;
- if (error == 0)
- {
+ FLUSH_MEM_READ ();
+ md = &ch->mdr[ch->rxix_irq_srv];
+ status = le32_to_cpu (md->status);
+ if (!(status & HOST_RX_OWNED))
+ break; /* Not our mdesc, done */
+ m = md->mem_token;
+ error = (status >> 16) & 0xf;
+ if (error == 0)
+ {
#ifdef CONFIG_SBE_WAN256T3_NCOMM
- int hdlcnum = (pi->portnum * 32 + gchan);
-
- /*
- * if the packet number belongs to NCOMM, then send it to the TMS
- * driver
- */
- if (hdlcnum >= 228)
- {
- if (nciProcess_RX_packet)
- (*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
- } else
+ int hdlcnum = (pi->portnum * 32 + gchan);
+
+ /*
+ * if the packet number belongs to NCOMM, then send it to the TMS
+ * driver
+ */
+ if (hdlcnum >= 228)
+ {
+ if (nciProcess_RX_packet)
+ (*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
+ } else
#endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
- {
- if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru)))
- {
- /* substitute the mbuf+cluster */
- md->mem_token = m2;
- md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
-
- /* pass the received mbuf upward */
- sd_recv_consume (m, status & LENGTH_MASK, ch->user);
- ch->s.rx_packets++;
- ch->s.rx_bytes += status & LENGTH_MASK;
- } else
- {
- ch->s.rx_dropped++;
- }
- }
- } else if (error == ERR_FCS)
- {
- ch->s.rx_crc_errors++;
- } else if (error == ERR_ALIGN)
- {
- ch->s.rx_missed_errors++;
- } else if (error == ERR_ABT)
- {
- ch->s.rx_missed_errors++;
- } else if (error == ERR_LNG)
- {
- ch->s.rx_length_errors++;
- } else if (error == ERR_SHT)
- {
- ch->s.rx_length_errors++;
- }
- FLUSH_MEM_WRITE ();
- status = cxt1e1_max_mru;
- if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
- status |= EOBIRQ_ENABLE;
- md->status = cpu_to_le32 (status);
-
- /* Check next mdesc in the ring */
- if (++ch->rxix_irq_srv >= ch->rxd_num)
- ch->rxix_irq_srv = 0;
- FLUSH_MEM_WRITE ();
+ {
+ if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru)))
+ {
+ /* substitute the mbuf+cluster */
+ md->mem_token = m2;
+ md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
+
+ /* pass the received mbuf upward */
+ sd_recv_consume (m, status & LENGTH_MASK, ch->user);
+ ch->s.rx_packets++;
+ ch->s.rx_bytes += status & LENGTH_MASK;
+ } else
+ {
+ ch->s.rx_dropped++;
+ }
+ }
+ } else if (error == ERR_FCS)
+ {
+ ch->s.rx_crc_errors++;
+ } else if (error == ERR_ALIGN)
+ {
+ ch->s.rx_missed_errors++;
+ } else if (error == ERR_ABT)
+ {
+ ch->s.rx_missed_errors++;
+ } else if (error == ERR_LNG)
+ {
+ ch->s.rx_length_errors++;
+ } else if (error == ERR_SHT)
+ {
+ ch->s.rx_length_errors++;
+ }
+ FLUSH_MEM_WRITE ();
+ status = cxt1e1_max_mru;
+ if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
+ status |= EOBIRQ_ENABLE;
+ md->status = cpu_to_le32 (status);
+
+ /* Check next mdesc in the ring */
+ if (++ch->rxix_irq_srv >= ch->rxd_num)
+ ch->rxix_irq_srv = 0;
+ FLUSH_MEM_WRITE ();
}
}
@@ -1181,7 +1181,7 @@ musycc_intr_th_handler (void *devp)
*/
if (ci->state == C_INIT)
{
- return IRQ_NONE;
+ return IRQ_NONE;
}
/*
* Marked as hardware available. Don't service interrupts, just clear the
@@ -1190,11 +1190,11 @@ musycc_intr_th_handler (void *devp)
if (ci->state == C_IDLE)
{
- status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
+ status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
- /* clear the interrupt but process nothing else */
- pci_write_32 ((u_int32_t *) &ci->reg->isd, status);
- return IRQ_HANDLED;
+ /* clear the interrupt but process nothing else */
+ pci_write_32 ((u_int32_t *) &ci->reg->isd, status);
+ return IRQ_HANDLED;
}
FLUSH_PCI_READ ();
FLUSH_MEM_READ ();
@@ -1220,20 +1220,20 @@ musycc_intr_th_handler (void *devp)
if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new))
{
- if (cxt1e1_log_level >= LOG_MONITOR)
- {
- pr_info("%s: note - updated ISD from %08x to %08x\n",
- ci->devname, status,
- (status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
- }
- /*
- * Replace bogus status with software corrected value.
- *
- * It's not known whether, during this problem occurrence, if the
- * INTFULL bit is correctly reported or not.
- */
- status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
- nextInt = INTRPTS_NEXTINT (status);
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ {
+ pr_info("%s: note - updated ISD from %08x to %08x\n",
+ ci->devname, status,
+ (status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
+ }
+ /*
+ * Replace bogus status with software corrected value.
+ *
+ * It's not known whether, during this problem occurrence, if the
+ * INTFULL bit is correctly reported or not.
+ */
+ status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
+ nextInt = INTRPTS_NEXTINT (status);
}
/**********************************************/
/* Cn847x Bug Fix */
@@ -1244,42 +1244,42 @@ musycc_intr_th_handler (void *devp)
if (intCnt == INT_QUEUE_SIZE)
{
- currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
+ currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
} else
- /************************************************/
- /* Interrupt Write Location Issues */
- /* ------------------------------- */
- /* When the interrupt status descriptor is */
- /* written, the interrupt line is de-asserted */
- /* by the Cn847x. In the case of MIPS */
- /* microprocessors, this must occur at the */
- /* beginning of the interrupt handler so that */
- /* the interrupt handle is not re-entered due */
- /* to interrupt dis-assertion latency. */
- /* In the case of all other processors, this */
- /* action should occur at the end of the */
- /* interrupt handler to avoid overwriting the */
- /* interrupt queue. */
- /************************************************/
+ /************************************************/
+ /* Interrupt Write Location Issues */
+ /* ------------------------------- */
+ /* When the interrupt status descriptor is */
+ /* written, the interrupt line is de-asserted */
+ /* by the Cn847x. In the case of MIPS */
+ /* microprocessors, this must occur at the */
+ /* beginning of the interrupt handler so that */
+ /* the interrupt handle is not re-entered due */
+ /* to interrupt dis-assertion latency. */
+ /* In the case of all other processors, this */
+ /* action should occur at the end of the */
+ /* interrupt handler to avoid overwriting the */
+ /* interrupt queue. */
+ /************************************************/
if (intCnt)
{
- currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
+ currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
} else
{
- /*
- * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
- * can be indicative of a Shared Interrupt chain. Our driver can be
- * called from the system's interrupt handler as a matter of the OS
- * walking the chain. As the chain is walked, the interrupt will
- * eventually be serviced by the correct driver/handler.
- */
+ /*
+ * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
+ * can be indicative of a Shared Interrupt chain. Our driver can be
+ * called from the system's interrupt handler as a matter of the OS
+ * walking the chain. As the chain is walked, the interrupt will
+ * eventually be serviced by the correct driver/handler.
+ */
#if 0
- /* chained interrupt = not ours */
- pr_info(">> %s: intCnt NULL, sts %x, possibly a chained interrupt!\n",
- ci->devname, status);
+ /* chained interrupt = not ours */
+ pr_info(">> %s: intCnt NULL, sts %x, possibly a chained interrupt!\n",
+ ci->devname, status);
#endif
- return IRQ_NONE;
+ return IRQ_NONE;
}
ci->iqp_tailx = currInt;
@@ -1290,12 +1290,12 @@ musycc_intr_th_handler (void *devp)
if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
{
- pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
+ pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
}
if (cxt1e1_log_level >= LOG_DEBUG)
- pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
- ci->devname, &ci->reg->isd,
- status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
+ pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
+ ci->devname, &ci->reg->isd,
+ status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
FLUSH_MEM_WRITE ();
#if defined(SBE_ISR_TASKLET)
@@ -1339,18 +1339,18 @@ musycc_intr_bh_tasklet (ci_t * ci)
if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT))
{
#if defined(SBE_ISR_IMMEDIATE)
- return 0L;
+ return 0L;
#else
- return;
+ return;
#endif
}
#if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
if (drvr_state != SBE_DRVR_AVAILABLE)
{
#if defined(SBE_ISR_TASKLET)
- return;
+ return;
#elif defined(SBE_ISR_IMMEDIATE)
- return 0L;
+ return 0L;
#endif
}
#elif defined(SBE_ISR_INLINE)
@@ -1360,271 +1360,271 @@ musycc_intr_bh_tasklet (ci_t * ci)
ci->intlog.drvr_intr_bhcount++;
FLUSH_MEM_READ ();
{
- unsigned int bh = atomic_read (&ci->bh_pending);
+ unsigned int bh = atomic_read (&ci->bh_pending);
- max_bh = max (bh, max_bh);
+ max_bh = max (bh, max_bh);
}
atomic_set (&ci->bh_pending, 0);/* if here, no longer pending */
while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx))
{
- intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
- currInt = le32_to_cpu (ci->iqd_p[headx]);
-
- max_intcnt = max (intCnt, max_intcnt); /* RLD DEBUG */
-
- /**************************************************/
- /* HW Bug Fix */
- /* ---------- */
- /* The following code checks for the condition */
- /* of interrupt assertion before interrupt */
- /* queue update. This is a problem on several */
- /* PCI-Local bridge chips found on some products. */
- /**************************************************/
-
- readCount = 0;
- if ((currInt == badInt) || (currInt == badInt2))
- ci->intlog.drvr_int_failure++;
-
- while ((currInt == badInt) || (currInt == badInt2))
- {
- for (loopCount = 0; loopCount < 0x30; loopCount++)
- OS_uwait_dummy (); /* use call to avoid optimization removal
- * of dummy delay */
- FLUSH_MEM_READ ();
- currInt = le32_to_cpu (ci->iqd_p[headx]);
- if (readCount++ > 20)
- break;
- }
-
- if ((currInt == badInt) || (currInt == badInt2)) /* catch failure of Bug
- * Fix checking */
- {
- if (cxt1e1_log_level >= LOG_WARN)
- pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
- ci->devname, &ci->iqd_p[headx], headx);
-
- /*
- * If the descriptor has not recovered, then leaving the EMPTY
- * entry set will not signal to the MUSYCC that this descriptor
- * has been serviced. The Interrupt Queue can then start losing
- * available descriptors and MUSYCC eventually encounters and
- * reports the INTFULL condition. Per manual, changing any bit
- * marks descriptor as available, thus the use of different
- * EMPTY_ENTRY values.
- */
-
- if (currInt == badInt)
- {
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
- } else
- {
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
- }
- ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
- FLUSH_MEM_WRITE ();
- FLUSH_MEM_READ ();
- continue;
- }
- group = INTRPT_GRP (currInt);
- gchan = INTRPT_CH (currInt);
- event = INTRPT_EVENT (currInt);
- err = INTRPT_ERROR (currInt);
- tx = currInt & INTRPT_DIR_M;
-
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
- FLUSH_MEM_WRITE ();
-
- if (cxt1e1_log_level >= LOG_DEBUG)
- {
- if (err != 0)
- pr_info(" %08x -> err: %2d,", currInt, err);
-
- pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
- event, group, gchan, tx ? 'T' : 'R');
- }
- pi = &ci->port[group]; /* notice that here we assume 1-1 group -
- * port mapping */
- ch = pi->chan[gchan];
- switch (event)
- {
- case EVE_SACK: /* Service Request Acknowledge */
- if (cxt1e1_log_level >= LOG_DEBUG)
- {
- volatile u_int32_t r;
-
- r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
- pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
- }
- SD_SEM_GIVE (&pi->sr_sem_wait); /* wake up waiting process */
- break;
- case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
- case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
- break;
- case EVE_EOM: /* End Of Message */
- case EVE_EOB: /* End Of Buffer (Transparent mode) */
- if (tx)
- {
- musycc_bh_tx_eom (pi, gchan);
- } else
- {
- musycc_bh_rx_eom (pi, gchan);
- }
+ intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
+ currInt = le32_to_cpu (ci->iqd_p[headx]);
+
+ max_intcnt = max (intCnt, max_intcnt); /* RLD DEBUG */
+
+ /**************************************************/
+ /* HW Bug Fix */
+ /* ---------- */
+ /* The following code checks for the condition */
+ /* of interrupt assertion before interrupt */
+ /* queue update. This is a problem on several */
+ /* PCI-Local bridge chips found on some products. */
+ /**************************************************/
+
+ readCount = 0;
+ if ((currInt == badInt) || (currInt == badInt2))
+ ci->intlog.drvr_int_failure++;
+
+ while ((currInt == badInt) || (currInt == badInt2))
+ {
+ for (loopCount = 0; loopCount < 0x30; loopCount++)
+ OS_uwait_dummy (); /* use call to avoid optimization removal
+ * of dummy delay */
+ FLUSH_MEM_READ ();
+ currInt = le32_to_cpu (ci->iqd_p[headx]);
+ if (readCount++ > 20)
+ break;
+ }
+
+ if ((currInt == badInt) || (currInt == badInt2)) /* catch failure of Bug
+ * Fix checking */
+ {
+ if (cxt1e1_log_level >= LOG_WARN)
+ pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
+ ci->devname, &ci->iqd_p[headx], headx);
+
+ /*
+ * If the descriptor has not recovered, then leaving the EMPTY
+ * entry set will not signal to the MUSYCC that this descriptor
+ * has been serviced. The Interrupt Queue can then start losing
+ * available descriptors and MUSYCC eventually encounters and
+ * reports the INTFULL condition. Per manual, changing any bit
+ * marks descriptor as available, thus the use of different
+ * EMPTY_ENTRY values.
+ */
+
+ if (currInt == badInt)
+ {
+ ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
+ } else
+ {
+ ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
+ }
+ ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
+ FLUSH_MEM_WRITE ();
+ FLUSH_MEM_READ ();
+ continue;
+ }
+ group = INTRPT_GRP (currInt);
+ gchan = INTRPT_CH (currInt);
+ event = INTRPT_EVENT (currInt);
+ err = INTRPT_ERROR (currInt);
+ tx = currInt & INTRPT_DIR_M;
+
+ ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
+ FLUSH_MEM_WRITE ();
+
+ if (cxt1e1_log_level >= LOG_DEBUG)
+ {
+ if (err != 0)
+ pr_info(" %08x -> err: %2d,", currInt, err);
+
+ pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
+ event, group, gchan, tx ? 'T' : 'R');
+ }
+ pi = &ci->port[group]; /* notice that here we assume 1-1 group -
+ * port mapping */
+ ch = pi->chan[gchan];
+ switch (event)
+ {
+ case EVE_SACK: /* Service Request Acknowledge */
+ if (cxt1e1_log_level >= LOG_DEBUG)
+ {
+ volatile u_int32_t r;
+
+ r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
+ pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
+ }
+ SD_SEM_GIVE (&pi->sr_sem_wait); /* wake up waiting process */
+ break;
+ case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
+ case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
+ break;
+ case EVE_EOM: /* End Of Message */
+ case EVE_EOB: /* End Of Buffer (Transparent mode) */
+ if (tx)
+ {
+ musycc_bh_tx_eom (pi, gchan);
+ } else
+ {
+ musycc_bh_rx_eom (pi, gchan);
+ }
#if 0
- break;
+ break;
#else
- /*
- * MUSYCC Interrupt Descriptor section states that EOB and EOM
- * can be combined with the NONE error (as well as others). So
- * drop thru to catch this...
- */
+ /*
+ * MUSYCC Interrupt Descriptor section states that EOB and EOM
+ * can be combined with the NONE error (as well as others). So
+ * drop thru to catch this...
+ */
#endif
- case EVE_NONE:
- if (err == ERR_SHT)
- {
- ch->s.rx_length_errors++;
- }
- break;
- default:
- if (cxt1e1_log_level >= LOG_WARN)
- pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
- event, headx, currInt, group);
- break;
- } /* switch on event */
-
-
- /*
- * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
- * are service-affecting and require action to resume normal
- * bit-level processing.
- */
-
- switch (err)
- {
- case ERR_ONR:
- /*
- * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
- * error requires Transmit channel reactivation.
- *
- * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
- * requires Receive channel reactivation.
- */
- if (tx)
- {
-
- /*
- * TX ONR Error only occurs when channel is configured for
- * Transparent Mode. However, this code will catch and
- * re-activate on ANY TX ONR error.
- */
-
- /*
- * Set flag to re-enable on any next transmit attempt.
- */
- ch->ch_start_tx = CH_START_TX_ONR;
-
- {
+ case EVE_NONE:
+ if (err == ERR_SHT)
+ {
+ ch->s.rx_length_errors++;
+ }
+ break;
+ default:
+ if (cxt1e1_log_level >= LOG_WARN)
+ pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
+ event, headx, currInt, group);
+ break;
+ } /* switch on event */
+
+
+ /*
+ * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
+ * are service-affecting and require action to resume normal
+ * bit-level processing.
+ */
+
+ switch (err)
+ {
+ case ERR_ONR:
+ /*
+ * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
+ * error requires Transmit channel reactivation.
+ *
+ * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
+ * requires Receive channel reactivation.
+ */
+ if (tx)
+ {
+
+ /*
+ * TX ONR Error only occurs when channel is configured for
+ * Transparent Mode. However, this code will catch and
+ * re-activate on ANY TX ONR error.
+ */
+
+ /*
+ * Set flag to re-enable on any next transmit attempt.
+ */
+ ch->ch_start_tx = CH_START_TX_ONR;
+
+ {
#ifdef RLD_TRANS_DEBUG
- if (1 || cxt1e1_log_level >= LOG_MONITOR)
+ if (1 || cxt1e1_log_level >= LOG_MONITOR)
#else
- if (cxt1e1_log_level >= LOG_MONITOR)
+ if (cxt1e1_log_level >= LOG_MONITOR)
#endif
- {
- pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
- ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
+ {
+ pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
+ ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
#ifdef RLD_DEBUG
- if (ch->p.chan_mode == 2) /* problem = ONR on HDLC
- * mode */
- {
- pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
- (u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
- sd_queue_stopped (ch->user),
- ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
- musycc_dump_txbuffer_ring (ch, 0);
- }
+ if (ch->p.chan_mode == 2) /* problem = ONR on HDLC
+ * mode */
+ {
+ pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
+ (u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
+ sd_queue_stopped (ch->user),
+ ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
+ musycc_dump_txbuffer_ring (ch, 0);
+ }
#endif
- }
- }
- } else /* RX buffer overrun */
- {
- /*
- * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
- * channel recovery for this RX ONR error IS required. It is
- * also suggested to increase the number of receive buffers
- * for this channel. Receive channel reactivation IS
- * required, and data has been lost.
- */
- ch->s.rx_over_errors++;
- ch->ch_start_rx = CH_START_RX_ONR;
-
- if (cxt1e1_log_level >= LOG_WARN)
- {
- pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
- ci->devname, ch->channum, ch->p.chan_mode);
- //musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
- }
- }
- musycc_chan_restart (ch);
- break;
- case ERR_BUF:
- if (tx)
- {
- ch->s.tx_fifo_errors++;
- ch->ch_start_tx = CH_START_TX_BUF;
- /*
- * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
- * this BUFF error requires Transmit channel reactivation.
- */
- if (cxt1e1_log_level >= LOG_MONITOR)
- pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
- ci->devname, ch->channum, ch->p.chan_mode);
- } else /* RX buffer overrun */
- {
- ch->s.rx_over_errors++;
- /*
- * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
- * mode requires NO recovery for this RX BUFF error is
- * required. It is suggested to increase the FIFO buffer
- * space for this channel. Receive channel reactivation is
- * not required, but data has been lost.
- */
- if (cxt1e1_log_level >= LOG_WARN)
- pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
- ci->devname, ch->channum, ch->p.chan_mode);
- /*
- * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
- * Transparent mode DOES require recovery for the RX BUFF
- * error. It is suggested to increase the FIFO buffer space
- * for this channel. Receive channel reactivation IS
- * required and data has been lost.
- */
- if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
- ch->ch_start_rx = CH_START_RX_BUF;
- }
-
- if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
- musycc_chan_restart (ch);
- break;
- default:
- break;
- } /* switch on err */
-
- /* Check for interrupt lost condition */
- if ((currInt & INTRPT_ILOST_M) && (cxt1e1_log_level >= LOG_ERROR))
- {
- pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
- ci->devname);
- }
- ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
- FLUSH_MEM_WRITE ();
- FLUSH_MEM_READ ();
+ }
+ }
+ } else /* RX buffer overrun */
+ {
+ /*
+ * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
+ * channel recovery for this RX ONR error IS required. It is
+ * also suggested to increase the number of receive buffers
+ * for this channel. Receive channel reactivation IS
+ * required, and data has been lost.
+ */
+ ch->s.rx_over_errors++;
+ ch->ch_start_rx = CH_START_RX_ONR;
+
+ if (cxt1e1_log_level >= LOG_WARN)
+ {
+ pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
+ ci->devname, ch->channum, ch->p.chan_mode);
+ //musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
+ }
+ }
+ musycc_chan_restart (ch);
+ break;
+ case ERR_BUF:
+ if (tx)
+ {
+ ch->s.tx_fifo_errors++;
+ ch->ch_start_tx = CH_START_TX_BUF;
+ /*
+ * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
+ * this BUFF error requires Transmit channel reactivation.
+ */
+ if (cxt1e1_log_level >= LOG_MONITOR)
+ pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
+ ci->devname, ch->channum, ch->p.chan_mode);
+ } else /* RX buffer overrun */
+ {
+ ch->s.rx_over_errors++;
+ /*
+ * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
+ * mode requires NO recovery for this RX BUFF error is
+ * required. It is suggested to increase the FIFO buffer
+ * space for this channel. Receive channel reactivation is
+ * not required, but data has been lost.
+ */
+ if (cxt1e1_log_level >= LOG_WARN)
+ pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
+ ci->devname, ch->channum, ch->p.chan_mode);
+ /*
+ * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
+ * Transparent mode DOES require recovery for the RX BUFF
+ * error. It is suggested to increase the FIFO buffer space
+ * for this channel. Receive channel reactivation IS
+ * required and data has been lost.
+ */
+ if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
+ ch->ch_start_rx = CH_START_RX_BUF;
+ }
+
+ if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
+ musycc_chan_restart (ch);
+ break;
+ default:
+ break;
+ } /* switch on err */
+
+ /* Check for interrupt lost condition */
+ if ((currInt & INTRPT_ILOST_M) && (cxt1e1_log_level >= LOG_ERROR))
+ {
+ pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
+ ci->devname);
+ }
+ ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
+ FLUSH_MEM_WRITE ();
+ FLUSH_MEM_READ ();
} /* while */
if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx))
{
- int bh;
+ int bh;
- bh = atomic_read (&CI->bh_pending);
- pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
- ci->iqp_headx, ci->iqp_tailx, bh);
+ bh = atomic_read (&CI->bh_pending);
+ pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
+ ci->iqp_headx, ci->iqp_tailx, bh);
}
#if defined(SBE_ISR_IMMEDIATE)
return 0L;
@@ -1641,7 +1641,7 @@ musycc_new_chan (ci_t * ci, int channum, void *user)
ch = ci->port[channum / MUSYCC_NCHANS].chan[channum % MUSYCC_NCHANS];
if (ch->state != UNASSIGNED)
- return EEXIST;
+ return EEXIST;
/* NOTE: mch_t already cleared during OS_kmalloc() */
ch->state = DOWN;
ch->user = user;
@@ -1670,7 +1670,7 @@ musycc_chan_down (ci_t * dummy, int channum)
int i, gchan;
if (!(ch = sd_find_chan (dummy, channum)))
- return EINVAL;
+ return EINVAL;
pi = ch->up;
gchan = ch->gchan;
@@ -1681,7 +1681,7 @@ musycc_chan_down (ci_t * dummy, int channum)
ch->ch_start_tx = 0;
if (ch->state == DOWN)
- return 0;
+ return 0;
ch->state = DOWN;
pi->regram->thp[gchan] = 0;
@@ -1691,14 +1691,14 @@ musycc_chan_down (ci_t * dummy, int channum)
FLUSH_MEM_WRITE ();
for (i = 0; i < ch->txd_num; i++)
{
- if (ch->mdt[i].mem_token != 0)
- OS_mem_token_free (ch->mdt[i].mem_token);
+ if (ch->mdt[i].mem_token != 0)
+ OS_mem_token_free (ch->mdt[i].mem_token);
}
for (i = 0; i < ch->rxd_num; i++)
{
- if (ch->mdr[i].mem_token != 0)
- OS_mem_token_free (ch->mdr[i].mem_token);
+ if (ch->mdr[i].mem_token != 0)
+ OS_mem_token_free (ch->mdr[i].mem_token);
}
OS_kfree (ch->mdr);
@@ -1723,11 +1723,11 @@ musycc_del_chan (ci_t * ci, int channum)
mch_t *ch;
if ((channum < 0) || (channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS))) /* sanity chk param */
- return ECHRNG;
+ return ECHRNG;
if (!(ch = sd_find_chan (ci, channum)))
- return ENOENT;
+ return ENOENT;
if (ch->state == UP)
- musycc_chan_down (ci, channum);
+ musycc_chan_down (ci, channum);
ch->state = UNASSIGNED;
return 0;
}
@@ -1739,9 +1739,9 @@ musycc_del_chan_stats (ci_t * ci, int channum)
mch_t *ch;
if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
- return ECHRNG;
+ return ECHRNG;
if (!(ch = sd_find_chan (ci, channum)))
- return ENOENT;
+ return ENOENT;
memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
return 0;
@@ -1761,15 +1761,15 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
u_int32_t len;
if (!(ch = sd_find_chan (ci, channum)))
- return -ENOENT;
+ return -ENOENT;
if (ci->state != C_RUNNING) /* full interrupt processing available */
- return -EINVAL;
+ return -EINVAL;
if (ch->state != UP)
- return -EINVAL;
+ return -EINVAL;
if (!(ch->status & TX_ENABLED))
- return -EROFS; /* how else to flag unwritable state ? */
+ return -EROFS; /* how else to flag unwritable state ? */
#ifdef RLD_TRANS_DEBUGx
if (1 || cxt1e1_log_level >= LOG_MONITOR2)
@@ -1777,9 +1777,9 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
if (cxt1e1_log_level >= LOG_MONITOR2)
#endif
{
- pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
- channum, ch->state, ch->ch_start_tx, ch->tx_full,
- ch->txd_free, ch->txd_required, sd_queue_stopped (ch->user));
+ pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
+ channum, ch->state, ch->ch_start_tx, ch->tx_full,
+ ch->txd_free, ch->txd_required, sd_queue_stopped (ch->user));
}
/***********************************************/
/** Determine total amount of data to be sent **/
@@ -1787,35 +1787,35 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
m2 = mem_token;
txd_need_cnt = 0;
for (len = OS_mem_token_tlen (m2); len > 0;
- m2 = (void *) OS_mem_token_next (m2))
+ m2 = (void *) OS_mem_token_next (m2))
{
- if (!OS_mem_token_len (m2))
- continue;
- txd_need_cnt++;
- len -= OS_mem_token_len (m2);
+ if (!OS_mem_token_len (m2))
+ continue;
+ txd_need_cnt++;
+ len -= OS_mem_token_len (m2);
}
if (txd_need_cnt == 0)
{
- if (cxt1e1_log_level >= LOG_MONITOR2)
- pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
- OS_mem_token_free (mem_token);
- return 0; /* no data to send */
+ if (cxt1e1_log_level >= LOG_MONITOR2)
+ pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
+ OS_mem_token_free (mem_token);
+ return 0; /* no data to send */
}
/*************************************************/
/** Are there sufficient descriptors available? **/
/*************************************************/
if (txd_need_cnt > ch->txd_num) /* never enough descriptors for this
- * large a buffer */
+ * large a buffer */
{
- if (cxt1e1_log_level >= LOG_DEBUG)
- {
- pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
- ch->txd_num, txd_need_cnt + 1);
- }
- ch->s.tx_dropped++;
- OS_mem_token_free (mem_token);
- return 0;
+ if (cxt1e1_log_level >= LOG_DEBUG)
+ {
+ pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
+ ch->txd_num, txd_need_cnt + 1);
+ }
+ ch->s.tx_dropped++;
+ OS_mem_token_free (mem_token);
+ return 0;
}
#if 0
spin_lock_irqsave (&ch->ch_txlock, flags);
@@ -1825,18 +1825,18 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
/************************************************************/
if (txd_need_cnt > ch->txd_free)
{
- if (cxt1e1_log_level >= LOG_MONITOR2)
- {
- pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
- channum, ch->txd_free, ch->txd_num, txd_need_cnt);
- }
- ch->tx_full = 1;
- ch->txd_required = txd_need_cnt;
- sd_disable_xmit (ch->user);
+ if (cxt1e1_log_level >= LOG_MONITOR2)
+ {
+ pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
+ channum, ch->txd_free, ch->txd_num, txd_need_cnt);
+ }
+ ch->tx_full = 1;
+ ch->txd_required = txd_need_cnt;
+ sd_disable_xmit (ch->user);
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore (&ch->ch_txlock, flags);
#endif
- return -EBUSY; /* tell user to try again later */
+ return -EBUSY; /* tell user to try again later */
}
/**************************************************/
/** Put the user data into MUSYCC data buffer(s) **/
@@ -1846,57 +1846,57 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2))
{
- int u = OS_mem_token_len (m2);
-
- if (!u)
- continue;
- len -= u;
-
- /*
- * Enable following chunks, yet wait to enable the FIRST chunk until
- * after ALL subsequent chunks are setup.
- */
- if (md != ch->txd_usr_add) /* not first chunk */
- u |= MUSYCC_TX_OWNED; /* transfer ownership from HOST to MUSYCC */
-
- if (len) /* not last chunk */
- u |= EOBIRQ_ENABLE;
- else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
- {
- /*
- * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
- * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
- * (IE. don't set herein).
- */
- u |= EOBIRQ_ENABLE;
- } else
- u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
-
-
- /* last chunk in hdlc mode */
- u |= (ch->p.idlecode << IDLE_CODE);
- if (ch->p.pad_fill_count)
- {
+ int u = OS_mem_token_len (m2);
+
+ if (!u)
+ continue;
+ len -= u;
+
+ /*
+ * Enable following chunks, yet wait to enable the FIRST chunk until
+ * after ALL subsequent chunks are setup.
+ */
+ if (md != ch->txd_usr_add) /* not first chunk */
+ u |= MUSYCC_TX_OWNED; /* transfer ownership from HOST to MUSYCC */
+
+ if (len) /* not last chunk */
+ u |= EOBIRQ_ENABLE;
+ else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
+ {
+ /*
+ * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
+ * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
+ * (IE. don't set herein).
+ */
+ u |= EOBIRQ_ENABLE;
+ } else
+ u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
+
+
+ /* last chunk in hdlc mode */
+ u |= (ch->p.idlecode << IDLE_CODE);
+ if (ch->p.pad_fill_count)
+ {
#if 0
- /* NOOP NOTE: u_int8_t cannot be > 0xFF */
- /* sanitize pad_fill_count for maximums allowed by hardware */
- if (ch->p.pad_fill_count > EXTRA_FLAGS_MASK)
- ch->p.pad_fill_count = EXTRA_FLAGS_MASK;
+ /* NOOP NOTE: u_int8_t cannot be > 0xFF */
+ /* sanitize pad_fill_count for maximums allowed by hardware */
+ if (ch->p.pad_fill_count > EXTRA_FLAGS_MASK)
+ ch->p.pad_fill_count = EXTRA_FLAGS_MASK;
#endif
- u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
- }
- md->mem_token = len ? 0 : mem_token; /* Fill in mds on last
- * segment, others set ZERO
- * so that entire token is
- * removed ONLY when ALL
- * segments have been
- * transmitted. */
-
- md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
- FLUSH_MEM_WRITE ();
- md->status = cpu_to_le32 (u);
- --ch->txd_free;
- md = md->snext;
+ u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
+ }
+ md->mem_token = len ? 0 : mem_token; /* Fill in mds on last
+ * segment, others set ZERO
+ * so that entire token is
+ * removed ONLY when ALL
+ * segments have been
+ * transmitted. */
+
+ md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
+ FLUSH_MEM_WRITE ();
+ md->status = cpu_to_le32 (u);
+ --ch->txd_free;
+ md = md->snext;
}
FLUSH_MEM_WRITE ();
@@ -1920,7 +1920,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
*/
if (ch->ch_start_tx)
{
- musycc_chan_restart (ch);
+ musycc_chan_restart (ch);
}
#ifdef SBE_WAN256T3_ENABLE
wan256t3_led (ci, LED_TX, LEDV_G);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 05/10] staging: cxt1e1: musycc.c: fixes brace placement
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (2 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 04/10] staging: cxt1e1: musycc.c: uses tabs for indentation Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses Johan Meiring
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit fixes incorrect brace placement as reported by the
checkpatch.pl tool.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.c | 314 +++++++++++----------------------------
1 file changed, 90 insertions(+), 224 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
index 5feac8a..42e1ca4 100644
--- a/drivers/staging/cxt1e1/musycc.c
+++ b/drivers/staging/cxt1e1/musycc.c
@@ -83,18 +83,13 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
int n;
if (lockit)
- {
spin_lock_irqsave (&ch->ch_rxlock, flags);
- }
if (ch->rxd_num == 0)
- {
pr_info(" ZERO receive buffers allocated for this channel.");
- } else
- {
+ else {
FLUSH_MEM_READ ();
m = &ch->mdr[ch->rxix_irq_srv];
- for (n = ch->rxd_num; n; n--)
- {
+ for (n = ch->rxd_num; n; n--) {
status = le32_to_cpu (m->status);
{
pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
@@ -138,9 +133,7 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
pr_info("\n");
if (lockit)
- {
spin_unlock_irqrestore (&ch->ch_rxlock, flags);
- }
return 0;
}
#endif
@@ -155,18 +148,13 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
int n;
if (lockit)
- {
spin_lock_irqsave (&ch->ch_txlock, flags);
- }
if (ch->txd_num == 0)
- {
pr_info(" ZERO transmit buffers allocated for this channel.");
- } else
- {
+ else {
FLUSH_MEM_READ ();
m = ch->txd_irq_srv;
- for (n = ch->txd_num; n; n--)
- {
+ for (n = ch->txd_num; n; n--) {
status = le32_to_cpu (m->status);
{
pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
@@ -185,8 +173,7 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
u_int32_t *dp;
int len = status & LENGTH_MASK;
- if (m->data)
- {
+ if (m->data) {
dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
if (len >= 0x10)
pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
@@ -206,9 +193,7 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
pr_info("\n");
if (lockit)
- {
spin_unlock_irqrestore (&ch->ch_txlock, flags);
- }
return 0;
}
#endif
@@ -225,9 +210,7 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
mch_t *ch;
if (chan >= MAX_CHANS_USED)
- {
return SBE_DRVR_FAIL; /* E2BIG */
- }
{
int bh;
@@ -241,8 +224,7 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
max_intcnt = 0; /* reset counter */
}
- if (!(ch = sd_find_chan (dummy, chan)))
- {
+ if (!(ch = sd_find_chan (dummy, chan))) {
pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
return ENOENT;
}
@@ -299,9 +281,7 @@ musycc_init_mdt (mpi_t * pi)
cfg = CFG_CH_FLAG_7E << IDLE_CODE;
for (i = 0; i < 32; addr++, i++)
- {
pci_write_32 (addr, cfg);
- }
}
@@ -314,18 +294,15 @@ musycc_update_tx_thp (mch_t * ch)
unsigned long flags;
spin_lock_irqsave (&ch->ch_txlock, flags);
- while (1)
- {
+ while (1) {
md = ch->txd_irq_srv;
FLUSH_MEM_READ ();
- if (!md->data)
- {
+ if (!md->data) {
/* No MDs with buffers to process */
spin_unlock_irqrestore (&ch->ch_txlock, flags);
return;
}
- if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)
- {
+ if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED) {
/* this is the MD to restart TX with */
break;
}
@@ -341,8 +318,7 @@ musycc_update_tx_thp (mch_t * ch)
ch->up->regram->thp[ch->gchan] = cpu_to_le32 (OS_vtophys (md));
FLUSH_MEM_WRITE ();
- if (ch->tx_full)
- {
+ if (ch->tx_full) {
ch->tx_full = 0;
ch->txd_required = 0;
sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
@@ -388,16 +364,14 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
/** check for RX restart request **/
/**********************************/
- if ((ch->ch_start_rx) && (ch->status & RX_ENABLED))
- {
+ if ((ch->ch_start_rx) && (ch->status & RX_ENABLED)) {
ch->ch_start_rx = 0;
#if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
{
static int hereb4 = 7;
- if (hereb4) /* RLD DEBUG */
- {
+ if (hereb4) { /* RLD DEBUG */
hereb4--;
#ifdef RLD_TRANS_DEBUG
md = &ch->mdr[ch->rxix_irq_srv];
@@ -420,8 +394,7 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
/** check for TX restart request **/
/**********************************/
- if ((ch->ch_start_tx) && (ch->status & TX_ENABLED))
- {
+ if ((ch->ch_start_tx) && (ch->status & TX_ENABLED)) {
/* find next unprocessed message, then set TX thp to it */
musycc_update_tx_thp (ch);
@@ -429,16 +402,14 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
spin_lock_irqsave (&ch->ch_txlock, flags);
#endif
md = ch->txd_irq_srv;
- if (!md)
- {
+ if (!md) {
#ifdef RLD_TRANS_DEBUG
pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
#endif
#if 0
spin_unlock_irqrestore (&ch->ch_txlock, flags);
#endif
- } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
- {
+ } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)) {
ch->ch_start_tx = 0;
#if 0
spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
@@ -450,8 +421,7 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
}
#ifdef RLD_RESTART_DEBUG
- else
- {
+ else {
/* retain request to start until retried and we have data to xmit */
pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
ch->channum, md,
@@ -523,8 +493,7 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
* group */
- if (pi->sr_last == req)
- {
+ if (pi->sr_last == req) {
#ifdef RLD_TRANS_DEBUG
pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
#endif
@@ -539,8 +508,7 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
r = (pi->sr_last & ~SR_GCHANNEL_MASK);
if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
- (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION)))
- {
+ (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION))) {
#ifdef RLD_TRANS_DEBUG
pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
#endif
@@ -548,8 +516,7 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
musycc_serv_req (pi, SR_NOOP);
SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
* original req */
- } else if (req == SR_NOOP)
- {
+ } else if (req == SR_NOOP) {
/* no need to issue back-to-back SR_NOOP commands at this time */
#ifdef RLD_TRANS_DEBUG
pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
@@ -576,8 +543,7 @@ rewrite:
* timing imposition */
- if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT))
- {
+ if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT)) {
if (cxt1e1_log_level >= LOG_MONITOR)
pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
pi->up->devname, rcnt, req, pi->sr_last, r,
@@ -586,15 +552,13 @@ rewrite:
* (reason not yet researched) */
goto rewrite;
}
- if (rcnt > MUSYCC_SR_RETRY_CNT)
- {
+ if (rcnt > MUSYCC_SR_RETRY_CNT) {
pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
return;
}
- if (req == SR_CHIP_RESET)
- {
+ if (req == SR_CHIP_RESET) {
/*
* PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
* the upcoming delay is used. Though the MUSYCC documentation
@@ -603,8 +567,7 @@ rewrite:
* suggesting this 'lack of ACK' workaround. Thus the use of uwait.
*/
OS_uwait (100000, "icard"); /* 100ms */
- } else
- {
+ } else {
FLUSH_MEM_READ ();
SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
* interrupt occurs */
@@ -620,8 +583,7 @@ musycc_update_timeslots (mpi_t * pi)
int i, ch;
char e1mode = IS_FRAME_ANY_E1 (pi->p.port_mode);
- for (i = 0; i < 32; i++)
- {
+ for (i = 0; i < 32; i++) {
int usedby = 0, last = 0, ts, j, bits[8];
u_int8_t lastval = 0;
@@ -629,18 +591,13 @@ musycc_update_timeslots (mpi_t * pi)
if (((i == 0) && e1mode) || /* disable if E1 mode */
((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
|| ((i > 23) && (!e1mode))) /* disable if T1 mode */
- {
pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
- } else
- {
+ else
pi->tsm[i] = 0x00; /* make tslot available for assignment */
- }
for (j = 0; j < 8; j++)
bits[j] = -1;
- for (ch = 0; ch < MUSYCC_NCHANS; ch++)
- {
- if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i]))
- {
+ for (ch = 0; ch < MUSYCC_NCHANS; ch++) {
+ if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i])) {
usedby++;
last = ch;
lastval = pi->chan[ch]->p.bitmask[i];
@@ -656,16 +613,14 @@ musycc_update_timeslots (mpi_t * pi)
ts = (4 << 5) | last;
else if ((usedby == 1) && (lastval == 0x7f))
ts = (5 << 5) | last;
- else
- {
+ else {
int idx;
if (bits[0] < 0)
ts = (6 << 5) | (idx = last);
else
ts = (7 << 5) | (idx = bits[0]);
- for (j = 1; j < 8; j++)
- {
+ for (j = 1; j < 8; j++) {
pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
}
@@ -699,8 +654,7 @@ musycc_update_timeslots (mpi_t * pi)
#ifdef SBE_WAN256T3_ENABLE
hmask = (0x1f << hyperdummy) & 0x1f;
#endif
- for (i = 0; i < 128; i++)
- {
+ for (i = 0; i < 128; i++) {
gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
ch = pi->chan[gchan];
if (ch->p.mode_56k)
@@ -727,8 +681,7 @@ musycc_chan_proto (int proto)
{
int reg;
- switch (proto)
- {
+ switch (proto) {
case CFG_CH_PROTO_TRANS: /* 0 */
reg = MUSYCC_CCD_TRANS;
break;
@@ -807,12 +760,9 @@ musycc_init (ci_t * ci)
* closest boundary */
for (i = 0; i < INT_QUEUE_SIZE; i++)
- {
ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
- }
- for (i = 0; i < ci->max_port; i++)
- {
+ for (i = 0; i < ci->max_port; i++) {
mpi_t *pi = &ci->port[i];
/*
@@ -823,10 +773,8 @@ musycc_init (ci_t * ci)
#define GROUP_BOUNDARY 0x800
regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
- if (regaddr == 0)
- {
- for (gchan = 0; gchan < i; gchan++)
- {
+ if (regaddr == 0) {
+ for (gchan = 0; gchan < i; gchan++) {
pi = &ci->port[gchan];
OS_kfree (pi->reg);
pi->reg = 0;
@@ -864,14 +812,12 @@ musycc_init (ci_t * ci)
/* sanity check settable parameters */
- if (cxt1e1_max_mru > 0xffe)
- {
+ if (cxt1e1_max_mru > 0xffe) {
pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
cxt1e1_max_mru, 0xffe);
cxt1e1_max_mru = 0xffe;
}
- if (cxt1e1_max_mtu > 0xffe)
- {
+ if (cxt1e1_max_mtu > 0xffe) {
pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
cxt1e1_max_mtu, 0xffe);
cxt1e1_max_mtu = 0xffe;
@@ -900,8 +846,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
volatile u_int32_t status;
ch = pi->chan[gchan];
- if (ch == 0 || ch->state != UP)
- {
+ if (ch == 0 || ch->state != UP) {
if (cxt1e1_log_level >= LOG_ERROR)
pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
pi->up->devname, gchan);
@@ -917,8 +862,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
spin_lock_irqsave (&ch->ch_txlock, flags);
#endif
#endif
- do
- {
+ do {
FLUSH_MEM_READ ();
md = ch->txd_irq_srv;
status = le32_to_cpu (md->status);
@@ -927,8 +871,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
* Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
* Transmit Buffer Descriptor during Transparent Mode.
*/
- if (status & MUSYCC_TX_OWNED)
- {
+ if (status & MUSYCC_TX_OWNED) {
int readCount, loopCount;
/***********************************************************/
@@ -941,8 +884,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
/***********************************************************/
readCount = 0;
- while (status & MUSYCC_TX_OWNED)
- {
+ while (status & MUSYCC_TX_OWNED) {
for (loopCount = 0; loopCount < 0x30; loopCount++)
OS_uwait_dummy (); /* use call to avoid optimization
* removal of dummy delay */
@@ -951,10 +893,8 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
if (readCount++ > 40)
break; /* don't wait any longer */
}
- if (status & MUSYCC_TX_OWNED)
- {
- if (cxt1e1_log_level >= LOG_MONITOR)
- {
+ if (status & MUSYCC_TX_OWNED) {
+ if (cxt1e1_log_level >= LOG_MONITOR) {
pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
pi->up->devname, pi->portnum, ch->channum,
md, status);
@@ -965,8 +905,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
musycc_dump_txbuffer_ring (ch, 0);
}
break; /* Not our mdesc, done */
- } else
- {
+ } else {
if (cxt1e1_log_level >= LOG_MONITOR)
pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
@@ -975,8 +914,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
ch->txd_irq_srv = md->snext;
md->data = 0;
- if (md->mem_token != 0)
- {
+ if (md->mem_token != 0) {
/* upcount channel */
atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
/* upcount card */
@@ -991,8 +929,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
{
int hdlcnum = (pi->portnum * 32 + gchan);
- if (hdlcnum >= 228)
- {
+ if (hdlcnum >= 228) {
if (nciProcess_TX_complete)
(*nciProcess_TX_complete) (hdlcnum,
getuserbychan (gchan));
@@ -1012,16 +949,14 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
++ch->txd_free;
FLUSH_MEM_WRITE ();
- if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE))
- {
+ if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE)) {
if (cxt1e1_log_level >= LOG_MONITOR)
pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
pi->up->devname, ch->p.chan_mode, status);
if ((status & EOMIRQ_ENABLE) == 0)
break;
}
- }
- while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
+ } while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
/*
* NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
* Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
@@ -1034,15 +969,13 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
* Smooth flow control hysterisis by maintaining task stoppage until half
* the available write buffers are available.
*/
- if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2)))
- {
+ if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2))) {
/*
* Then, only releave task stoppage if we actually have enough
* buffers to service the last requested packet. It may require MORE
* than half the available!
*/
- if (ch->txd_free >= ch->txd_required)
- {
+ if (ch->txd_free >= ch->txd_required) {
#ifdef RLD_TXFULL_DEBUG
if (cxt1e1_log_level >= LOG_MONITOR2)
@@ -1057,8 +990,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
}
}
#ifdef RLD_TXFULL_DEBUG
- else if (ch->tx_full)
- {
+ else if (ch->tx_full) {
if (cxt1e1_log_level >= LOG_MONITOR2)
pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
ch->channum,
@@ -1087,8 +1019,7 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
u_int32_t error;
ch = pi->chan[gchan];
- if (ch == 0 || ch->state != UP)
- {
+ if (ch == 0 || ch->state != UP) {
if (cxt1e1_log_level > LOG_ERROR)
pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
pi->up->devname, gchan);
@@ -1097,8 +1028,7 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
if (ch->mdr == 0)
return; /* can this happen ? */
- for (;;)
- {
+ for (;;) {
FLUSH_MEM_READ ();
md = &ch->mdr[ch->rxix_irq_srv];
status = le32_to_cpu (md->status);
@@ -1106,8 +1036,7 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
break; /* Not our mdesc, done */
m = md->mem_token;
error = (status >> 16) & 0xf;
- if (error == 0)
- {
+ if (error == 0) {
#ifdef CONFIG_SBE_WAN256T3_NCOMM
int hdlcnum = (pi->portnum * 32 + gchan);
@@ -1115,16 +1044,14 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
* if the packet number belongs to NCOMM, then send it to the TMS
* driver
*/
- if (hdlcnum >= 228)
- {
+ if (hdlcnum >= 228) {
if (nciProcess_RX_packet)
(*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
} else
#endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
{
- if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru)))
- {
+ if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru))) {
/* substitute the mbuf+cluster */
md->mem_token = m2;
md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
@@ -1134,26 +1061,18 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
ch->s.rx_packets++;
ch->s.rx_bytes += status & LENGTH_MASK;
} else
- {
ch->s.rx_dropped++;
- }
}
} else if (error == ERR_FCS)
- {
ch->s.rx_crc_errors++;
- } else if (error == ERR_ALIGN)
- {
+ else if (error == ERR_ALIGN)
ch->s.rx_missed_errors++;
- } else if (error == ERR_ABT)
- {
+ else if (error == ERR_ABT)
ch->s.rx_missed_errors++;
- } else if (error == ERR_LNG)
- {
+ else if (error == ERR_LNG)
ch->s.rx_length_errors++;
- } else if (error == ERR_SHT)
- {
+ else if (error == ERR_SHT)
ch->s.rx_length_errors++;
- }
FLUSH_MEM_WRITE ();
status = cxt1e1_max_mru;
if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
@@ -1180,16 +1099,13 @@ musycc_intr_th_handler (void *devp)
* might be shared, just return.
*/
if (ci->state == C_INIT)
- {
return IRQ_NONE;
- }
/*
* Marked as hardware available. Don't service interrupts, just clear the
* event.
*/
- if (ci->state == C_IDLE)
- {
+ if (ci->state == C_IDLE) {
status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
/* clear the interrupt but process nothing else */
@@ -1218,10 +1134,8 @@ musycc_intr_th_handler (void *devp)
/* incorrect ISD's are encountered. */
/*********************************************************/
- if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new))
- {
- if (cxt1e1_log_level >= LOG_MONITOR)
- {
+ if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new)) {
+ if (cxt1e1_log_level >= LOG_MONITOR) {
pr_info("%s: note - updated ISD from %08x to %08x\n",
ci->devname, status,
(status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
@@ -1243,9 +1157,8 @@ musycc_intr_th_handler (void *devp)
/**********************************************/
if (intCnt == INT_QUEUE_SIZE)
- {
currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
- } else
+ else
/************************************************/
/* Interrupt Write Location Issues */
/* ------------------------------- */
@@ -1263,10 +1176,8 @@ musycc_intr_th_handler (void *devp)
/************************************************/
if (intCnt)
- {
currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
- } else
- {
+ else {
/*
* NOTE: Servicing an interrupt whose ISD contains a count of ZERO
* can be indicative of a Shared Interrupt chain. Our driver can be
@@ -1289,9 +1200,7 @@ musycc_intr_th_handler (void *devp)
ci->intlog.this_status_new = currInt;
if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
- {
pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
- }
if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
ci->devname, &ci->reg->isd,
@@ -1336,8 +1245,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
* Hardware not available, potential interrupt hang. But since interrupt
* might be shared, just return.
*/
- if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT))
- {
+ if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT)) {
#if defined(SBE_ISR_IMMEDIATE)
return 0L;
#else
@@ -1345,8 +1253,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
#endif
}
#if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
- if (drvr_state != SBE_DRVR_AVAILABLE)
- {
+ if (drvr_state != SBE_DRVR_AVAILABLE) {
#if defined(SBE_ISR_TASKLET)
return;
#elif defined(SBE_ISR_IMMEDIATE)
@@ -1365,8 +1272,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
max_bh = max (bh, max_bh);
}
atomic_set (&ci->bh_pending, 0);/* if here, no longer pending */
- while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx))
- {
+ while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx)) {
intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
currInt = le32_to_cpu (ci->iqd_p[headx]);
@@ -1385,8 +1291,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
if ((currInt == badInt) || (currInt == badInt2))
ci->intlog.drvr_int_failure++;
- while ((currInt == badInt) || (currInt == badInt2))
- {
+ while ((currInt == badInt) || (currInt == badInt2)) {
for (loopCount = 0; loopCount < 0x30; loopCount++)
OS_uwait_dummy (); /* use call to avoid optimization removal
* of dummy delay */
@@ -1396,9 +1301,8 @@ musycc_intr_bh_tasklet (ci_t * ci)
break;
}
- if ((currInt == badInt) || (currInt == badInt2)) /* catch failure of Bug
+ if ((currInt == badInt) || (currInt == badInt2)) { /* catch failure of Bug
* Fix checking */
- {
if (cxt1e1_log_level >= LOG_WARN)
pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
ci->devname, &ci->iqd_p[headx], headx);
@@ -1414,12 +1318,9 @@ musycc_intr_bh_tasklet (ci_t * ci)
*/
if (currInt == badInt)
- {
ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
- } else
- {
+ else
ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
- }
ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
FLUSH_MEM_WRITE ();
FLUSH_MEM_READ ();
@@ -1434,8 +1335,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
FLUSH_MEM_WRITE ();
- if (cxt1e1_log_level >= LOG_DEBUG)
- {
+ if (cxt1e1_log_level >= LOG_DEBUG) {
if (err != 0)
pr_info(" %08x -> err: %2d,", currInt, err);
@@ -1445,11 +1345,9 @@ musycc_intr_bh_tasklet (ci_t * ci)
pi = &ci->port[group]; /* notice that here we assume 1-1 group -
* port mapping */
ch = pi->chan[gchan];
- switch (event)
- {
+ switch (event) {
case EVE_SACK: /* Service Request Acknowledge */
- if (cxt1e1_log_level >= LOG_DEBUG)
- {
+ if (cxt1e1_log_level >= LOG_DEBUG) {
volatile u_int32_t r;
r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
@@ -1463,12 +1361,9 @@ musycc_intr_bh_tasklet (ci_t * ci)
case EVE_EOM: /* End Of Message */
case EVE_EOB: /* End Of Buffer (Transparent mode) */
if (tx)
- {
musycc_bh_tx_eom (pi, gchan);
- } else
- {
+ else
musycc_bh_rx_eom (pi, gchan);
- }
#if 0
break;
#else
@@ -1480,9 +1375,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
#endif
case EVE_NONE:
if (err == ERR_SHT)
- {
ch->s.rx_length_errors++;
- }
break;
default:
if (cxt1e1_log_level >= LOG_WARN)
@@ -1498,8 +1391,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
* bit-level processing.
*/
- switch (err)
- {
+ switch (err) {
case ERR_ONR:
/*
* Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
@@ -1508,8 +1400,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
* Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
* requires Receive channel reactivation.
*/
- if (tx)
- {
+ if (tx) {
/*
* TX ONR Error only occurs when channel is configured for
@@ -1532,9 +1423,8 @@ musycc_intr_bh_tasklet (ci_t * ci)
pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
#ifdef RLD_DEBUG
- if (ch->p.chan_mode == 2) /* problem = ONR on HDLC
+ if (ch->p.chan_mode == 2) { /* problem = ONR on HDLC
* mode */
- {
pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
(u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
sd_queue_stopped (ch->user),
@@ -1544,8 +1434,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
#endif
}
}
- } else /* RX buffer overrun */
- {
+ } else { /* RX buffer overrun */
/*
* Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
* channel recovery for this RX ONR error IS required. It is
@@ -1556,8 +1445,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
ch->s.rx_over_errors++;
ch->ch_start_rx = CH_START_RX_ONR;
- if (cxt1e1_log_level >= LOG_WARN)
- {
+ if (cxt1e1_log_level >= LOG_WARN) {
pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
ci->devname, ch->channum, ch->p.chan_mode);
//musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
@@ -1566,8 +1454,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
musycc_chan_restart (ch);
break;
case ERR_BUF:
- if (tx)
- {
+ if (tx) {
ch->s.tx_fifo_errors++;
ch->ch_start_tx = CH_START_TX_BUF;
/*
@@ -1577,8 +1464,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
if (cxt1e1_log_level >= LOG_MONITOR)
pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
ci->devname, ch->channum, ch->p.chan_mode);
- } else /* RX buffer overrun */
- {
+ } else { /* RX buffer overrun */
ch->s.rx_over_errors++;
/*
* Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
@@ -1610,16 +1496,13 @@ musycc_intr_bh_tasklet (ci_t * ci)
/* Check for interrupt lost condition */
if ((currInt & INTRPT_ILOST_M) && (cxt1e1_log_level >= LOG_ERROR))
- {
pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
ci->devname);
- }
ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
FLUSH_MEM_WRITE ();
FLUSH_MEM_READ ();
} /* while */
- if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx))
- {
+ if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx)) {
int bh;
bh = atomic_read (&CI->bh_pending);
@@ -1690,16 +1573,12 @@ musycc_chan_down (ci_t * dummy, int channum)
pi->regram->rmp[gchan] = 0;
FLUSH_MEM_WRITE ();
for (i = 0; i < ch->txd_num; i++)
- {
if (ch->mdt[i].mem_token != 0)
OS_mem_token_free (ch->mdt[i].mem_token);
- }
for (i = 0; i < ch->rxd_num; i++)
- {
if (ch->mdr[i].mem_token != 0)
OS_mem_token_free (ch->mdr[i].mem_token);
- }
OS_kfree (ch->mdr);
ch->mdr = 0;
@@ -1787,16 +1666,14 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
m2 = mem_token;
txd_need_cnt = 0;
for (len = OS_mem_token_tlen (m2); len > 0;
- m2 = (void *) OS_mem_token_next (m2))
- {
+ m2 = (void *) OS_mem_token_next (m2)) {
if (!OS_mem_token_len (m2))
continue;
txd_need_cnt++;
len -= OS_mem_token_len (m2);
}
- if (txd_need_cnt == 0)
- {
+ if (txd_need_cnt == 0) {
if (cxt1e1_log_level >= LOG_MONITOR2)
pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
OS_mem_token_free (mem_token);
@@ -1805,14 +1682,11 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
/*************************************************/
/** Are there sufficient descriptors available? **/
/*************************************************/
- if (txd_need_cnt > ch->txd_num) /* never enough descriptors for this
- * large a buffer */
- {
+ if (txd_need_cnt > ch->txd_num) { /* never enough descriptors for this
+ * large a buffer */
if (cxt1e1_log_level >= LOG_DEBUG)
- {
pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
ch->txd_num, txd_need_cnt + 1);
- }
ch->s.tx_dropped++;
OS_mem_token_free (mem_token);
return 0;
@@ -1823,13 +1697,10 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
/************************************************************/
/** flow control the line if not enough descriptors remain **/
/************************************************************/
- if (txd_need_cnt > ch->txd_free)
- {
+ if (txd_need_cnt > ch->txd_free) {
if (cxt1e1_log_level >= LOG_MONITOR2)
- {
pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
channum, ch->txd_free, ch->txd_num, txd_need_cnt);
- }
ch->tx_full = 1;
ch->txd_required = txd_need_cnt;
sd_disable_xmit (ch->user);
@@ -1844,8 +1715,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
m2 = mem_token;
md = ch->txd_usr_add; /* get current available descriptor */
- for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2))
- {
+ for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2)) {
int u = OS_mem_token_len (m2);
if (!u)
@@ -1861,8 +1731,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
if (len) /* not last chunk */
u |= EOBIRQ_ENABLE;
- else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
- {
+ else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS) {
/*
* Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
* always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
@@ -1875,8 +1744,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
/* last chunk in hdlc mode */
u |= (ch->p.idlecode << IDLE_CODE);
- if (ch->p.pad_fill_count)
- {
+ if (ch->p.pad_fill_count) {
#if 0
/* NOOP NOTE: u_int8_t cannot be > 0xFF */
/* sanitize pad_fill_count for maximums allowed by hardware */
@@ -1919,9 +1787,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
* transmission.
*/
if (ch->ch_start_tx)
- {
musycc_chan_restart (ch);
- }
#ifdef SBE_WAN256T3_ENABLE
wan256t3_led (ci, LED_TX, LEDV_G);
#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (3 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 05/10] staging: cxt1e1: musycc.c: fixes brace placement Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-21 9:07 ` Dan Carpenter
2012-11-20 17:28 ` [PATCH 07/10] staging: cxt1e1: sbecrc.c: fixes indentation issues Johan Meiring
` (3 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit fixes several incorrect placements of parantheses, as
identified by the checkpatch.pl tool.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/musycc.c | 490 +++++++++++++++++++--------------------
1 file changed, 245 insertions(+), 245 deletions(-)
diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
index 42e1ca4..b2cc68a 100644
--- a/drivers/staging/cxt1e1/musycc.c
+++ b/drivers/staging/cxt1e1/musycc.c
@@ -60,21 +60,21 @@ extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
/*******************************************************************/
/* forward references */
-void c4_fifo_free (mpi_t *, int);
-void c4_wk_chan_restart (mch_t *);
-void musycc_bh_tx_eom (mpi_t *, int);
-int musycc_chan_up (ci_t *, int);
-status_t __init musycc_init (ci_t *);
-STATIC void __init musycc_init_port (mpi_t *);
-void musycc_intr_bh_tasklet (ci_t *);
-void musycc_serv_req (mpi_t *, u_int32_t);
-void musycc_update_timeslots (mpi_t *);
+void c4_fifo_free(mpi_t *, int);
+void c4_wk_chan_restart(mch_t *);
+void musycc_bh_tx_eom(mpi_t *, int);
+int musycc_chan_up(ci_t *, int);
+status_t __init musycc_init(ci_t *);
+STATIC void __init musycc_init_port(mpi_t *);
+void musycc_intr_bh_tasklet(ci_t *);
+void musycc_serv_req(mpi_t *, u_int32_t);
+void musycc_update_timeslots(mpi_t *);
/*******************************************************************/
#if 1
STATIC int
-musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
+musycc_dump_rxbuffer_ring(mch_t * ch, int lockit)
{
struct mdesc *m;
unsigned long flags = 0;
@@ -83,14 +83,14 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
int n;
if (lockit)
- spin_lock_irqsave (&ch->ch_rxlock, flags);
+ spin_lock_irqsave(&ch->ch_rxlock, flags);
if (ch->rxd_num == 0)
pr_info(" ZERO receive buffers allocated for this channel.");
else {
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
m = &ch->mdr[ch->rxix_irq_srv];
for (n = ch->rxd_num; n; n--) {
- status = le32_to_cpu (m->status);
+ status = le32_to_cpu(m->status);
{
pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
(m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
@@ -101,7 +101,7 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
status & EOBIRQ_ENABLE ? 'b' : '-',
status & EOMIRQ_ENABLE ? 'm' : '-',
status & LENGTH_MASK,
- le32_to_cpu (m->data), le32_to_cpu (m->next));
+ le32_to_cpu(m->data), le32_to_cpu(m->next));
#ifdef RLD_DUMP_BUFDATA
{
u_int32_t *dp;
@@ -114,7 +114,7 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
* data */
#endif
{
- dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
+ dp = (u_int32_t *) OS_phystov((void *) (le32_to_cpu(m->data)));
if (len >= 0x10)
pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
*dp, *(dp + 1), *(dp + 2), *(dp + 3));
@@ -133,14 +133,14 @@ musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
pr_info("\n");
if (lockit)
- spin_unlock_irqrestore (&ch->ch_rxlock, flags);
+ spin_unlock_irqrestore(&ch->ch_rxlock, flags);
return 0;
}
#endif
#if 1
STATIC int
-musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
+musycc_dump_txbuffer_ring(mch_t * ch, int lockit)
{
struct mdesc *m;
unsigned long flags = 0;
@@ -148,14 +148,14 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
int n;
if (lockit)
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave(&ch->ch_txlock, flags);
if (ch->txd_num == 0)
pr_info(" ZERO transmit buffers allocated for this channel.");
else {
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
m = ch->txd_irq_srv;
for (n = ch->txd_num; n; n--) {
- status = le32_to_cpu (m->status);
+ status = le32_to_cpu(m->status);
{
pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
(m == ch->txd_usr_add) ? 'F' : ' ',
@@ -167,14 +167,14 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
status & EOBIRQ_ENABLE ? 'b' : '-',
status & EOMIRQ_ENABLE ? 'm' : '-',
status & LENGTH_MASK,
- le32_to_cpu (m->data), le32_to_cpu (m->next));
+ le32_to_cpu(m->data), le32_to_cpu(m->next));
#ifdef RLD_DUMP_BUFDATA
{
u_int32_t *dp;
int len = status & LENGTH_MASK;
if (m->data) {
- dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
+ dp = (u_int32_t *) OS_phystov((void *) (le32_to_cpu(m->data)));
if (len >= 0x10)
pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
*dp, *(dp + 1), *(dp + 2), *(dp + 3));
@@ -193,7 +193,7 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
pr_info("\n");
if (lockit)
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
return 0;
}
#endif
@@ -205,7 +205,7 @@ musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
*/
status_t
-musycc_dump_ring (ci_t * ci, unsigned int chan)
+musycc_dump_ring(ci_t * ci, unsigned int chan)
{
mch_t *ch;
@@ -214,7 +214,7 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
{
int bh;
- bh = atomic_read (&ci->bh_pending);
+ bh = atomic_read(&ci->bh_pending);
pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
ci->intlog.drvr_intr_thcount,
@@ -224,7 +224,7 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
max_intcnt = 0; /* reset counter */
}
- if (!(ch = sd_find_chan (dummy, chan))) {
+ if (!(ch = sd_find_chan(dummy, chan))) {
pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
return ENOENT;
}
@@ -232,28 +232,28 @@ musycc_dump_ring (ci_t * ci, unsigned int chan)
ch->status, ch->p.status);
pr_info("--------------------------------\nTX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
chan, ch->txd_num,
- (u_int32_t) atomic_read (&ci->tx_pending), (u_int32_t) atomic_read (&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
+ (u_int32_t) atomic_read(&ci->tx_pending), (u_int32_t) atomic_read(&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
ch->user, ch->txd_irq_srv, ch->txd_usr_add,
- sd_queue_stopped (ch->user),
+ sd_queue_stopped(ch->user),
ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
- musycc_dump_txbuffer_ring (ch, 1);
+ musycc_dump_txbuffer_ring(ch, 1);
pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
chan, ch->rxd_num, ch->rxix_irq_srv,
&ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
- musycc_dump_rxbuffer_ring (ch, 1);
+ musycc_dump_rxbuffer_ring(ch, 1);
return SBE_DRVR_SUCCESS;
}
status_t
-musycc_dump_rings (ci_t * ci, unsigned int start_chan)
+musycc_dump_rings(ci_t * ci, unsigned int start_chan)
{
unsigned int chan;
for (chan = start_chan; chan < (start_chan + 5); chan++)
- musycc_dump_ring (ci, chan);
+ musycc_dump_ring(ci, chan);
return SBE_DRVR_SUCCESS;
}
@@ -264,7 +264,7 @@ musycc_dump_rings (ci_t * ci, unsigned int start_chan)
*/
void
-musycc_init_mdt (mpi_t * pi)
+musycc_init_mdt(mpi_t * pi)
{
u_int32_t *addr, cfg;
int i;
@@ -281,28 +281,28 @@ musycc_init_mdt (mpi_t * pi)
cfg = CFG_CH_FLAG_7E << IDLE_CODE;
for (i = 0; i < 32; addr++, i++)
- pci_write_32 (addr, cfg);
+ pci_write_32(addr, cfg);
}
/* Set TX thp to the next unprocessed md */
void
-musycc_update_tx_thp (mch_t * ch)
+musycc_update_tx_thp(mch_t * ch)
{
struct mdesc *md;
unsigned long flags;
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave(&ch->ch_txlock, flags);
while (1) {
md = ch->txd_irq_srv;
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
if (!md->data) {
/* No MDs with buffers to process */
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
return;
}
- if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED) {
+ if ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED) {
/* this is the MD to restart TX with */
break;
}
@@ -312,19 +312,19 @@ musycc_update_tx_thp (mch_t * ch)
* so... process this MD, it's owned by the host. (This might give
* as a new, updated txd_irq_srv.)
*/
- musycc_bh_tx_eom (ch->up, ch->gchan);
+ musycc_bh_tx_eom(ch->up, ch->gchan);
}
md = ch->txd_irq_srv;
- ch->up->regram->thp[ch->gchan] = cpu_to_le32 (OS_vtophys (md));
- FLUSH_MEM_WRITE ();
+ ch->up->regram->thp[ch->gchan] = cpu_to_le32(OS_vtophys(md));
+ FLUSH_MEM_WRITE();
if (ch->tx_full) {
ch->tx_full = 0;
ch->txd_required = 0;
- sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
+ sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
* channel */
}
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
#ifdef RLD_TRANS_DEBUG
pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n", ch->channum, md, md->status);
@@ -342,7 +342,7 @@ musycc_update_tx_thp (mch_t * ch)
*/
void
-musycc_wq_chan_restart (void *arg) /* channel private structure */
+musycc_wq_chan_restart(void *arg) /* channel private structure */
{
mch_t *ch;
mpi_t *pi;
@@ -376,19 +376,19 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
#ifdef RLD_TRANS_DEBUG
md = &ch->mdr[ch->rxix_irq_srv];
pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
- ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
+ ch->channum, ch->rxix_irq_srv, md, le32_to_cpu(md->status),
ch->s.rx_packets);
#elif defined(RLD_RXACT_DEBUG)
md = &ch->mdr[ch->rxix_irq_srv];
pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
- ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
+ ch->channum, ch->rxix_irq_srv, md, le32_to_cpu(md->status),
ch->s.rx_packets);
- musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
+ musycc_dump_rxbuffer_ring(ch, 1); /* RLD DEBUG */
#endif
}
}
#endif
- musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
+ musycc_serv_req(pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
}
/**********************************/
/** check for TX restart request **/
@@ -396,10 +396,10 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
if ((ch->ch_start_tx) && (ch->status & TX_ENABLED)) {
/* find next unprocessed message, then set TX thp to it */
- musycc_update_tx_thp (ch);
+ musycc_update_tx_thp(ch);
#if 0
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave(&ch->ch_txlock, flags);
#endif
md = ch->txd_irq_srv;
if (!md) {
@@ -407,29 +407,29 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
#endif
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
#endif
- } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)) {
+ } else if (md->data && ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED)) {
ch->ch_start_tx = 0;
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
+ spin_unlock_irqrestore(&ch->ch_txlock, flags); /* allow interrupts for service request */
#endif
#ifdef RLD_TRANS_DEBUG
pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
#endif
- musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
+ musycc_serv_req(pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
}
#ifdef RLD_RESTART_DEBUG
else {
/* retain request to start until retried and we have data to xmit */
pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
ch->channum, md,
- le32_to_cpu (md->status),
- le32_to_cpu (md->data), ch->ch_start_tx);
- musycc_dump_txbuffer_ring (ch, 0);
+ le32_to_cpu(md->status),
+ le32_to_cpu(md->data), ch->ch_start_tx);
+ musycc_dump_txbuffer_ring(ch, 0);
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
+ spin_unlock_irqrestore(&ch->ch_txlock, flags); /* allow interrupts for service request */
#endif
}
#endif
@@ -443,7 +443,7 @@ musycc_wq_chan_restart (void *arg) /* channel private structure */
*/
void
-musycc_chan_restart (mch_t * ch)
+musycc_chan_restart(mch_t * ch)
{
#ifdef RLD_RESTART_DEBUG
pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
@@ -454,14 +454,14 @@ musycc_chan_restart (mch_t * ch)
#ifdef RLD_RESTART_DEBUG
pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n", ch->channum, &ch->ch_work);
#endif
- c4_wk_chan_restart (ch); /* work queue mechanism fires off: Ref:
+ c4_wk_chan_restart(ch); /* work queue mechanism fires off: Ref:
* musycc_wq_chan_restart () */
}
void
-rld_put_led (mpi_t * pi, u_int32_t ledval)
+rld_put_led(mpi_t * pi, u_int32_t ledval)
{
static u_int32_t led = 0;
@@ -470,14 +470,14 @@ rld_put_led (mpi_t * pi, u_int32_t ledval)
else
led |= ledval;
- pci_write_32 ((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
+ pci_write_32((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
}
#define MUSYCC_SR_RETRY_CNT 9
void
-musycc_serv_req (mpi_t * pi, u_int32_t req)
+musycc_serv_req(mpi_t * pi, u_int32_t req)
{
volatile u_int32_t r;
int rcnt;
@@ -490,7 +490,7 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
* acknowledged."
*/
- SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
+ SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
* group */
if (pi->sr_last == req) {
@@ -512,24 +512,24 @@ musycc_serv_req (mpi_t * pi, u_int32_t req)
#ifdef RLD_TRANS_DEBUG
pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
#endif
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
- musycc_serv_req (pi, SR_NOOP);
- SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
+ SD_SEM_GIVE(&pi->sr_sem_busy); /* allow this next request */
+ musycc_serv_req(pi, SR_NOOP);
+ SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* relock & continue w/
* original req */
} else if (req == SR_NOOP) {
/* no need to issue back-to-back SR_NOOP commands at this time */
#ifdef RLD_TRANS_DEBUG
pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
#endif
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
+ SD_SEM_GIVE(&pi->sr_sem_busy); /* allow this next request */
return;
}
}
rcnt = 0;
pi->sr_last = req;
rewrite:
- pci_write_32 ((u_int32_t *) &pi->reg->srd, req);
- FLUSH_MEM_WRITE ();
+ pci_write_32((u_int32_t *) &pi->reg->srd, req);
+ FLUSH_MEM_WRITE();
/*
* Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
@@ -539,7 +539,7 @@ rewrite:
* the host follow any SCR write with another operation which reads from
* the same address."
*/
- r = pci_read_32 ((u_int32_t *) &pi->reg->srd); /* adhere to write
+ r = pci_read_32((u_int32_t *) &pi->reg->srd); /* adhere to write
* timing imposition */
@@ -548,14 +548,14 @@ rewrite:
pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
pi->up->devname, rcnt, req, pi->sr_last, r,
(pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
- OS_uwait_dummy (); /* this delay helps reduce reissue counts
+ OS_uwait_dummy(); /* this delay helps reduce reissue counts
* (reason not yet researched) */
goto rewrite;
}
if (rcnt > MUSYCC_SR_RETRY_CNT) {
pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
+ SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
return;
}
if (req == SR_CHIP_RESET) {
@@ -566,22 +566,22 @@ rewrite:
* unclear what CPU/BUS clock speeds might have been assumed when
* suggesting this 'lack of ACK' workaround. Thus the use of uwait.
*/
- OS_uwait (100000, "icard"); /* 100ms */
+ OS_uwait(100000, "icard"); /* 100ms */
} else {
- FLUSH_MEM_READ ();
- SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
+ FLUSH_MEM_READ();
+ SD_SEM_TAKE(&pi->sr_sem_wait, "sakack"); /* sleep until SACK
* interrupt occurs */
}
- SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
+ SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
}
#ifdef SBE_PMCC4_ENABLE
void
-musycc_update_timeslots (mpi_t * pi)
+musycc_update_timeslots(mpi_t * pi)
{
int i, ch;
- char e1mode = IS_FRAME_ANY_E1 (pi->p.port_mode);
+ char e1mode = IS_FRAME_ANY_E1(pi->p.port_mode);
for (i = 0; i < 32; i++) {
int usedby = 0, last = 0, ts, j, bits[8];
@@ -628,19 +628,19 @@ musycc_update_timeslots (mpi_t * pi)
pi->regram->rtsm[i] = ts;
pi->regram->ttsm[i] = ts;
}
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
- musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
- musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
- musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
- musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
+ musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
+ musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
+ musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
+ musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
}
#endif
#ifdef SBE_WAN256T3_ENABLE
void
-musycc_update_timeslots (mpi_t * pi)
+musycc_update_timeslots(mpi_t * pi)
{
mch_t *ch;
@@ -665,9 +665,9 @@ musycc_update_timeslots (mpi_t * pi)
pi->regram->rtsm[i] = ts;
pi->regram->ttsm[i] = ts;
}
- FLUSH_MEM_WRITE ();
- musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
- musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
+ FLUSH_MEM_WRITE();
+ musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
+ musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
}
#endif
@@ -677,7 +677,7 @@ musycc_update_timeslots (mpi_t * pi)
* into a hardware specific register value (IE. MUSYCC CCD Register).
*/
u_int32_t
-musycc_chan_proto (int proto)
+musycc_chan_proto(int proto)
{
int reg;
@@ -703,12 +703,12 @@ musycc_chan_proto (int proto)
#ifdef SBE_WAN256T3_ENABLE
STATIC void __init
-musycc_init_port (mpi_t * pi)
+musycc_init_port(mpi_t * pi)
{
- pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
+ pci_write_32((u_int32_t *) &pi->reg->gbp, OS_vtophys(pi->regram));
pi->regram->grcd =
- __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
+ __constant_cpu_to_le32(MUSYCC_GRCD_RX_ENABLE |
MUSYCC_GRCD_TX_ENABLE |
MUSYCC_GRCD_SF_ALIGN |
MUSYCC_GRCD_SUBCHAN_DISABLE |
@@ -718,31 +718,31 @@ musycc_init_port (mpi_t * pi)
(MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
pi->regram->pcd =
- __constant_cpu_to_le32 (MUSYCC_PCD_E1X4_MODE |
+ __constant_cpu_to_le32(MUSYCC_PCD_E1X4_MODE |
MUSYCC_PCD_TXDATA_RISING |
MUSYCC_PCD_TX_DRIVEN);
/* Message length descriptor */
- pi->regram->mld = __constant_cpu_to_le32 (cxt1e1_max_mru | (cxt1e1_max_mru << 16));
- FLUSH_MEM_WRITE ();
+ pi->regram->mld = __constant_cpu_to_le32(cxt1e1_max_mru | (cxt1e1_max_mru << 16));
+ FLUSH_MEM_WRITE();
- musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
- musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
+ musycc_serv_req(pi, SR_GROUP_INIT | SR_RX_DIRECTION);
+ musycc_serv_req(pi, SR_GROUP_INIT | SR_TX_DIRECTION);
- musycc_init_mdt (pi);
+ musycc_init_mdt(pi);
- musycc_update_timeslots (pi);
+ musycc_update_timeslots(pi);
}
#endif
status_t __init
-musycc_init (ci_t * ci)
+musycc_init(ci_t * ci)
{
char *regaddr; /* temp for address boundary calculations */
int i, gchan;
- OS_sem_init (&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
+ OS_sem_init(&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
/*
* Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
@@ -751,7 +751,7 @@ musycc_init (ci_t * ci)
#define INT_QUEUE_BOUNDARY 4
- regaddr = OS_kmalloc ((INT_QUEUE_SIZE + 1) * sizeof (u_int32_t));
+ regaddr = OS_kmalloc((INT_QUEUE_SIZE + 1) * sizeof(u_int32_t));
if (regaddr == 0)
return ENOMEM;
ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
@@ -760,7 +760,7 @@ musycc_init (ci_t * ci)
* closest boundary */
for (i = 0; i < INT_QUEUE_SIZE; i++)
- ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
+ ci->iqd_p[i] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
for (i = 0; i < ci->max_port; i++) {
mpi_t *pi = &ci->port[i];
@@ -772,11 +772,11 @@ musycc_init (ci_t * ci)
#define GROUP_BOUNDARY 0x800
- regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
+ regaddr = OS_kmalloc(sizeof(struct musycc_groupr) + GROUP_BOUNDARY);
if (regaddr == 0) {
for (gchan = 0; gchan < i; gchan++) {
pi = &ci->port[gchan];
- OS_kfree (pi->reg);
+ OS_kfree(pi->reg);
pi->reg = 0;
}
return ENOMEM;
@@ -789,26 +789,26 @@ musycc_init (ci_t * ci)
/* any board centric MUSYCC commands will use group ZERO as its "home" */
ci->regram = ci->port[0].regram;
- musycc_serv_req (&ci->port[0], SR_CHIP_RESET);
+ musycc_serv_req(&ci->port[0], SR_CHIP_RESET);
- pci_write_32 ((u_int32_t *) &ci->reg->gbp, OS_vtophys (ci->regram));
- pci_flush_write (ci);
+ pci_write_32((u_int32_t *) &ci->reg->gbp, OS_vtophys(ci->regram));
+ pci_flush_write(ci);
#ifdef CONFIG_SBE_PMCC4_NCOMM
- ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC);
+ ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC);
#else
/* standard driver POLLS for INTB via CPLD register */
- ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
+ ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
#endif
- ci->regram->__iqp = cpu_to_le32 (OS_vtophys (&ci->iqd_p[0]));
- ci->regram->__iql = __constant_cpu_to_le32 (INT_QUEUE_SIZE - 1);
- pci_write_32 ((u_int32_t *) &ci->reg->dacbp, 0);
- FLUSH_MEM_WRITE ();
+ ci->regram->__iqp = cpu_to_le32(OS_vtophys(&ci->iqd_p[0]));
+ ci->regram->__iql = __constant_cpu_to_le32(INT_QUEUE_SIZE - 1);
+ pci_write_32((u_int32_t *) &ci->reg->dacbp, 0);
+ FLUSH_MEM_WRITE();
ci->state = C_RUNNING; /* mark as full interrupt processing
* available */
- musycc_serv_req (&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
+ musycc_serv_req(&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
/* sanity check settable parameters */
@@ -824,7 +824,7 @@ musycc_init (ci_t * ci)
}
#ifdef SBE_WAN256T3_ENABLE
for (i = 0; i < MUSYCC_NPORTS; i++)
- musycc_init_port (&ci->port[i]);
+ musycc_init_port(&ci->port[i]);
#endif
return SBE_DRVR_SUCCESS; /* no error */
@@ -832,7 +832,7 @@ musycc_init (ci_t * ci)
void
-musycc_bh_tx_eom (mpi_t * pi, int gchan)
+musycc_bh_tx_eom(mpi_t * pi, int gchan)
{
mch_t *ch;
struct mdesc *md;
@@ -857,15 +857,15 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
#if 0
#ifdef SBE_ISR_INLINE
- spin_lock_irq (&ch->ch_txlock);
+ spin_lock_irq(&ch->ch_txlock);
#else
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave(&ch->ch_txlock, flags);
#endif
#endif
do {
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
md = ch->txd_irq_srv;
- status = le32_to_cpu (md->status);
+ status = le32_to_cpu(md->status);
/*
* Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
@@ -886,10 +886,10 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
readCount = 0;
while (status & MUSYCC_TX_OWNED) {
for (loopCount = 0; loopCount < 0x30; loopCount++)
- OS_uwait_dummy (); /* use call to avoid optimization
+ OS_uwait_dummy(); /* use call to avoid optimization
* removal of dummy delay */
- FLUSH_MEM_READ ();
- status = le32_to_cpu (md->status);
+ FLUSH_MEM_READ();
+ status = le32_to_cpu(md->status);
if (readCount++ > 40)
break; /* don't wait any longer */
}
@@ -900,9 +900,9 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
md, status);
pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
ch->user, ch->txd_irq_srv, ch->txd_usr_add,
- sd_queue_stopped (ch->user),
+ sd_queue_stopped(ch->user),
ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
- musycc_dump_txbuffer_ring (ch, 0);
+ musycc_dump_txbuffer_ring(ch, 0);
}
break; /* Not our mdesc, done */
} else {
@@ -916,12 +916,12 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
md->data = 0;
if (md->mem_token != 0) {
/* upcount channel */
- atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
+ atomic_sub(OS_mem_token_tlen(md->mem_token), &ch->tx_pending);
/* upcount card */
- atomic_sub (OS_mem_token_tlen (md->mem_token), &pi->up->tx_pending);
+ atomic_sub(OS_mem_token_tlen(md->mem_token), &pi->up->tx_pending);
#ifdef SBE_WAN256T3_ENABLE
- if (!atomic_read (&pi->up->tx_pending))
- wan256t3_led (pi->up, LED_TX, 0);
+ if (!atomic_read(&pi->up->tx_pending))
+ wan256t3_led(pi->up, LED_TX, 0);
#endif
#ifdef CONFIG_SBE_WAN256T3_NCOMM
@@ -932,12 +932,12 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
if (hdlcnum >= 228) {
if (nciProcess_TX_complete)
(*nciProcess_TX_complete) (hdlcnum,
- getuserbychan (gchan));
+ getuserbychan(gchan));
}
}
#endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
- OS_mem_token_free_irq (md->mem_token);
+ OS_mem_token_free_irq(md->mem_token);
md->mem_token = 0;
}
md->status = 0;
@@ -947,7 +947,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
ch->tx_full, ch->txd_free, ch->txd_free + 1);
#endif
++ch->txd_free;
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE)) {
if (cxt1e1_log_level >= LOG_MONITOR)
@@ -964,7 +964,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
* buffer.
*/
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
/*
* Smooth flow control hysterisis by maintaining task stoppage until half
* the available write buffers are available.
@@ -985,7 +985,7 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
#endif
ch->tx_full = 0;
ch->txd_required = 0;
- sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
+ sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
* channel */
}
}
@@ -998,19 +998,19 @@ musycc_bh_tx_eom (mpi_t * pi, int gchan)
}
#endif
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
#if 0
#ifdef SBE_ISR_INLINE
- spin_unlock_irq (&ch->ch_txlock);
+ spin_unlock_irq(&ch->ch_txlock);
#else
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
#endif
#endif
}
STATIC void
-musycc_bh_rx_eom (mpi_t * pi, int gchan)
+musycc_bh_rx_eom(mpi_t * pi, int gchan)
{
mch_t *ch;
void *m, *m2;
@@ -1029,9 +1029,9 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
return; /* can this happen ? */
for (;;) {
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
md = &ch->mdr[ch->rxix_irq_srv];
- status = le32_to_cpu (md->status);
+ status = le32_to_cpu(md->status);
if (!(status & HOST_RX_OWNED))
break; /* Not our mdesc, done */
m = md->mem_token;
@@ -1051,13 +1051,13 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
#endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
{
- if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru))) {
+ if ((m2 = OS_mem_token_alloc(cxt1e1_max_mru))) {
/* substitute the mbuf+cluster */
md->mem_token = m2;
- md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
+ md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
/* pass the received mbuf upward */
- sd_recv_consume (m, status & LENGTH_MASK, ch->user);
+ sd_recv_consume(m, status & LENGTH_MASK, ch->user);
ch->s.rx_packets++;
ch->s.rx_bytes += status & LENGTH_MASK;
} else
@@ -1073,22 +1073,22 @@ musycc_bh_rx_eom (mpi_t * pi, int gchan)
ch->s.rx_length_errors++;
else if (error == ERR_SHT)
ch->s.rx_length_errors++;
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
status = cxt1e1_max_mru;
if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
status |= EOBIRQ_ENABLE;
- md->status = cpu_to_le32 (status);
+ md->status = cpu_to_le32(status);
/* Check next mdesc in the ring */
if (++ch->rxix_irq_srv >= ch->rxd_num)
ch->rxix_irq_srv = 0;
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
}
}
irqreturn_t
-musycc_intr_th_handler (void *devp)
+musycc_intr_th_handler(void *devp)
{
ci_t *ci = (ci_t *) devp;
volatile u_int32_t status, currInt = 0;
@@ -1106,18 +1106,18 @@ musycc_intr_th_handler (void *devp)
*/
if (ci->state == C_IDLE) {
- status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
+ status = pci_read_32((u_int32_t *) &ci->reg->isd);
/* clear the interrupt but process nothing else */
- pci_write_32 ((u_int32_t *) &ci->reg->isd, status);
+ pci_write_32((u_int32_t *) &ci->reg->isd, status);
return IRQ_HANDLED;
}
- FLUSH_PCI_READ ();
- FLUSH_MEM_READ ();
+ FLUSH_PCI_READ();
+ FLUSH_MEM_READ();
- status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
- nextInt = INTRPTS_NEXTINT (status);
- intCnt = INTRPTS_INTCNT (status);
+ status = pci_read_32((u_int32_t *) &ci->reg->isd);
+ nextInt = INTRPTS_NEXTINT(status);
+ intCnt = INTRPTS_INTCNT(status);
ci->intlog.drvr_intr_thcount++;
/*********************************************************/
@@ -1134,7 +1134,7 @@ musycc_intr_th_handler (void *devp)
/* incorrect ISD's are encountered. */
/*********************************************************/
- if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new)) {
+ if (nextInt != INTRPTS_NEXTINT(ci->intlog.this_status_new)) {
if (cxt1e1_log_level >= LOG_MONITOR) {
pr_info("%s: note - updated ISD from %08x to %08x\n",
ci->devname, status,
@@ -1147,7 +1147,7 @@ musycc_intr_th_handler (void *devp)
* INTFULL bit is correctly reported or not.
*/
status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
- nextInt = INTRPTS_NEXTINT (status);
+ nextInt = INTRPTS_NEXTINT(status);
}
/**********************************************/
/* Cn847x Bug Fix */
@@ -1206,19 +1206,19 @@ musycc_intr_th_handler (void *devp)
ci->devname, &ci->reg->isd,
status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
#if defined(SBE_ISR_TASKLET)
- pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
- atomic_inc (&ci->bh_pending);
- tasklet_schedule (&ci->ci_musycc_isr_tasklet);
+ pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
+ atomic_inc(&ci->bh_pending);
+ tasklet_schedule(&ci->ci_musycc_isr_tasklet);
#elif defined(SBE_ISR_IMMEDIATE)
- pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
- atomic_inc (&ci->bh_pending);
- queue_task (&ci->ci_musycc_isr_tq, &tq_immediate);
- mark_bh (IMMEDIATE_BH);
+ pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
+ atomic_inc(&ci->bh_pending);
+ queue_task(&ci->ci_musycc_isr_tq, &tq_immediate);
+ mark_bh(IMMEDIATE_BH);
#elif defined(SBE_ISR_INLINE)
- (void) musycc_intr_bh_tasklet (ci);
- pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
+ (void) musycc_intr_bh_tasklet(ci);
+ pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
#endif
return IRQ_HANDLED;
}
@@ -1229,7 +1229,7 @@ unsigned long
#else
void
#endif
-musycc_intr_bh_tasklet (ci_t * ci)
+musycc_intr_bh_tasklet(ci_t * ci)
{
mpi_t *pi;
mch_t *ch;
@@ -1265,18 +1265,18 @@ musycc_intr_bh_tasklet (ci_t * ci)
#endif
ci->intlog.drvr_intr_bhcount++;
- FLUSH_MEM_READ ();
+ FLUSH_MEM_READ();
{
- unsigned int bh = atomic_read (&ci->bh_pending);
+ unsigned int bh = atomic_read(&ci->bh_pending);
- max_bh = max (bh, max_bh);
+ max_bh = max(bh, max_bh);
}
- atomic_set (&ci->bh_pending, 0);/* if here, no longer pending */
+ atomic_set(&ci->bh_pending, 0);/* if here, no longer pending */
while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx)) {
intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
- currInt = le32_to_cpu (ci->iqd_p[headx]);
+ currInt = le32_to_cpu(ci->iqd_p[headx]);
- max_intcnt = max (intCnt, max_intcnt); /* RLD DEBUG */
+ max_intcnt = max(intCnt, max_intcnt); /* RLD DEBUG */
/**************************************************/
/* HW Bug Fix */
@@ -1293,10 +1293,10 @@ musycc_intr_bh_tasklet (ci_t * ci)
while ((currInt == badInt) || (currInt == badInt2)) {
for (loopCount = 0; loopCount < 0x30; loopCount++)
- OS_uwait_dummy (); /* use call to avoid optimization removal
+ OS_uwait_dummy(); /* use call to avoid optimization removal
* of dummy delay */
- FLUSH_MEM_READ ();
- currInt = le32_to_cpu (ci->iqd_p[headx]);
+ FLUSH_MEM_READ();
+ currInt = le32_to_cpu(ci->iqd_p[headx]);
if (readCount++ > 20)
break;
}
@@ -1318,22 +1318,22 @@ musycc_intr_bh_tasklet (ci_t * ci)
*/
if (currInt == badInt)
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
+ ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY2);
else
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
+ ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
- FLUSH_MEM_WRITE ();
- FLUSH_MEM_READ ();
+ FLUSH_MEM_WRITE();
+ FLUSH_MEM_READ();
continue;
}
- group = INTRPT_GRP (currInt);
- gchan = INTRPT_CH (currInt);
- event = INTRPT_EVENT (currInt);
- err = INTRPT_ERROR (currInt);
+ group = INTRPT_GRP(currInt);
+ gchan = INTRPT_CH(currInt);
+ event = INTRPT_EVENT(currInt);
+ err = INTRPT_ERROR(currInt);
tx = currInt & INTRPT_DIR_M;
- ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
- FLUSH_MEM_WRITE ();
+ ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
+ FLUSH_MEM_WRITE();
if (cxt1e1_log_level >= LOG_DEBUG) {
if (err != 0)
@@ -1350,10 +1350,10 @@ musycc_intr_bh_tasklet (ci_t * ci)
if (cxt1e1_log_level >= LOG_DEBUG) {
volatile u_int32_t r;
- r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
+ r = pci_read_32((u_int32_t *) &pi->reg->srd);
pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
}
- SD_SEM_GIVE (&pi->sr_sem_wait); /* wake up waiting process */
+ SD_SEM_GIVE(&pi->sr_sem_wait); /* wake up waiting process */
break;
case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
@@ -1361,9 +1361,9 @@ musycc_intr_bh_tasklet (ci_t * ci)
case EVE_EOM: /* End Of Message */
case EVE_EOB: /* End Of Buffer (Transparent mode) */
if (tx)
- musycc_bh_tx_eom (pi, gchan);
+ musycc_bh_tx_eom(pi, gchan);
else
- musycc_bh_rx_eom (pi, gchan);
+ musycc_bh_rx_eom(pi, gchan);
#if 0
break;
#else
@@ -1421,15 +1421,15 @@ musycc_intr_bh_tasklet (ci_t * ci)
#endif
{
pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
- ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
+ ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped(ch->user), ch->txd_free);
#ifdef RLD_DEBUG
if (ch->p.chan_mode == 2) { /* problem = ONR on HDLC
* mode */
pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
(u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
- sd_queue_stopped (ch->user),
+ sd_queue_stopped(ch->user),
ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
- musycc_dump_txbuffer_ring (ch, 0);
+ musycc_dump_txbuffer_ring(ch, 0);
}
#endif
}
@@ -1451,7 +1451,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
//musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
}
}
- musycc_chan_restart (ch);
+ musycc_chan_restart(ch);
break;
case ERR_BUF:
if (tx) {
@@ -1488,7 +1488,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
}
if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
- musycc_chan_restart (ch);
+ musycc_chan_restart(ch);
break;
default:
break;
@@ -1499,13 +1499,13 @@ musycc_intr_bh_tasklet (ci_t * ci)
pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
ci->devname);
ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
- FLUSH_MEM_WRITE ();
- FLUSH_MEM_READ ();
+ FLUSH_MEM_WRITE();
+ FLUSH_MEM_READ();
} /* while */
if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx)) {
int bh;
- bh = atomic_read (&CI->bh_pending);
+ bh = atomic_read(&CI->bh_pending);
pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
ci->iqp_headx, ci->iqp_tailx, bh);
}
@@ -1517,7 +1517,7 @@ musycc_intr_bh_tasklet (ci_t * ci)
#if 0
int __init
-musycc_new_chan (ci_t * ci, int channum, void *user)
+musycc_new_chan(ci_t * ci, int channum, void *user)
{
mch_t *ch;
@@ -1536,8 +1536,8 @@ musycc_new_chan (ci_t * ci, int channum, void *user)
ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
ch->p.idlecode = CFG_CH_FLAG_7E;
ch->p.pad_fill_count = 2;
- spin_lock_init (&ch->ch_rxlock);
- spin_lock_init (&ch->ch_txlock);
+ spin_lock_init(&ch->ch_rxlock);
+ spin_lock_init(&ch->ch_txlock);
return 0;
}
@@ -1546,21 +1546,21 @@ musycc_new_chan (ci_t * ci, int channum, void *user)
#ifdef SBE_PMCC4_ENABLE
status_t
-musycc_chan_down (ci_t * dummy, int channum)
+musycc_chan_down(ci_t * dummy, int channum)
{
mpi_t *pi;
mch_t *ch;
int i, gchan;
- if (!(ch = sd_find_chan (dummy, channum)))
+ if (!(ch = sd_find_chan(dummy, channum)))
return EINVAL;
pi = ch->up;
gchan = ch->gchan;
/* Deactivate the channel */
- musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
+ musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
ch->ch_start_rx = 0;
- musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
+ musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
ch->ch_start_tx = 0;
if (ch->state == DOWN)
@@ -1571,24 +1571,24 @@ musycc_chan_down (ci_t * dummy, int channum)
pi->regram->tmp[gchan] = 0;
pi->regram->rhp[gchan] = 0;
pi->regram->rmp[gchan] = 0;
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
for (i = 0; i < ch->txd_num; i++)
if (ch->mdt[i].mem_token != 0)
- OS_mem_token_free (ch->mdt[i].mem_token);
+ OS_mem_token_free(ch->mdt[i].mem_token);
for (i = 0; i < ch->rxd_num; i++)
if (ch->mdr[i].mem_token != 0)
- OS_mem_token_free (ch->mdr[i].mem_token);
+ OS_mem_token_free(ch->mdr[i].mem_token);
- OS_kfree (ch->mdr);
+ OS_kfree(ch->mdr);
ch->mdr = 0;
ch->rxd_num = 0;
- OS_kfree (ch->mdt);
+ OS_kfree(ch->mdt);
ch->mdt = 0;
ch->txd_num = 0;
- musycc_update_timeslots (pi);
- c4_fifo_free (pi, ch->gchan);
+ musycc_update_timeslots(pi);
+ c4_fifo_free(pi, ch->gchan);
pi->openchans--;
return 0;
@@ -1597,38 +1597,38 @@ musycc_chan_down (ci_t * dummy, int channum)
int
-musycc_del_chan (ci_t * ci, int channum)
+musycc_del_chan(ci_t * ci, int channum)
{
mch_t *ch;
if ((channum < 0) || (channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS))) /* sanity chk param */
return ECHRNG;
- if (!(ch = sd_find_chan (ci, channum)))
+ if (!(ch = sd_find_chan(ci, channum)))
return ENOENT;
if (ch->state == UP)
- musycc_chan_down (ci, channum);
+ musycc_chan_down(ci, channum);
ch->state = UNASSIGNED;
return 0;
}
int
-musycc_del_chan_stats (ci_t * ci, int channum)
+musycc_del_chan_stats(ci_t * ci, int channum)
{
mch_t *ch;
if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
return ECHRNG;
- if (!(ch = sd_find_chan (ci, channum)))
+ if (!(ch = sd_find_chan(ci, channum)))
return ENOENT;
- memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
+ memset(&ch->s, 0, sizeof(struct sbecom_chan_stats));
return 0;
}
int
-musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
+musycc_start_xmit(ci_t * ci, int channum, void *mem_token)
{
mch_t *ch;
struct mdesc *md;
@@ -1639,7 +1639,7 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
int txd_need_cnt;
u_int32_t len;
- if (!(ch = sd_find_chan (ci, channum)))
+ if (!(ch = sd_find_chan(ci, channum)))
return -ENOENT;
if (ci->state != C_RUNNING) /* full interrupt processing available */
@@ -1658,25 +1658,25 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
{
pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
channum, ch->state, ch->ch_start_tx, ch->tx_full,
- ch->txd_free, ch->txd_required, sd_queue_stopped (ch->user));
+ ch->txd_free, ch->txd_required, sd_queue_stopped(ch->user));
}
/***********************************************/
/** Determine total amount of data to be sent **/
/***********************************************/
m2 = mem_token;
txd_need_cnt = 0;
- for (len = OS_mem_token_tlen (m2); len > 0;
- m2 = (void *) OS_mem_token_next (m2)) {
- if (!OS_mem_token_len (m2))
+ for (len = OS_mem_token_tlen(m2); len > 0;
+ m2 = (void *) OS_mem_token_next(m2)) {
+ if (!OS_mem_token_len(m2))
continue;
txd_need_cnt++;
- len -= OS_mem_token_len (m2);
+ len -= OS_mem_token_len(m2);
}
if (txd_need_cnt == 0) {
if (cxt1e1_log_level >= LOG_MONITOR2)
pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
- OS_mem_token_free (mem_token);
+ OS_mem_token_free(mem_token);
return 0; /* no data to send */
}
/*************************************************/
@@ -1688,11 +1688,11 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
ch->txd_num, txd_need_cnt + 1);
ch->s.tx_dropped++;
- OS_mem_token_free (mem_token);
+ OS_mem_token_free(mem_token);
return 0;
}
#if 0
- spin_lock_irqsave (&ch->ch_txlock, flags);
+ spin_lock_irqsave(&ch->ch_txlock, flags);
#endif
/************************************************************/
/** flow control the line if not enough descriptors remain **/
@@ -1703,9 +1703,9 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
channum, ch->txd_free, ch->txd_num, txd_need_cnt);
ch->tx_full = 1;
ch->txd_required = txd_need_cnt;
- sd_disable_xmit (ch->user);
+ sd_disable_xmit(ch->user);
#if 0
- spin_unlock_irqrestore (&ch->ch_txlock, flags);
+ spin_unlock_irqrestore(&ch->ch_txlock, flags);
#endif
return -EBUSY; /* tell user to try again later */
}
@@ -1715,8 +1715,8 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
m2 = mem_token;
md = ch->txd_usr_add; /* get current available descriptor */
- for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2)) {
- int u = OS_mem_token_len (m2);
+ for (len = OS_mem_token_tlen(m2); len > 0; m2 = OS_mem_token_next(m2)) {
+ int u = OS_mem_token_len(m2);
if (!u)
continue;
@@ -1760,26 +1760,26 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
* segments have been
* transmitted. */
- md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
- FLUSH_MEM_WRITE ();
- md->status = cpu_to_le32 (u);
+ md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
+ FLUSH_MEM_WRITE();
+ md->status = cpu_to_le32(u);
--ch->txd_free;
md = md->snext;
}
- FLUSH_MEM_WRITE ();
+ FLUSH_MEM_WRITE();
/*
* Now transfer ownership of first chunk from HOST to MUSYCC in order to
* fire-off this XMIT.
*/
- ch->txd_usr_add->status |= __constant_cpu_to_le32 (MUSYCC_TX_OWNED);
- FLUSH_MEM_WRITE ();
+ ch->txd_usr_add->status |= __constant_cpu_to_le32(MUSYCC_TX_OWNED);
+ FLUSH_MEM_WRITE();
ch->txd_usr_add = md;
- len = OS_mem_token_tlen (mem_token);
- atomic_add (len, &ch->tx_pending);
- atomic_add (len, &ci->tx_pending);
+ len = OS_mem_token_tlen(mem_token);
+ atomic_add(len, &ch->tx_pending);
+ atomic_add(len, &ci->tx_pending);
ch->s.tx_packets++;
ch->s.tx_bytes += len;
/*
@@ -1787,9 +1787,9 @@ musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
* transmission.
*/
if (ch->ch_start_tx)
- musycc_chan_restart (ch);
+ musycc_chan_restart(ch);
#ifdef SBE_WAN256T3_ENABLE
- wan256t3_led (ci, LED_TX, LEDV_G);
+ wan256t3_led(ci, LED_TX, LEDV_G);
#endif
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 07/10] staging: cxt1e1: sbecrc.c: fixes indentation issues
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (4 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 08/10] staging: cxt1e1: sbecrc.c: fixes brace placement Johan Meiring
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit converts several instances of space-based indentation
to use tabs instead.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/sbecrc.c | 106 +++++++++++++++++++--------------------
1 file changed, 53 insertions(+), 53 deletions(-)
diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
index 3f3cd60..b4fabe1 100644
--- a/drivers/staging/cxt1e1/sbecrc.c
+++ b/drivers/staging/cxt1e1/sbecrc.c
@@ -46,23 +46,23 @@ static u_int32_t CRCTable[CRC_TABLE_ENTRIES];
static void
genCrcTable (u_int32_t *CRCTable)
{
- int ii, jj;
- u_int32_t crc;
-
- for (ii = 0; ii < CRC_TABLE_ENTRIES; ii++)
- {
- crc = ii;
- for (jj = 8; jj > 0; jj--)
- {
- if (crc & 1)
- crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
- else
- crc >>= 1;
- }
- CRCTable[ii] = crc;
- }
-
- crcTableInit++;
+ int ii, jj;
+ u_int32_t crc;
+
+ for (ii = 0; ii < CRC_TABLE_ENTRIES; ii++)
+ {
+ crc = ii;
+ for (jj = 8; jj > 0; jj--)
+ {
+ if (crc & 1)
+ crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
+ else
+ crc >>= 1;
+ }
+ CRCTable[ii] = crc;
+ }
+
+ crcTableInit++;
}
@@ -86,51 +86,51 @@ genCrcTable (u_int32_t *CRCTable)
void
sbeCrc (u_int8_t *buffer, /* data buffer to crc */
- u_int32_t count, /* length of block in bytes */
- u_int32_t initialCrc, /* starting CRC */
- u_int32_t *result)
+ u_int32_t count, /* length of block in bytes */
+ u_int32_t initialCrc, /* starting CRC */
+ u_int32_t *result)
{
- u_int32_t *tbl = 0;
- u_int32_t temp1, temp2, crc;
-
- /*
- * if table not yet created, do so. Don't care about "extra" time
- * checking this every time sbeCrc() is called, since CRC calculations are
- * already time consuming
- */
- if (!crcTableInit)
- {
+ u_int32_t *tbl = 0;
+ u_int32_t temp1, temp2, crc;
+
+ /*
+ * if table not yet created, do so. Don't care about "extra" time
+ * checking this every time sbeCrc() is called, since CRC calculations
+ * are already time consuming
+ */
+ if (!crcTableInit)
+ {
#ifdef STATIC_CRC_TABLE
- tbl = &CRCTable;
- genCrcTable (tbl);
+ tbl = &CRCTable;
+ genCrcTable (tbl);
#else
- tbl = (u_int32_t *) OS_kmalloc (CRC_TABLE_ENTRIES * sizeof (u_int32_t));
- if (tbl == 0)
- {
- *result = 0; /* dummy up return value due to malloc
- * failure */
- return;
- }
- genCrcTable (tbl);
+ tbl = (u_int32_t *) OS_kmalloc (CRC_TABLE_ENTRIES * sizeof (u_int32_t));
+ if (tbl == 0)
+ {
+ *result = 0; /* dummy up return value due to malloc
+ * failure */
+ return;
+ }
+ genCrcTable (tbl);
#endif
- }
- /* inverting bits makes ZMODEM & PKZIP compatible */
- crc = initialCrc ^ 0xFFFFFFFFL;
+ }
+ /* inverting bits makes ZMODEM & PKZIP compatible */
+ crc = initialCrc ^ 0xFFFFFFFFL;
- while (count-- != 0)
- {
- temp1 = (crc >> 8) & 0x00FFFFFFL;
- temp2 = tbl[((int) crc ^ *buffer++) & 0xff];
- crc = temp1 ^ temp2;
- }
+ while (count-- != 0)
+ {
+ temp1 = (crc >> 8) & 0x00FFFFFFL;
+ temp2 = tbl[((int) crc ^ *buffer++) & 0xff];
+ crc = temp1 ^ temp2;
+ }
- crc ^= 0xFFFFFFFFL;
+ crc ^= 0xFFFFFFFFL;
- *result = crc;
+ *result = crc;
#ifndef STATIC_CRC_TABLE
- crcTableInit = 0;
- OS_kfree (tbl);
+ crcTableInit = 0;
+ OS_kfree (tbl);
#endif
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 08/10] staging: cxt1e1: sbecrc.c: fixes brace placement
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (5 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 07/10] staging: cxt1e1: sbecrc.c: fixes indentation issues Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 09/10] staging: cxt1e1: sbecrc.c: fixes coding style issue Johan Meiring
2012-11-20 17:28 ` [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue Johan Meiring
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit sorts out the incorrect placement of braces in the file.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/sbecrc.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
index b4fabe1..f95728e 100644
--- a/drivers/staging/cxt1e1/sbecrc.c
+++ b/drivers/staging/cxt1e1/sbecrc.c
@@ -49,11 +49,9 @@ genCrcTable (u_int32_t *CRCTable)
int ii, jj;
u_int32_t crc;
- for (ii = 0; ii < CRC_TABLE_ENTRIES; ii++)
- {
+ for (ii = 0; ii < CRC_TABLE_ENTRIES; ii++) {
crc = ii;
- for (jj = 8; jj > 0; jj--)
- {
+ for (jj = 8; jj > 0; jj--) {
if (crc & 1)
crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
else
@@ -98,15 +96,13 @@ sbeCrc (u_int8_t *buffer, /* data buffer to crc */
* checking this every time sbeCrc() is called, since CRC calculations
* are already time consuming
*/
- if (!crcTableInit)
- {
+ if (!crcTableInit) {
#ifdef STATIC_CRC_TABLE
tbl = &CRCTable;
genCrcTable (tbl);
#else
tbl = (u_int32_t *) OS_kmalloc (CRC_TABLE_ENTRIES * sizeof (u_int32_t));
- if (tbl == 0)
- {
+ if (tbl == 0) {
*result = 0; /* dummy up return value due to malloc
* failure */
return;
@@ -117,8 +113,7 @@ sbeCrc (u_int8_t *buffer, /* data buffer to crc */
/* inverting bits makes ZMODEM & PKZIP compatible */
crc = initialCrc ^ 0xFFFFFFFFL;
- while (count-- != 0)
- {
+ while (count-- != 0) {
temp1 = (crc >> 8) & 0x00FFFFFFL;
temp2 = tbl[((int) crc ^ *buffer++) & 0xff];
crc = temp1 ^ temp2;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 09/10] staging: cxt1e1: sbecrc.c: fixes coding style issue
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (6 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 08/10] staging: cxt1e1: sbecrc.c: fixes brace placement Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-20 17:28 ` [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue Johan Meiring
8 siblings, 0 replies; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit sorts out a coding style issue related to spaces between
parentheses and function names.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/sbecrc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
index f95728e..87512a5 100644
--- a/drivers/staging/cxt1e1/sbecrc.c
+++ b/drivers/staging/cxt1e1/sbecrc.c
@@ -44,7 +44,7 @@ static u_int32_t CRCTable[CRC_TABLE_ENTRIES];
***************************************************************************/
static void
-genCrcTable (u_int32_t *CRCTable)
+genCrcTable(u_int32_t *CRCTable)
{
int ii, jj;
u_int32_t crc;
@@ -83,7 +83,7 @@ genCrcTable (u_int32_t *CRCTable)
*/
void
-sbeCrc (u_int8_t *buffer, /* data buffer to crc */
+sbeCrc(u_int8_t *buffer, /* data buffer to crc */
u_int32_t count, /* length of block in bytes */
u_int32_t initialCrc, /* starting CRC */
u_int32_t *result)
@@ -99,15 +99,15 @@ sbeCrc (u_int8_t *buffer, /* data buffer to crc */
if (!crcTableInit) {
#ifdef STATIC_CRC_TABLE
tbl = &CRCTable;
- genCrcTable (tbl);
+ genCrcTable(tbl);
#else
- tbl = (u_int32_t *) OS_kmalloc (CRC_TABLE_ENTRIES * sizeof (u_int32_t));
+ tbl = (u_int32_t *) OS_kmalloc(CRC_TABLE_ENTRIES * sizeof(u_int32_t));
if (tbl == 0) {
*result = 0; /* dummy up return value due to malloc
* failure */
return;
}
- genCrcTable (tbl);
+ genCrcTable(tbl);
#endif
}
/* inverting bits makes ZMODEM & PKZIP compatible */
@@ -125,7 +125,7 @@ sbeCrc (u_int8_t *buffer, /* data buffer to crc */
#ifndef STATIC_CRC_TABLE
crcTableInit = 0;
- OS_kfree (tbl);
+ OS_kfree(tbl);
#endif
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue
2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
` (7 preceding siblings ...)
2012-11-20 17:28 ` [PATCH 09/10] staging: cxt1e1: sbecrc.c: fixes coding style issue Johan Meiring
@ 2012-11-20 17:28 ` Johan Meiring
2012-11-21 9:04 ` Dan Carpenter
8 siblings, 1 reply; 12+ messages in thread
From: Johan Meiring @ 2012-11-20 17:28 UTC (permalink / raw)
To: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel; +Cc: Johan Meiring
This commit sorts out a single case where a line was longer than
80 characters.
Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
---
drivers/staging/cxt1e1/sbecrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
index 87512a5..59dd7e2 100644
--- a/drivers/staging/cxt1e1/sbecrc.c
+++ b/drivers/staging/cxt1e1/sbecrc.c
@@ -101,7 +101,8 @@ sbeCrc(u_int8_t *buffer, /* data buffer to crc */
tbl = &CRCTable;
genCrcTable(tbl);
#else
- tbl = (u_int32_t *) OS_kmalloc(CRC_TABLE_ENTRIES * sizeof(u_int32_t));
+ tbl = (u_int32_t *) OS_kmalloc(CRC_TABLE_ENTRIES
+ * sizeof(u_int32_t));
if (tbl == 0) {
*result = 0; /* dummy up return value due to malloc
* failure */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue
2012-11-20 17:28 ` [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue Johan Meiring
@ 2012-11-21 9:04 ` Dan Carpenter
0 siblings, 0 replies; 12+ messages in thread
From: Dan Carpenter @ 2012-11-21 9:04 UTC (permalink / raw)
To: Johan Meiring; +Cc: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel
On Tue, Nov 20, 2012 at 07:28:52PM +0200, Johan Meiring wrote:
> This commit sorts out a single case where a line was longer than
> 80 characters.
>
> Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
> ---
> drivers/staging/cxt1e1/sbecrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
> index 87512a5..59dd7e2 100644
> --- a/drivers/staging/cxt1e1/sbecrc.c
> +++ b/drivers/staging/cxt1e1/sbecrc.c
> @@ -101,7 +101,8 @@ sbeCrc(u_int8_t *buffer, /* data buffer to crc */
> tbl = &CRCTable;
> genCrcTable(tbl);
> #else
> - tbl = (u_int32_t *) OS_kmalloc(CRC_TABLE_ENTRIES * sizeof(u_int32_t));
> + tbl = (u_int32_t *) OS_kmalloc(CRC_TABLE_ENTRIES
> + * sizeof(u_int32_t));
The way we would normally break this is:
tbl = (u_int32_t *)OS_kmalloc(CRC_TABLE_ENTRIES *
sizeof(u_int32_t));
* goes on the first line so that it shows this is a partial line.
The sizeof() lines up with the first parameter. You will have to
use spaces since it's not exactly on a tab stop.
But really it's better to just get rid of the call to OS_kmalloc().
tbl = kmalloc(CRC_TABLE_ENTRIES * sizeof(*tbl), GFP_KERNEL);
OS_kmalloc() adds a GFP_DMA flag and a memset() but it's not needed
here.
regards,
dan carpenter
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses
2012-11-20 17:28 ` [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses Johan Meiring
@ 2012-11-21 9:07 ` Dan Carpenter
0 siblings, 0 replies; 12+ messages in thread
From: Dan Carpenter @ 2012-11-21 9:07 UTC (permalink / raw)
To: Johan Meiring; +Cc: gregkh, a.beregalov, devendra.aaru, devel, linux-kernel
On Tue, Nov 20, 2012 at 07:28:48PM +0200, Johan Meiring wrote:
> This commit fixes several incorrect placements of parantheses, as
> identified by the checkpatch.pl tool.
>
This patch is fine, and all.
Acked-by: Dan Carpenter <dan.carpenter@oracle.com>
But you could go beyond fixing just checkpatch.pl warnings.
> Signed-off-by: Johan Meiring <johanmeiring@gmail.com>
> ---
> drivers/staging/cxt1e1/musycc.c | 490 +++++++++++++++++++--------------------
> 1 file changed, 245 insertions(+), 245 deletions(-)
>
> diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
> index 42e1ca4..b2cc68a 100644
> --- a/drivers/staging/cxt1e1/musycc.c
> +++ b/drivers/staging/cxt1e1/musycc.c
> @@ -60,21 +60,21 @@ extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
>
> /*******************************************************************/
This line could be deleted.
> /* forward references */
Obvious comment is obvious.
> -void c4_fifo_free (mpi_t *, int);
> -void c4_wk_chan_restart (mch_t *);
> -void musycc_bh_tx_eom (mpi_t *, int);
> -int musycc_chan_up (ci_t *, int);
> -status_t __init musycc_init (ci_t *);
> -STATIC void __init musycc_init_port (mpi_t *);
> -void musycc_intr_bh_tasklet (ci_t *);
> -void musycc_serv_req (mpi_t *, u_int32_t);
> -void musycc_update_timeslots (mpi_t *);
> +void c4_fifo_free(mpi_t *, int);
> +void c4_wk_chan_restart(mch_t *);
> +void musycc_bh_tx_eom(mpi_t *, int);
> +int musycc_chan_up(ci_t *, int);
> +status_t __init musycc_init(ci_t *);
> +STATIC void __init musycc_init_port(mpi_t *);
> +void musycc_intr_bh_tasklet(ci_t *);
> +void musycc_serv_req(mpi_t *, u_int32_t);
> +void musycc_update_timeslots(mpi_t *);
These would look better done properly.
void musycc_serv_req(mpi_t *pi, u_int32_t req);
Keep the parameter names because they serve as documentation. And
actually, they should be moved to a header file which is included
instead of declared in the .c files where they are used.
regards,
dan carpenter
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2012-11-21 9:08 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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2012-11-20 17:28 [PATCH 01/10] staging: cxt1e1: musycc.h: fixes indentation issues Johan Meiring
2012-11-20 17:28 ` [PATCH 02/10] staging: cxt1e1: musycc.h: fixes coding style issues Johan Meiring
2012-11-20 17:28 ` [PATCH 03/10] staging: cxt1e1: musycc.h: fixes brace placement Johan Meiring
2012-11-20 17:28 ` [PATCH 04/10] staging: cxt1e1: musycc.c: uses tabs for indentation Johan Meiring
2012-11-20 17:28 ` [PATCH 05/10] staging: cxt1e1: musycc.c: fixes brace placement Johan Meiring
2012-11-20 17:28 ` [PATCH 06/10] staging: cxt1e1: musycc.c: fixes placement of parentheses Johan Meiring
2012-11-21 9:07 ` Dan Carpenter
2012-11-20 17:28 ` [PATCH 07/10] staging: cxt1e1: sbecrc.c: fixes indentation issues Johan Meiring
2012-11-20 17:28 ` [PATCH 08/10] staging: cxt1e1: sbecrc.c: fixes brace placement Johan Meiring
2012-11-20 17:28 ` [PATCH 09/10] staging: cxt1e1: sbecrc.c: fixes coding style issue Johan Meiring
2012-11-20 17:28 ` [PATCH 10/10] staging: cxt1e1: sbecrc.c: fixes 80+ char line length issue Johan Meiring
2012-11-21 9:04 ` Dan Carpenter
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