From: Robert Richter <rric@kernel.org>
To: Jacob Shin <jacob.shin@amd.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Stephane Eranian <eranian@google.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] perf, amd: Enable northbridge performance counters on AMD family 15h
Date: Tue, 27 Nov 2012 13:10:51 +0100 [thread overview]
Message-ID: <20121127121051.GF1877@rric.localhost> (raw)
In-Reply-To: <1353970111-4508-5-git-send-email-jacob.shin@amd.com>
One minor comment:
On 26.11.12 16:48:30, Jacob Shin wrote:
> __init int amd_pmu_init(void)
> {
> /* Performance-monitoring supported from K7 and later: */
> @@ -666,6 +749,10 @@ __init int amd_pmu_init(void)
> setup_event_constraints();
> setup_perfctr_core();
>
> + num_core_counters = x86_pmu.num_counters;
I would better move this to setup_perfctr_nb().
> +
> + setup_perfctr_nb();
> +
> /* Events are common for all AMDs */
> memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
Otherwise the whole patch set looks good.
Acked-by: Robert Richter <rric@kernel.org>
Thanks Jacob.
-Robert
next prev parent reply other threads:[~2012-11-27 12:11 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-26 22:48 [PATCH V3 0/5] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2012-11-26 22:48 ` [PATCH 1/5] perf, amd: Rework northbridge event constraints handler Jacob Shin
2012-11-26 22:48 ` [PATCH 2/5] perf, amd: Generalize northbridge constraints code for family 15h Jacob Shin
2012-11-26 22:48 ` [PATCH 3/5] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2012-11-26 22:48 ` [PATCH 4/5] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2012-11-27 12:10 ` Robert Richter [this message]
2012-11-27 16:37 ` Jacob Shin
2012-11-26 22:48 ` [PATCH 5/5] perf, amd: Use proper naming scheme for AMD bit field definitions Jacob Shin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20121127121051.GF1877@rric.localhost \
--to=rric@kernel.org \
--cc=a.p.zijlstra@chello.nl \
--cc=acme@ghostprotocols.net \
--cc=eranian@google.com \
--cc=hpa@zytor.com \
--cc=jacob.shin@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=paulus@samba.org \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox