From: Mark Brown <broonie@kernel.org>
To: Nicolin Chen <Guangyu.Chen@freescale.com>
Cc: Xiubo Li-B47053 <Li.Xiubo@freescale.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>
Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
Date: Thu, 27 Mar 2014 10:54:36 +0000 [thread overview]
Message-ID: <20140327105436.GF30768@sirena.org.uk> (raw)
In-Reply-To: <20140327035726.GA16359@MrMyself>
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On Thu, Mar 27, 2014 at 11:57:27AM +0800, Nicolin Chen wrote:
> On Thu, Mar 27, 2014 at 12:06:53PM +0800, Xiubo Li-B47053 wrote:
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are all the
> > Same as above, and nothing else.
> > Have I missed ?
> What i.MX IC team told me is SAI ignores what we do to FWF and FRF, so you
> don't need to worry about it at all unless Vybrid makes them writable, in
> which case we may also need to clear these bits and confirm with Vybrid IC
> team if they're also W1C.
And even if it payed attention I'd expect that a lot of the time they'd
just be reasserted immediately as the condition still holds.
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prev parent reply other threads:[~2014-03-27 10:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-26 11:48 [PATCH] ASoC: fsl_sai: Add isr to deal with error flag Nicolin Chen
2014-03-26 11:59 ` David Laight
2014-03-27 1:14 ` Mark Brown
2014-03-27 2:29 ` [alsa-devel] " Nicolin Chen
2014-03-27 9:41 ` David Laight
2014-03-27 13:05 ` Mark Brown
2014-03-27 2:13 ` Li.Xiubo
2014-03-27 2:36 ` Nicolin Chen
2014-03-27 2:53 ` Li.Xiubo
2014-03-27 2:56 ` Nicolin Chen
2014-03-27 3:41 ` Li.Xiubo
2014-03-27 3:31 ` Nicolin Chen
2014-03-27 4:06 ` Li.Xiubo
2014-03-27 3:57 ` Nicolin Chen
2014-03-27 4:18 ` Li.Xiubo
2014-03-27 10:54 ` Mark Brown [this message]
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