* [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11
@ 2014-09-12 11:45 Mark yao
2014-09-25 15:27 ` Doug Anderson
2014-09-25 21:45 ` Mike Turquette
0 siblings, 2 replies; 3+ messages in thread
From: Mark yao @ 2014-09-12 11:45 UTC (permalink / raw)
To: Mike Turquette, heiko, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala
Cc: devicetree, linux-kernel, djkurtz, dianders, dkl, eddie.cai, xjq,
kfx, huangtao, zyw, yxj, cym, zhengsq, caesar.wang, kever.yang,
Mark yao
The patch add the rest of the indices of the additional reset
registers from the updated TRM.
Signed-off-by: Mark yao <mark.yao@rock-chips.com>
---
include/dt-bindings/clock/rk3288-cru.h | 43 ++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index ebcb460..e65d522 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -276,3 +276,46 @@
#define SRST_USBHOST1_CON 140
#define SRST_USB_ADP 141
#define SRST_ACC_EFUSE 142
+
+#define SRST_CORESIGHT 144
+#define SRST_PD_CORE_AHB_NOC 145
+#define SRST_PD_CORE_APB_NOC 146
+#define SRST_PD_CORE_MP_AXI 147
+#define SRST_GIC 148
+#define SRST_LCDC_PWM0 149
+#define SRST_LCDC_PWM1 150
+#define SRST_VIO0_H2P_BRG 151
+#define SRST_VIO1_H2P_BRG 152
+#define SRST_RGA_H2P_BRG 153
+#define SRST_HEVC 154
+#define SRST_TSADC 159
+
+#define SRST_DDRPHY0 160
+#define SRST_DDRPHY0_APB 161
+#define SRST_DDRCTRL0 162
+#define SRST_DDRCTRL0_APB 163
+#define SRST_DDRPHY0_CTRL 164
+#define SRST_DDRPHY1 165
+#define SRST_DDRPHY1_APB 166
+#define SRST_DDRCTRL1 167
+#define SRST_DDRCTRL1_APB 168
+#define SRST_DDRPHY1_CTRL 169
+#define SRST_DDRMSCH0 170
+#define SRST_DDRMSCH1 171
+#define SRST_CRYPTO 174
+#define SRST_C2C_HOST 175
+
+#define SRST_LCDC1_AXI 176
+#define SRST_LCDC1_AHB 177
+#define SRST_LCDC1_DCLK 178
+#define SRST_UART0 179
+#define SRST_UART1 180
+#define SRST_UART2 181
+#define SRST_UART3 182
+#define SRST_UART4 183
+#define SRST_SIMC 186
+#define SRST_PS2C 187
+#define SRST_TSP 188
+#define SRST_TSP_CLKIN0 189
+#define SRST_TSP_CLKIN1 190
+#define SRST_TSP_27M 191
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11
2014-09-12 11:45 [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11 Mark yao
@ 2014-09-25 15:27 ` Doug Anderson
2014-09-25 21:45 ` Mike Turquette
1 sibling, 0 replies; 3+ messages in thread
From: Doug Anderson @ 2014-09-25 15:27 UTC (permalink / raw)
To: Mark yao
Cc: Mike Turquette, Heiko Stübner, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Daniel Kurtz, 戴克霖 (Jack), Eddie Cai,
Jianqun Xu, 柯飞雄, Tao Huang, Chris,
闫孝军, jeff chen, Shunqian Zheng,
晓腾王, Kever Yang
Mark,
On Fri, Sep 12, 2014 at 4:45 AM, Mark yao <mark.yao@rock-chips.com> wrote:
> The patch add the rest of the indices of the additional reset
> registers from the updated TRM.
>
> Signed-off-by: Mark yao <mark.yao@rock-chips.com>
> ---
> include/dt-bindings/clock/rk3288-cru.h | 43 ++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
> index ebcb460..e65d522 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -276,3 +276,46 @@
> #define SRST_USBHOST1_CON 140
> #define SRST_USB_ADP 141
> #define SRST_ACC_EFUSE 142
> +
> +#define SRST_CORESIGHT 144
> +#define SRST_PD_CORE_AHB_NOC 145
> +#define SRST_PD_CORE_APB_NOC 146
> +#define SRST_PD_CORE_MP_AXI 147
> +#define SRST_GIC 148
> +#define SRST_LCDC_PWM0 149
> +#define SRST_LCDC_PWM1 150
> +#define SRST_VIO0_H2P_BRG 151
> +#define SRST_VIO1_H2P_BRG 152
> +#define SRST_RGA_H2P_BRG 153
> +#define SRST_HEVC 154
> +#define SRST_TSADC 159
> +
> +#define SRST_DDRPHY0 160
> +#define SRST_DDRPHY0_APB 161
> +#define SRST_DDRCTRL0 162
> +#define SRST_DDRCTRL0_APB 163
> +#define SRST_DDRPHY0_CTRL 164
> +#define SRST_DDRPHY1 165
> +#define SRST_DDRPHY1_APB 166
> +#define SRST_DDRCTRL1 167
> +#define SRST_DDRCTRL1_APB 168
> +#define SRST_DDRPHY1_CTRL 169
> +#define SRST_DDRMSCH0 170
> +#define SRST_DDRMSCH1 171
Interestingly 170 and 171 show as Reserved in my TRM... ...but if
that's what the reserved bits map to then I have no objection.
> +#define SRST_CRYPTO 174
> +#define SRST_C2C_HOST 175
> +
> +#define SRST_LCDC1_AXI 176
> +#define SRST_LCDC1_AHB 177
> +#define SRST_LCDC1_DCLK 178
> +#define SRST_UART0 179
> +#define SRST_UART1 180
> +#define SRST_UART2 181
> +#define SRST_UART3 182
> +#define SRST_UART4 183
> +#define SRST_SIMC 186
> +#define SRST_PS2C 187
> +#define SRST_TSP 188
> +#define SRST_TSP_CLKIN0 189
> +#define SRST_TSP_CLKIN1 190
> +#define SRST_TSP_27M 191
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11
2014-09-12 11:45 [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11 Mark yao
2014-09-25 15:27 ` Doug Anderson
@ 2014-09-25 21:45 ` Mike Turquette
1 sibling, 0 replies; 3+ messages in thread
From: Mike Turquette @ 2014-09-25 21:45 UTC (permalink / raw)
To: Mark yao, heiko, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala
Cc: devicetree, linux-kernel, djkurtz, dianders, dkl, eddie.cai, xjq,
kfx, huangtao, zyw, yxj, cym, zhengsq, caesar.wang, kever.yang,
Mark yao
Quoting Mark yao (2014-09-12 04:45:27)
> The patch add the rest of the indices of the additional reset
> registers from the updated TRM.
>
> Signed-off-by: Mark yao <mark.yao@rock-chips.com>
Applied to clk-next.
Regards,
Mike
> ---
> include/dt-bindings/clock/rk3288-cru.h | 43 ++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
> index ebcb460..e65d522 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -276,3 +276,46 @@
> #define SRST_USBHOST1_CON 140
> #define SRST_USB_ADP 141
> #define SRST_ACC_EFUSE 142
> +
> +#define SRST_CORESIGHT 144
> +#define SRST_PD_CORE_AHB_NOC 145
> +#define SRST_PD_CORE_APB_NOC 146
> +#define SRST_PD_CORE_MP_AXI 147
> +#define SRST_GIC 148
> +#define SRST_LCDC_PWM0 149
> +#define SRST_LCDC_PWM1 150
> +#define SRST_VIO0_H2P_BRG 151
> +#define SRST_VIO1_H2P_BRG 152
> +#define SRST_RGA_H2P_BRG 153
> +#define SRST_HEVC 154
> +#define SRST_TSADC 159
> +
> +#define SRST_DDRPHY0 160
> +#define SRST_DDRPHY0_APB 161
> +#define SRST_DDRCTRL0 162
> +#define SRST_DDRCTRL0_APB 163
> +#define SRST_DDRPHY0_CTRL 164
> +#define SRST_DDRPHY1 165
> +#define SRST_DDRPHY1_APB 166
> +#define SRST_DDRCTRL1 167
> +#define SRST_DDRCTRL1_APB 168
> +#define SRST_DDRPHY1_CTRL 169
> +#define SRST_DDRMSCH0 170
> +#define SRST_DDRMSCH1 171
> +#define SRST_CRYPTO 174
> +#define SRST_C2C_HOST 175
> +
> +#define SRST_LCDC1_AXI 176
> +#define SRST_LCDC1_AHB 177
> +#define SRST_LCDC1_DCLK 178
> +#define SRST_UART0 179
> +#define SRST_UART1 180
> +#define SRST_UART2 181
> +#define SRST_UART3 182
> +#define SRST_UART4 183
> +#define SRST_SIMC 186
> +#define SRST_PS2C 187
> +#define SRST_TSP 188
> +#define SRST_TSP_CLKIN0 189
> +#define SRST_TSP_CLKIN1 190
> +#define SRST_TSP_27M 191
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-09-12 11:45 [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11 Mark yao
2014-09-25 15:27 ` Doug Anderson
2014-09-25 21:45 ` Mike Turquette
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