[PATCH 01/28] serial: earlycon: allow MEM32 I/O for DT earlycon

[PATCH 01/28] serial: earlycon: allow MEM32 I/O for DT earlycon

[Paul Burton]

Read the reg-io-width property when earlycon is setup via device tree,
and set the I/O type to UPIO_MEM32 when 4 is read. This behaviour
matches that of the of_serial driver, and is needed for DT configured
earlycon on the MIPS Boston board.

Note that this is only possible when CONFIG_LIBFDT is enabled, but
enabling it everywhere seems like overkill. Thus systems that need this
functionality should select CONFIG_LIBFDT for themselves.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/of/fdt.c              |  2 +-
 drivers/tty/serial/Makefile   |  1 +
 drivers/tty/serial/earlycon.c | 15 ++++++++++++++-
 include/linux/serial_core.h   |  2 +-
 4 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index d243029..71c7f0d 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -833,7 +833,7 @@ static int __init early_init_dt_scan_chosen_serial(void)
 		if (addr == OF_BAD_ADDR)
 			return -ENXIO;
 
-		of_setup_earlycon(addr, match->data);
+		of_setup_earlycon(fdt, offset, addr, match->data);
 		return 0;
 	}
 	return -ENODEV;
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 5ab4111..1d290d6 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SERIAL_21285) += 21285.o
 
 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
 obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
+CFLAGS_earlycon.o += -I$(srctree)/scripts/dtc/libfdt
 
 # These Sparc drivers have to appear before others such as 8250
 # which share ttySx minor node space.  Otherwise console device
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index f096360..2b936a7 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/libfdt.h>
 #include <linux/serial_core.h>
 #include <linux/sizes.h>
 #include <linux/mod_devicetable.h>
@@ -196,17 +197,29 @@ static int __init param_setup_earlycon(char *buf)
 }
 early_param("earlycon", param_setup_earlycon);
 
-int __init of_setup_earlycon(unsigned long addr,
+int __init of_setup_earlycon(const void *fdt, int offset, unsigned long addr,
 			     int (*setup)(struct earlycon_device *, const char *))
 {
 	int err;
 	struct uart_port *port = &early_console_dev.port;
+	const __be32 *prop;
 
 	port->iotype = UPIO_MEM;
 	port->mapbase = addr;
 	port->uartclk = BASE_BAUD * 16;
 	port->membase = earlycon_map(addr, SZ_4K);
 
+	if (config_enabled(CONFIG_LIBFDT)) {
+		prop = fdt_getprop(fdt, offset, "reg-io-width", NULL);
+		if (prop) {
+			switch (be32_to_cpup(prop)) {
+			case 4:
+				port->iotype = UPIO_MEM32;
+				break;
+			}
+		}
+	}
+
 	early_console_dev.con->data = &early_console_dev;
 	err = setup(&early_console_dev, NULL);
 	if (err < 0)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 297d4fa..aa375f1 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -345,7 +345,7 @@ struct earlycon_id {
 } __aligned(32);
 
 extern int setup_earlycon(char *buf);
-extern int of_setup_earlycon(unsigned long addr,
+extern int of_setup_earlycon(const void *fdt, int offset, unsigned long addr,
 			     int (*setup)(struct earlycon_device *, const char *));
 
 #define EARLYCON_DECLARE(_name, func)					\
-- 
2.6.2

Re: [PATCH 01/28] serial: earlycon: allow MEM32 I/O for DT earlycon

[Rob Herring]

On Mon, Nov 30, 2015 at 10:21 AM, Paul Burton <paul.burton@imgtec.com> wrote:
> Read the reg-io-width property when earlycon is setup via device tree,
> and set the I/O type to UPIO_MEM32 when 4 is read. This behaviour
> matches that of the of_serial driver, and is needed for DT configured
> earlycon on the MIPS Boston board.
>
> Note that this is only possible when CONFIG_LIBFDT is enabled, but
> enabling it everywhere seems like overkill. Thus systems that need this
> functionality should select CONFIG_LIBFDT for themselves.

libfdt is enabled if you are booting from DT, so checking this
property should not add anything.

>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>  drivers/of/fdt.c              |  2 +-
>  drivers/tty/serial/Makefile   |  1 +
>  drivers/tty/serial/earlycon.c | 15 ++++++++++++++-
>  include/linux/serial_core.h   |  2 +-
>  4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index d243029..71c7f0d 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -833,7 +833,7 @@ static int __init early_init_dt_scan_chosen_serial(void)
>                 if (addr == OF_BAD_ADDR)
>                         return -ENXIO;
>
> -               of_setup_earlycon(addr, match->data);
> +               of_setup_earlycon(fdt, offset, addr, match->data);
>                 return 0;
>         }
>         return -ENODEV;
> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
> index 5ab4111..1d290d6 100644
> --- a/drivers/tty/serial/Makefile
> +++ b/drivers/tty/serial/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_SERIAL_21285) += 21285.o
>
>  obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
>  obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
> +CFLAGS_earlycon.o += -I$(srctree)/scripts/dtc/libfdt

This is no longer necessary.

>
>  # These Sparc drivers have to appear before others such as 8250
>  # which share ttySx minor node space.  Otherwise console device
> diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
> index f096360..2b936a7 100644
> --- a/drivers/tty/serial/earlycon.c
> +++ b/drivers/tty/serial/earlycon.c
> @@ -17,6 +17,7 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/libfdt.h>
>  #include <linux/serial_core.h>
>  #include <linux/sizes.h>
>  #include <linux/mod_devicetable.h>
> @@ -196,17 +197,29 @@ static int __init param_setup_earlycon(char *buf)
>  }
>  early_param("earlycon", param_setup_earlycon);
>
> -int __init of_setup_earlycon(unsigned long addr,
> +int __init of_setup_earlycon(const void *fdt, int offset, unsigned long addr,

I would add iotype as a parameter instead, and then...

>                              int (*setup)(struct earlycon_device *, const char *))
>  {
>         int err;
>         struct uart_port *port = &early_console_dev.port;
> +       const __be32 *prop;
>
>         port->iotype = UPIO_MEM;
>         port->mapbase = addr;
>         port->uartclk = BASE_BAUD * 16;
>         port->membase = earlycon_map(addr, SZ_4K);
>
> +       if (config_enabled(CONFIG_LIBFDT)) {
> +               prop = fdt_getprop(fdt, offset, "reg-io-width", NULL);
> +               if (prop) {
> +                       switch (be32_to_cpup(prop)) {
> +                       case 4:
> +                               port->iotype = UPIO_MEM32;
> +                               break;
> +                       }
> +               }

...move this parsing into fdt.c where we parse the address.

Rob

Re: [PATCH 01/28] serial: earlycon: allow MEM32 I/O for DT earlycon

[Peter Hurley]

On 11/30/2015 05:52 PM, Rob Herring wrote:
> On Mon, Nov 30, 2015 at 10:21 AM, Paul Burton <paul.burton@imgtec.com> wrote:
>> Read the reg-io-width property when earlycon is setup via device tree,
>> and set the I/O type to UPIO_MEM32 when 4 is read. This behaviour
>> matches that of the of_serial driver, and is needed for DT configured
>> earlycon on the MIPS Boston board.
>>
>> Note that this is only possible when CONFIG_LIBFDT is enabled, but
>> enabling it everywhere seems like overkill. Thus systems that need this
>> functionality should select CONFIG_LIBFDT for themselves.
> 
> libfdt is enabled if you are booting from DT, so checking this
> property should not add anything.
> 
>>
>> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
>> ---
>>
>>  drivers/of/fdt.c              |  2 +-
>>  drivers/tty/serial/Makefile   |  1 +
>>  drivers/tty/serial/earlycon.c | 15 ++++++++++++++-
>>  include/linux/serial_core.h   |  2 +-
>>  4 files changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
>> index d243029..71c7f0d 100644
>> --- a/drivers/of/fdt.c
>> +++ b/drivers/of/fdt.c
>> @@ -833,7 +833,7 @@ static int __init early_init_dt_scan_chosen_serial(void)
>>                 if (addr == OF_BAD_ADDR)
>>                         return -ENXIO;
>>
>> -               of_setup_earlycon(addr, match->data);
>> +               of_setup_earlycon(fdt, offset, addr, match->data);
>>                 return 0;
>>         }
>>         return -ENODEV;
>> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
>> index 5ab4111..1d290d6 100644
>> --- a/drivers/tty/serial/Makefile
>> +++ b/drivers/tty/serial/Makefile
>> @@ -7,6 +7,7 @@ obj-$(CONFIG_SERIAL_21285) += 21285.o
>>
>>  obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
>>  obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
>> +CFLAGS_earlycon.o += -I$(srctree)/scripts/dtc/libfdt
> 
> This is no longer necessary.
> 
>>
>>  # These Sparc drivers have to appear before others such as 8250
>>  # which share ttySx minor node space.  Otherwise console device
>> diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
>> index f096360..2b936a7 100644
>> --- a/drivers/tty/serial/earlycon.c
>> +++ b/drivers/tty/serial/earlycon.c
>> @@ -17,6 +17,7 @@
>>  #include <linux/kernel.h>
>>  #include <linux/init.h>
>>  #include <linux/io.h>
>> +#include <linux/libfdt.h>
>>  #include <linux/serial_core.h>
>>  #include <linux/sizes.h>
>>  #include <linux/mod_devicetable.h>
>> @@ -196,17 +197,29 @@ static int __init param_setup_earlycon(char *buf)
>>  }
>>  early_param("earlycon", param_setup_earlycon);
>>
>> -int __init of_setup_earlycon(unsigned long addr,
>> +int __init of_setup_earlycon(const void *fdt, int offset, unsigned long addr,
> 
> I would add iotype as a parameter instead, and then...
> 
>>                              int (*setup)(struct earlycon_device *, const char *))
>>  {
>>         int err;
>>         struct uart_port *port = &early_console_dev.port;
>> +       const __be32 *prop;
>>
>>         port->iotype = UPIO_MEM;
>>         port->mapbase = addr;
>>         port->uartclk = BASE_BAUD * 16;
>>         port->membase = earlycon_map(addr, SZ_4K);
>>
>> +       if (config_enabled(CONFIG_LIBFDT)) {
>> +               prop = fdt_getprop(fdt, offset, "reg-io-width", NULL);
>> +               if (prop) {
>> +                       switch (be32_to_cpup(prop)) {
>> +                       case 4:
>> +                               port->iotype = UPIO_MEM32;
>> +                               break;
>> +                       }
>> +               }
> 
> ...move this parsing into fdt.c where we parse the address.

FWIW, all of of_setup_earlycon() should only be #ifdef CONFIG_OF_EARLY_FLATTREE

Regards,
Peter Hurley

[PATCH 02/28] dt-bindings: ascii-lcd: Document a binding for simple ASCII LCDs

[Paul Burton]

Add documentation for a devicetree binding for simple memory-mapped
ASCII LCD displays, such as those found on the Imagination Technologies
Boston & Malta development boards.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 Documentation/devicetree/bindings/ascii-lcd.txt | 10 ++++++++++
 MAINTAINERS                                     |  5 +++++
 2 files changed, 15 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ascii-lcd.txt

diff --git a/Documentation/devicetree/bindings/ascii-lcd.txt b/Documentation/devicetree/bindings/ascii-lcd.txt
new file mode 100644
index 0000000..40ae536
--- /dev/null
+++ b/Documentation/devicetree/bindings/ascii-lcd.txt
@@ -0,0 +1,10 @@
+Binding for simple memory-mapped ASCII LCD displays
+
+Required properties:
+- compatible : should be one of:
+    "img,boston-lcd"
+    "mti,malta-lcd"
+- reg : memory region locating the device registers
+
+The layout of the registers & properties of the display are determined
+from the compatible string, making this binding somewhat trivial.
diff --git a/MAINTAINERS b/MAINTAINERS
index cba790b..1e2b74b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1782,6 +1782,11 @@ S:	Maintained
 F:	Documentation/hwmon/asc7621
 F:	drivers/hwmon/asc7621.c
 
+ASCII LCD DRIVER
+M:	Paul Burton <paul.burton@imgtec.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/ascii-lcd.txt
+
 ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
 M:	Corentin Chary <corentin.chary@gmail.com>
 L:	acpi4asus-user@lists.sourceforge.net
-- 
2.6.2

Re: [PATCH 02/28] dt-bindings: ascii-lcd: Document a binding for simple ASCII LCDs

[Rob Herring]

On Mon, Nov 30, 2015 at 04:21:27PM +0000, Paul Burton wrote:
> Add documentation for a devicetree binding for simple memory-mapped
> ASCII LCD displays, such as those found on the Imagination Technologies
> Boston & Malta development boards.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
> 
>  Documentation/devicetree/bindings/ascii-lcd.txt | 10 ++++++++++

This should go under bindings/display/.

>  MAINTAINERS                                     |  5 +++++
>  2 files changed, 15 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/ascii-lcd.txt
> 
> diff --git a/Documentation/devicetree/bindings/ascii-lcd.txt b/Documentation/devicetree/bindings/ascii-lcd.txt
> new file mode 100644
> index 0000000..40ae536
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ascii-lcd.txt
> @@ -0,0 +1,10 @@
> +Binding for simple memory-mapped ASCII LCD displays

Presumably, this is a binding for the controller, not the actual 
display. You need to more fully describe what the h/w looks like here. 
Like what is the interface between the controller and display?

Rob

> +
> +Required properties:
> +- compatible : should be one of:
> +    "img,boston-lcd"
> +    "mti,malta-lcd"
> +- reg : memory region locating the device registers
> +
> +The layout of the registers & properties of the display are determined
> +from the compatible string, making this binding somewhat trivial.
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cba790b..1e2b74b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1782,6 +1782,11 @@ S:	Maintained
>  F:	Documentation/hwmon/asc7621
>  F:	drivers/hwmon/asc7621.c
>  
> +ASCII LCD DRIVER
> +M:	Paul Burton <paul.burton@imgtec.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/ascii-lcd.txt
> +
>  ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
>  M:	Corentin Chary <corentin.chary@gmail.com>
>  L:	acpi4asus-user@lists.sourceforge.net
> -- 
> 2.6.2
> 

[PATCH 03/28] auxdisplay: driver for simple memory mapped ASCII LCD displays

[Paul Burton]

Add a driver for simple memory mapped ASCII LCD displays such as those
found on the MIPS Malta & Boston development boards. The driver displays
the Linux kernel version as the default message, but allows the message
to be changed via a character device. Messages longer then the number of
characters that the display can show will scroll.

This provides different behaviour to the existing LCD display code for
the MIPS Malta platform in the following ways:

  - The default string to display is not "LINUX ON MALTA" but "Linux"
    followed by the version number of the kernel (UTS_RELEASE).

  - Since that string tends to significantly longer it scrolls twice
    as fast, moving every 500ms rather than every 1s.

  - The LCD won't be updated until the driver is probed, so it doesn't
    provide the early "LINUX" string.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 MAINTAINERS                    |   1 +
 drivers/auxdisplay/Kconfig     |   7 ++
 drivers/auxdisplay/Makefile    |   1 +
 drivers/auxdisplay/ascii-lcd.c | 230 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 239 insertions(+)
 create mode 100644 drivers/auxdisplay/ascii-lcd.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1e2b74b..2e156b2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1786,6 +1786,7 @@ ASCII LCD DRIVER
 M:	Paul Burton <paul.burton@imgtec.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/ascii-lcd.txt
+F:	drivers/auxdisplay/ascii-lcd.c
 
 ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
 M:	Corentin Chary <corentin.chary@gmail.com>
diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
index c07e725..a465e0d 100644
--- a/drivers/auxdisplay/Kconfig
+++ b/drivers/auxdisplay/Kconfig
@@ -119,4 +119,11 @@ config CFAG12864B_RATE
 	  If you compile this as a module, you can still override this
 	  value using the module parameters.
 
+config ASCII_LCD
+	tristate "ASCII LCD Display"
+	default y if MIPS_MALTA
+	help
+	  Enable this to support simple memory mapped ASCII LCD displays such
+	  as those found on the MIPS Malta & Boston development boards.
+
 endif # AUXDISPLAY
diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile
index 8a8936a..8a5aa81 100644
--- a/drivers/auxdisplay/Makefile
+++ b/drivers/auxdisplay/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_KS0108)		+= ks0108.o
 obj-$(CONFIG_CFAG12864B)	+= cfag12864b.o cfag12864bfb.o
+obj-$(CONFIG_ASCII_LCD)		+= ascii-lcd.o
diff --git a/drivers/auxdisplay/ascii-lcd.c b/drivers/auxdisplay/ascii-lcd.c
new file mode 100644
index 0000000..5c9ec32
--- /dev/null
+++ b/drivers/auxdisplay/ascii-lcd.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <generated/utsrelease.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+
+struct ascii_lcd_ctx;
+
+struct ascii_lcd_config {
+	unsigned num_chars;
+	void (*update)(struct ascii_lcd_ctx *ctx);
+};
+
+struct ascii_lcd_ctx {
+	struct platform_device *pdev;
+	void __iomem *base;
+	const struct ascii_lcd_config *cfg;
+	char *message;
+	unsigned message_len;
+	unsigned scroll_pos;
+	unsigned scroll_rate;
+	struct timer_list timer;
+	char curr[] __aligned(8);
+};
+
+static void update_boston(struct ascii_lcd_ctx *ctx)
+{
+	u32 val32;
+	u64 val64;
+
+	if (config_enabled(CONFIG_64BIT)) {
+		val64 = *((u64 *)&ctx->curr[0]);
+		__raw_writeq(val64, ctx->base);
+	} else {
+		val32 = *((u32 *)&ctx->curr[0]);
+		__raw_writel(val32, ctx->base);
+		val32 = *((u32 *)&ctx->curr[4]);
+		__raw_writel(val32, ctx->base + 4);
+	}
+}
+
+static void update_malta(struct ascii_lcd_ctx *ctx)
+{
+	unsigned i;
+
+	for (i = 0; i < ctx->cfg->num_chars; i++)
+		__raw_writel(ctx->curr[i], ctx->base + (i * 8));
+}
+
+static struct ascii_lcd_config boston_config = {
+	.num_chars = 8,
+	.update = update_boston,
+};
+
+static struct ascii_lcd_config malta_config = {
+	.num_chars = 8,
+	.update = update_malta,
+};
+
+static const struct of_device_id ascii_lcd_matches[] = {
+	{ .compatible = "img,boston-lcd", .data = &boston_config },
+	{ .compatible = "mti,malta-lcd", .data = &malta_config },
+};
+
+static void ascii_lcd_scroll(unsigned long arg)
+{
+	struct ascii_lcd_ctx *ctx = (struct ascii_lcd_ctx *)arg;
+	unsigned i, ch = ctx->scroll_pos;
+	unsigned num_chars = ctx->cfg->num_chars;
+
+	/* update the current message string */
+	for (i = 0; i < num_chars;) {
+		/* copy as many characters from the string as possible */
+		for (; i < num_chars && ch < ctx->message_len; i++, ch++)
+			ctx->curr[i] = ctx->message[ch];
+
+		/* wrap around to the start of the string */
+		ch = 0;
+	}
+
+	/* update the LCD */
+	ctx->cfg->update(ctx);
+
+	/* move on to the next character */
+	ctx->scroll_pos++;
+	ctx->scroll_pos %= ctx->message_len;
+
+	/* rearm the timer */
+	if (ctx->message_len > ctx->cfg->num_chars)
+		mod_timer(&ctx->timer, jiffies + ctx->scroll_rate);
+}
+
+static int ascii_lcd_display(struct ascii_lcd_ctx *ctx,
+			     const char *msg, ssize_t count)
+{
+	char *new_msg;
+
+	/* stop the scroll timer */
+	del_timer_sync(&ctx->timer);
+
+	if (count == -1)
+		count = strlen(msg);
+
+	/* if the string ends with a newline, trim it */
+	if (msg[count - 1] == '\n')
+		count--;
+
+	new_msg = devm_kmalloc(&ctx->pdev->dev, count + 1, GFP_KERNEL);
+	if (!new_msg)
+		return -ENOMEM;
+
+	memcpy(new_msg, msg, count);
+	new_msg[count] = 0;
+
+	if (ctx->message)
+		devm_kfree(&ctx->pdev->dev, ctx->message);
+
+	ctx->message = new_msg;
+	ctx->message_len = count;
+	ctx->scroll_pos = 0;
+
+	/* update the LCD */
+	ascii_lcd_scroll((unsigned long)ctx);
+
+	return 0;
+}
+
+static ssize_t message_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct ascii_lcd_ctx *ctx = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", ctx->message);
+}
+
+static ssize_t message_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct ascii_lcd_ctx *ctx = dev_get_drvdata(dev);
+	int err;
+
+	err = ascii_lcd_display(ctx, buf, count);
+	return err ?: count;
+}
+
+static DEVICE_ATTR_RW(message);
+
+static int ascii_lcd_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	const struct ascii_lcd_config *cfg;
+	struct ascii_lcd_ctx *ctx;
+	struct resource *res;
+	int err;
+
+	match = of_match_device(ascii_lcd_matches, &pdev->dev);
+	if (!match)
+		return -ENODEV;
+
+	cfg = match->data;
+	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx) + cfg->num_chars,
+			   GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ctx->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(ctx->base))
+		return PTR_ERR(ctx->base);
+
+	ctx->pdev = pdev;
+	ctx->cfg = cfg;
+	ctx->message = NULL;
+	ctx->scroll_pos = 0;
+	ctx->scroll_rate = HZ / 2;
+
+	/* initialise a timer for scrolling the message */
+	init_timer(&ctx->timer);
+	ctx->timer.function = ascii_lcd_scroll;
+	ctx->timer.data = (unsigned long)ctx;
+
+	platform_set_drvdata(pdev, ctx);
+
+	/* display a default message */
+	err = ascii_lcd_display(ctx, "Linux " UTS_RELEASE "       ", -1);
+	if (err)
+		goto out_del_timer;
+
+	err = device_create_file(&pdev->dev, &dev_attr_message);
+	if (err)
+		goto out_del_timer;
+
+	return 0;
+out_del_timer:
+	del_timer_sync(&ctx->timer);
+	return err;
+}
+
+static int ascii_lcd_remove(struct platform_device *pdev)
+{
+	struct ascii_lcd_ctx *ctx = platform_get_drvdata(pdev);
+
+	device_remove_file(&pdev->dev, &dev_attr_message);
+	del_timer_sync(&ctx->timer);
+	return 0;
+}
+
+static struct platform_driver ascii_lcd_driver = {
+	.driver = {
+		.name		= "ascii-lcd",
+		.of_match_table	= ascii_lcd_matches,
+	},
+	.probe	= ascii_lcd_probe,
+	.remove	= ascii_lcd_remove,
+};
+module_platform_driver(ascii_lcd_driver);
-- 
2.6.2

[PATCH 04/28] MIPS: PCI: compatibility with ARM-like PCI host drivers

[Paul Burton]

Introduce support for struct hw_pci & the associated pci_common_init_dev
function as used by the PCI drivers written for ARM platforms under
drivers/pci. This is in preparation for reusing the xilinx-pcie driver
on the MIPS Boston board.

Platforms that make use of this more generic code will need to select
CONFIG_MIPS_GENERIC_PCI. Platforms which don't will continue to work as
they have, with the intent that PCI drivers be migrated towards struct
hw_pci & drivers/pci/ over time.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/Kconfig           |   6 ++
 arch/mips/include/asm/pci.h |  67 ++++++++++++-
 arch/mips/lib/iomap-pci.c   |   2 +-
 arch/mips/pci/Makefile      |   6 ++
 arch/mips/pci/pci-generic.c | 138 ++++++++++++++++++++++++++
 arch/mips/pci/pci-legacy.c  | 232 ++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/pci/pci.c         | 226 ++----------------------------------------
 7 files changed, 456 insertions(+), 221 deletions(-)
 create mode 100644 arch/mips/pci/pci-generic.c
 create mode 100644 arch/mips/pci/pci-legacy.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 71683a8..6d11a41 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2834,11 +2834,14 @@ config HW_HAS_EISA
 	bool
 config HW_HAS_PCI
 	bool
+config MIPS_GENERIC_PCI
+	bool
 
 config PCI
 	bool "Support for PCI controller"
 	depends on HW_HAS_PCI
 	select PCI_DOMAINS
+	select PCI_DOMAINS_GENERIC if MIPS_GENERIC_PCI
 	select NO_GENERIC_PCI_IOPORT_MAP
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
@@ -2860,6 +2863,9 @@ config HT_PCI
 config PCI_DOMAINS
 	bool
 
+config PCI_DOMAINS_GENERIC
+	bool
+
 source "drivers/pci/Kconfig"
 
 source "drivers/pci/pcie/Kconfig"
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 98c31e5..f02f3f8 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -19,12 +19,47 @@
 #include <linux/ioport.h>
 #include <linux/of.h>
 
+struct pci_sys_data;
+
+struct hw_pci {
+#ifdef CONFIG_PCI_DOMAINS
+	int		domain;
+#endif
+#ifdef CONFIG_PCI_MSI
+	struct msi_controller *msi_ctrl;
+#endif
+	struct pci_ops	*ops;
+	int		nr_controllers;
+	void		**private_data;
+	int		(*setup)(int nr, struct pci_sys_data *);
+	struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
+	void		(*preinit)(void);
+	void		(*postinit)(void);
+	u8		(*swizzle)(struct pci_dev *dev, u8 *pin);
+	int		(*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+	resource_size_t (*align_resource)(struct pci_dev *dev,
+					  const struct resource *res,
+					  resource_size_t start,
+					  resource_size_t size,
+					  resource_size_t align);
+};
+
+struct pci_sys_data {
+	int busnr;
+	struct list_head resources;
+	void *private_data;
+#ifdef CONFIG_PCI_MSI
+	struct msi_controller *msi_ctrl;
+#endif
+};
+
 /*
  * Each pci channel is a top-level PCI bus seem by CPU.	 A machine  with
  * multiple PCI channels may have multiple PCI host controllers or a
  * single controller supporting multiple channels.
  */
 struct pci_controller {
+	struct pci_sys_data sysdata;
 	struct pci_controller *next;
 	struct pci_bus *bus;
 	struct device_node *of_node;
@@ -45,17 +80,36 @@ struct pci_controller {
 
 	int iommu;
 
+	int		(*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+	resource_size_t (*align_resource)(struct pci_dev *dev,
+					  const struct resource *res,
+					  resource_size_t start,
+					  resource_size_t size,
+					  resource_size_t align);
+
 	/* Optional access methods for reading/writing the bus number
 	   of the PCI controller */
 	int (*get_busno)(void);
 	void (*set_busno)(int busno);
 };
 
+extern struct pci_controller *hose_head;
+
+static inline struct pci_controller *
+sysdata_to_hose(struct pci_sys_data *sysdata)
+{
+	return container_of(sysdata, struct pci_controller, sysdata);
+}
+
+extern void pci_common_init_dev(struct device *, struct hw_pci *);
+
 /*
  * Used by boards to register their PCI busses before the actual scanning.
  */
 extern void register_pci_controller(struct pci_controller *hose);
 
+extern void add_pci_controller(struct pci_controller *hose);
+
 /*
  * board supplied pci irq fixup routine
  */
@@ -113,12 +167,19 @@ struct pci_dev;
  */
 extern unsigned int PCI_DMA_BUS_IS_PHYS;
 
-#ifdef CONFIG_PCI_DOMAINS
-#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+	return pci_domain_nr(bus);
+}
+
+#elif defined(CONFIG_PCI_DOMAINS)
+#define pci_domain_nr(bus) (sysdata_to_hose(bus->sysdata)->index)
 
 static inline int pci_proc_domain(struct pci_bus *bus)
 {
-	struct pci_controller *hose = bus->sysdata;
+	struct pci_controller *hose = sysdata_to_hose(bus->sysdata);
 	return hose->need_domain_info;
 }
 #endif /* CONFIG_PCI_DOMAINS */
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index fd35daa..9595827 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -13,7 +13,7 @@
 void __iomem *__pci_ioport_map(struct pci_dev *dev,
 			       unsigned long port, unsigned int nr)
 {
-	struct pci_controller *ctrl = dev->bus->sysdata;
+	struct pci_controller *ctrl = sysdata_to_hose(dev->bus->sysdata);
 	unsigned long base = ctrl->io_map_base;
 
 	/* This will eventually become a BUG_ON but for now be gentle */
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 2eda01e..30e4cdc 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -4,6 +4,12 @@
 
 obj-y				+= pci.o
 
+ifeq ($(CONFIG_MIPS_GENERIC_PCI),y)
+obj-y				+= pci-generic.o
+else
+obj-y				+= pci-legacy.o
+endif
+
 #
 # PCI bus host bridge specific code
 #
diff --git a/arch/mips/pci/pci-generic.c b/arch/mips/pci/pci-generic.c
new file mode 100644
index 0000000..f20adc0
--- /dev/null
+++ b/arch/mips/pci/pci-generic.c
@@ -0,0 +1,138 @@
+/*
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle (ralf@linux-mips.org)
+ */
+
+#include <linux/pci.h>
+
+int __weak pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct pci_sys_data *sysdata = dev->sysdata;
+	struct pci_controller *ctl = sysdata_to_hose(sysdata);
+
+	if (!ctl->map_irq)
+		return -1;
+
+	return ctl->map_irq(dev, slot, pin);
+}
+
+void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
+{
+	struct pci_controller *ctl;
+	struct resource_entry *window;
+	struct resource **ctl_res;
+	int i, ret, next_busnr = 0;
+
+	for (i = 0; i < hw->nr_controllers; i++) {
+		ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
+		if (!ctl) {
+			pr_err("%s: unable to allocate pci_controller\n",
+			       __func__);
+			continue;
+		}
+
+		ctl->pci_ops = hw->ops;
+		ctl->align_resource = hw->align_resource;
+		ctl->map_irq = hw->map_irq;
+
+		INIT_LIST_HEAD(&ctl->sysdata.resources);
+
+		if (hw->private_data)
+			ctl->sysdata.private_data = hw->private_data[i];
+
+		ctl->sysdata.busnr = next_busnr;
+#ifdef CONFIG_PCI_MSI
+		ctl->sysdata.msi_ctrl = hw->msi_ctrl;
+#endif
+
+		if (hw->preinit)
+			hw->preinit();
+
+		ret = hw->setup(i, &ctl->sysdata);
+		if (ret < 0) {
+			pr_err("%s: unable to setup controller: %d\n",
+			       __func__, ret);
+			kfree(ctl);
+			continue;
+		}
+
+		resource_list_for_each_entry(window, &ctl->sysdata.resources) {
+			switch (resource_type(window->res)) {
+			case IORESOURCE_IO:
+				ctl_res = &ctl->io_resource;
+				break;
+
+			case IORESOURCE_MEM:
+				ctl_res = &ctl->mem_resource;
+				break;
+
+			default:
+				ctl_res = NULL;
+			}
+
+			if (!ctl_res)
+				continue;
+
+			if (*ctl_res) {
+				pr_warn("%s: multiple resources of type 0x%lx\n",
+					__func__, resource_type(window->res));
+				continue;
+			}
+
+			*ctl_res = window->res;
+		}
+
+		if (hw->scan)
+			ctl->bus = hw->scan(i, &ctl->sysdata);
+		else
+			ctl->bus = pci_scan_root_bus(parent,
+					ctl->sysdata.busnr,
+					hw->ops, &ctl->sysdata,
+					&ctl->sysdata.resources);
+
+		add_pci_controller(ctl);
+
+		if (hw->postinit)
+			hw->postinit();
+
+		pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
+
+		if (ctl->bus) {
+			if (!pci_has_flag(PCI_PROBE_ONLY)) {
+				pci_bus_size_bridges(ctl->bus);
+				pci_bus_assign_resources(ctl->bus);
+			}
+
+			pci_bus_add_devices(ctl->bus);
+			next_busnr = ctl->bus->busn_res.end + 1;
+		}
+	}
+}
+
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+	pci_read_bridge_bases(bus);
+}
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+	if (pci_has_flag(PCI_PROBE_ONLY))
+		return 0;
+
+	return pci_enable_resources(dev, mask);
+}
+
+#ifdef CONFIG_PCI_MSI
+struct msi_controller *pcibios_msi_controller(struct pci_dev *dev)
+{
+	struct pci_sys_data *sysdata = dev->sysdata;
+
+	return sysdata->msi_ctrl;
+}
+#endif
diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c
new file mode 100644
index 0000000..cf76a08
--- /dev/null
+++ b/arch/mips/pci/pci-legacy.c
@@ -0,0 +1,232 @@
+/*
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle (ralf@linux-mips.org)
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/of_address.h>
+#include <linux/pci.h>
+
+#include <asm/cpu-info.h>
+
+static int pci_initialized;
+static DEFINE_MUTEX(pci_scan_mutex);
+
+static void pcibios_scanbus(struct pci_controller *hose)
+{
+	static int next_busno;
+	static int need_domain_info;
+	LIST_HEAD(resources);
+	struct pci_bus *bus;
+
+	if (!hose->iommu)
+		PCI_DMA_BUS_IS_PHYS = 1;
+
+	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
+		next_busno = (*hose->get_busno)();
+
+	hose->sysdata.busnr = next_busno;
+
+	pci_add_resource_offset(&resources,
+				hose->mem_resource, hose->mem_offset);
+	pci_add_resource_offset(&resources,
+				hose->io_resource, hose->io_offset);
+	pci_add_resource_offset(&resources,
+				hose->busn_resource, hose->busn_offset);
+	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, &hose->sysdata,
+				&resources);
+	hose->bus = bus;
+
+	need_domain_info = need_domain_info || hose->index;
+	hose->need_domain_info = need_domain_info;
+
+	if (!bus) {
+		pci_free_resource_list(&resources);
+		return;
+	}
+
+	next_busno = bus->busn_res.end + 1;
+	/* Don't allow 8-bit bus number overflow inside the hose -
+	   reserve some space for bridges. */
+	if (next_busno > 224) {
+		next_busno = 0;
+		need_domain_info = 1;
+	}
+
+	if (!pci_has_flag(PCI_PROBE_ONLY)) {
+		pci_bus_size_bridges(bus);
+		pci_bus_assign_resources(bus);
+	}
+	pci_bus_add_devices(bus);
+}
+
+#ifdef CONFIG_OF
+void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
+{
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
+
+	pr_info("PCI host bridge %s ranges:\n", node->full_name);
+	hose->of_node = node;
+
+	if (of_pci_range_parser_init(&parser, node))
+		return;
+
+	for_each_of_pci_range(&parser, &range) {
+		struct resource *res = NULL;
+
+		switch (range.flags & IORESOURCE_TYPE_BITS) {
+		case IORESOURCE_IO:
+			pr_info("  IO 0x%016llx..0x%016llx\n",
+				range.cpu_addr,
+				range.cpu_addr + range.size - 1);
+			hose->io_map_base =
+				(unsigned long)ioremap(range.cpu_addr,
+						       range.size);
+			res = hose->io_resource;
+			break;
+		case IORESOURCE_MEM:
+			pr_info(" MEM 0x%016llx..0x%016llx\n",
+				range.cpu_addr,
+				range.cpu_addr + range.size - 1);
+			res = hose->mem_resource;
+			break;
+		}
+		if (res != NULL)
+			of_pci_range_to_resource(&range, node, res);
+	}
+}
+
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+	struct pci_controller *hose = sysdata_to_hose(bus->sysdata);
+
+	return of_node_get(hose->of_node);
+}
+#endif
+
+void register_pci_controller(struct pci_controller *hose)
+{
+	struct resource *parent;
+
+	parent = hose->mem_resource->parent;
+	if (!parent)
+		parent = &iomem_resource;
+
+	if (request_resource(parent, hose->mem_resource) < 0)
+		goto out;
+
+	parent = hose->io_resource->parent;
+	if (!parent)
+		parent = &ioport_resource;
+
+	if (request_resource(parent, hose->io_resource) < 0) {
+		release_resource(hose->mem_resource);
+		goto out;
+	}
+
+	add_pci_controller(hose);
+
+	/*
+	 * Do not panic here but later - this might happen before console init.
+	 */
+	if (!hose->io_map_base) {
+		printk(KERN_WARNING
+		       "registering PCI controller with io_map_base unset\n");
+	}
+
+	/*
+	 * Scan the bus if it is register after the PCI subsystem
+	 * initialization.
+	 */
+	if (pci_initialized) {
+		mutex_lock(&pci_scan_mutex);
+		pcibios_scanbus(hose);
+		mutex_unlock(&pci_scan_mutex);
+	}
+
+	return;
+
+out:
+	printk(KERN_WARNING
+	       "Skipping PCI bus scan due to resource conflict\n");
+}
+
+static int __init pcibios_init(void)
+{
+	struct pci_controller *hose;
+
+	/* Scan all of the recorded PCI controllers.  */
+	for (hose = hose_head; hose; hose = hose->next)
+		pcibios_scanbus(hose);
+
+	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
+
+	pci_initialized = 1;
+
+	return 0;
+}
+subsys_initcall(pcibios_init);
+
+static int pcibios_enable_resources(struct pci_dev *dev, int mask)
+{
+	u16 cmd, old_cmd;
+	int idx;
+	struct resource *r;
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	old_cmd = cmd;
+	for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
+		/* Only set up the requested stuff */
+		if (!(mask & (1<<idx)))
+			continue;
+
+		r = &dev->resource[idx];
+		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
+			continue;
+		if ((idx == PCI_ROM_RESOURCE) &&
+				(!(r->flags & IORESOURCE_ROM_ENABLE)))
+			continue;
+		if (!r->start && r->end) {
+			printk(KERN_ERR "PCI: Device %s not available "
+			       "because of resource collisions\n",
+			       pci_name(dev));
+			return -EINVAL;
+		}
+		if (r->flags & IORESOURCE_IO)
+			cmd |= PCI_COMMAND_IO;
+		if (r->flags & IORESOURCE_MEM)
+			cmd |= PCI_COMMAND_MEMORY;
+	}
+	if (cmd != old_cmd) {
+		printk("PCI: Enabling device %s (%04x -> %04x)\n",
+		       pci_name(dev), old_cmd, cmd);
+		pci_write_config_word(dev, PCI_COMMAND, cmd);
+	}
+	return 0;
+}
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+	int err;
+
+	err = pcibios_enable_resources(dev, mask);
+	return err ?: pcibios_plat_dev_init(dev);
+}
+
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+	struct pci_dev *dev = bus->self;
+
+	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
+	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+		pci_read_bridge_bases(bus);
+	}
+}
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index b8a0bf5..18ea99b 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -29,13 +29,12 @@
  * The PCI controller list.
  */
 
-static struct pci_controller *hose_head, **hose_tail = &hose_head;
+struct pci_controller *hose_head;
+static struct pci_controller **hose_tail = &hose_head;
 
 unsigned long PCIBIOS_MIN_IO;
 unsigned long PCIBIOS_MIN_MEM;
 
-static int pci_initialized;
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
@@ -54,7 +53,7 @@ pcibios_align_resource(void *data, const struct resource *res,
 		       resource_size_t size, resource_size_t align)
 {
 	struct pci_dev *dev = data;
-	struct pci_controller *hose = dev->sysdata;
+	struct pci_controller *hose = sysdata_to_hose(dev->sysdata);
 	resource_size_t start = res->start;
 
 	if (res->flags & IORESOURCE_IO) {
@@ -73,151 +72,19 @@ pcibios_align_resource(void *data, const struct resource *res,
 			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
 	}
 
-	return start;
-}
-
-static void pcibios_scanbus(struct pci_controller *hose)
-{
-	static int next_busno;
-	static int need_domain_info;
-	LIST_HEAD(resources);
-	struct pci_bus *bus;
-
-	if (!hose->iommu)
-		PCI_DMA_BUS_IS_PHYS = 1;
-
-	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
-		next_busno = (*hose->get_busno)();
-
-	pci_add_resource_offset(&resources,
-				hose->mem_resource, hose->mem_offset);
-	pci_add_resource_offset(&resources,
-				hose->io_resource, hose->io_offset);
-	pci_add_resource_offset(&resources,
-				hose->busn_resource, hose->busn_offset);
-	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
-				&resources);
-	hose->bus = bus;
-
-	need_domain_info = need_domain_info || hose->index;
-	hose->need_domain_info = need_domain_info;
-
-	if (!bus) {
-		pci_free_resource_list(&resources);
-		return;
-	}
-
-	next_busno = bus->busn_res.end + 1;
-	/* Don't allow 8-bit bus number overflow inside the hose -
-	   reserve some space for bridges. */
-	if (next_busno > 224) {
-		next_busno = 0;
-		need_domain_info = 1;
-	}
-
-	if (!pci_has_flag(PCI_PROBE_ONLY)) {
-		pci_bus_size_bridges(bus);
-		pci_bus_assign_resources(bus);
-	}
-	pci_bus_add_devices(bus);
-}
-
-#ifdef CONFIG_OF
-void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
-{
-	struct of_pci_range range;
-	struct of_pci_range_parser parser;
-
-	pr_info("PCI host bridge %s ranges:\n", node->full_name);
-	hose->of_node = node;
-
-	if (of_pci_range_parser_init(&parser, node))
-		return;
-
-	for_each_of_pci_range(&parser, &range) {
-		struct resource *res = NULL;
-
-		switch (range.flags & IORESOURCE_TYPE_BITS) {
-		case IORESOURCE_IO:
-			pr_info("  IO 0x%016llx..0x%016llx\n",
-				range.cpu_addr,
-				range.cpu_addr + range.size - 1);
-			hose->io_map_base =
-				(unsigned long)ioremap(range.cpu_addr,
-						       range.size);
-			res = hose->io_resource;
-			break;
-		case IORESOURCE_MEM:
-			pr_info(" MEM 0x%016llx..0x%016llx\n",
-				range.cpu_addr,
-				range.cpu_addr + range.size - 1);
-			res = hose->mem_resource;
-			break;
-		}
-		if (res != NULL)
-			of_pci_range_to_resource(&range, node, res);
-	}
-}
-
-struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
-{
-	struct pci_controller *hose = bus->sysdata;
+	if (hose->align_resource)
+		return hose->align_resource(dev, res, start, size, align);
 
-	return of_node_get(hose->of_node);
+	return start;
 }
-#endif
 
-static DEFINE_MUTEX(pci_scan_mutex);
-
-void register_pci_controller(struct pci_controller *hose)
+void add_pci_controller(struct pci_controller *hose)
 {
-	struct resource *parent;
-
-	parent = hose->mem_resource->parent;
-	if (!parent)
-		parent = &iomem_resource;
-
-	if (request_resource(parent, hose->mem_resource) < 0)
-		goto out;
-
-	parent = hose->io_resource->parent;
-	if (!parent)
-		parent = &ioport_resource;
-
-	if (request_resource(parent, hose->io_resource) < 0) {
-		release_resource(hose->mem_resource);
-		goto out;
-	}
-
 	*hose_tail = hose;
 	hose_tail = &hose->next;
-
-	/*
-	 * Do not panic here but later - this might happen before console init.
-	 */
-	if (!hose->io_map_base) {
-		printk(KERN_WARNING
-		       "registering PCI controller with io_map_base unset\n");
-	}
-
-	/*
-	 * Scan the bus if it is register after the PCI subsystem
-	 * initialization.
-	 */
-	if (pci_initialized) {
-		mutex_lock(&pci_scan_mutex);
-		pcibios_scanbus(hose);
-		mutex_unlock(&pci_scan_mutex);
-	}
-
-	return;
-
-out:
-	printk(KERN_WARNING
-	       "Skipping PCI bus scan due to resource conflict\n");
 }
 
-static void __init pcibios_set_cache_line_size(void)
+static int __init pcibios_set_cache_line_size(void)
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
 	unsigned int lsize;
@@ -235,90 +102,15 @@ static void __init pcibios_set_cache_line_size(void)
 	pci_dfl_cache_line_size = lsize >> 2;
 
 	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
-}
-
-static int __init pcibios_init(void)
-{
-	struct pci_controller *hose;
-
-	pcibios_set_cache_line_size();
-
-	/* Scan all of the recorded PCI controllers.  */
-	for (hose = hose_head; hose; hose = hose->next)
-		pcibios_scanbus(hose);
-
-	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
-
-	pci_initialized = 1;
-
-	return 0;
-}
-
-subsys_initcall(pcibios_init);
-
-static int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
-	u16 cmd, old_cmd;
-	int idx;
-	struct resource *r;
-
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	old_cmd = cmd;
-	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
-		/* Only set up the requested stuff */
-		if (!(mask & (1<<idx)))
-			continue;
-
-		r = &dev->resource[idx];
-		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
-			continue;
-		if ((idx == PCI_ROM_RESOURCE) &&
-				(!(r->flags & IORESOURCE_ROM_ENABLE)))
-			continue;
-		if (!r->start && r->end) {
-			printk(KERN_ERR "PCI: Device %s not available "
-			       "because of resource collisions\n",
-			       pci_name(dev));
-			return -EINVAL;
-		}
-		if (r->flags & IORESOURCE_IO)
-			cmd |= PCI_COMMAND_IO;
-		if (r->flags & IORESOURCE_MEM)
-			cmd |= PCI_COMMAND_MEMORY;
-	}
-	if (cmd != old_cmd) {
-		printk("PCI: Enabling device %s (%04x -> %04x)\n",
-		       pci_name(dev), old_cmd, cmd);
-		pci_write_config_word(dev, PCI_COMMAND, cmd);
-	}
 	return 0;
 }
+arch_initcall(pcibios_set_cache_line_size);
 
 unsigned int pcibios_assign_all_busses(void)
 {
 	return 1;
 }
 
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-	int err;
-
-	if ((err = pcibios_enable_resources(dev, mask)) < 0)
-		return err;
-
-	return pcibios_plat_dev_init(dev);
-}
-
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-	struct pci_dev *dev = bus->self;
-
-	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
-	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
-		pci_read_bridge_bases(bus);
-	}
-}
-
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 
-- 
2.6.2

[PATCH 05/28] PCI: xilinx: keep references to both IRQ domains

[Paul Burton]

pcie-xilinx creates 2 IRQ domains when built with MSI support: one for
MSI interrupts & one for legacy INTx interrupts. However, it only kept a
reference to the MSI IRQ domain. This means that any INTx interrupts
that may occur would be mapped using the wrong domain, and that only the
MSI IRQ domain would be removed along with the driver. Track both IRQ
domains & clean up both as appropriate.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/pcie-xilinx.c | 58 ++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 30 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3c7a0d5..c412a37 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -105,6 +105,7 @@
  * @root_busno: Root Bus number
  * @dev: Device pointer
  * @irq_domain: IRQ domain pointer
+ * @msi_irq_domain: MSI IRQ domain pointer
  * @bus_range: Bus range
  * @resources: Bus Resources
  */
@@ -115,6 +116,7 @@ struct xilinx_pcie_port {
 	u8 root_busno;
 	struct device *dev;
 	struct irq_domain *irq_domain;
+	struct irq_domain *msi_irq_domain;
 	struct resource bus_range;
 	struct list_head resources;
 };
@@ -291,7 +293,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
 	if (hwirq < 0)
 		return hwirq;
 
-	irq = irq_create_mapping(port->irq_domain, hwirq);
+	irq = irq_create_mapping(port->msi_irq_domain, hwirq);
 	if (!irq)
 		return -EINVAL;
 
@@ -517,31 +519,21 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 
 /**
  * xilinx_pcie_free_irq_domain - Free IRQ domain
- * @port: PCIe port information
+ * @domain: the IRQ domain to free
+ * @nr: the number of IRQs in the domain
  */
-static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
+static void xilinx_pcie_free_irq_domain(struct irq_domain *domain, int nr)
 {
 	int i;
-	u32 irq, num_irqs;
-
-	/* Free IRQ Domain */
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-
-		free_pages(port->msi_pages, 0);
-
-		num_irqs = XILINX_NUM_MSI_IRQS;
-	} else {
-		/* INTx */
-		num_irqs = 4;
-	}
+	u32 irq;
 
-	for (i = 0; i < num_irqs; i++) {
-		irq = irq_find_mapping(port->irq_domain, i);
+	for (i = 0; i < nr; i++) {
+		irq = irq_find_mapping(domain, i);
 		if (irq > 0)
 			irq_dispose_mapping(irq);
 	}
 
-	irq_domain_remove(port->irq_domain);
+	irq_domain_remove(domain);
 }
 
 /**
@@ -571,20 +563,20 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
 		return PTR_ERR(port->irq_domain);
 	}
 
-	/* Setup MSI */
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		port->irq_domain = irq_domain_add_linear(node,
-							 XILINX_NUM_MSI_IRQS,
-							 &msi_domain_ops,
-							 &xilinx_pcie_msi_chip);
-		if (!port->irq_domain) {
-			dev_err(dev, "Failed to get a MSI IRQ domain\n");
-			return PTR_ERR(port->irq_domain);
-		}
+	if (!IS_ENABLED(CONFIG_PCI_MSI))
+		return 0;
 
-		xilinx_pcie_enable_msi(port);
+	/* Setup MSI */
+	port->msi_irq_domain = irq_domain_add_linear(node,
+						     XILINX_NUM_MSI_IRQS,
+						     &msi_domain_ops,
+						     &xilinx_pcie_msi_chip);
+	if (!port->msi_irq_domain) {
+		dev_err(dev, "Failed to get a MSI IRQ domain\n");
+		return PTR_ERR(port->msi_irq_domain);
 	}
 
+	xilinx_pcie_enable_msi(port);
 	return 0;
 }
 
@@ -868,7 +860,13 @@ static int xilinx_pcie_remove(struct platform_device *pdev)
 {
 	struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
 
-	xilinx_pcie_free_irq_domain(port);
+	xilinx_pcie_free_irq_domain(port->irq_domain, 4);
+
+	if (config_enabled(CONFIG_MSI)) {
+		free_pages(port->msi_pages, 0);
+		xilinx_pcie_free_irq_domain(port->msi_irq_domain,
+					    XILINX_NUM_MSI_IRQS);
+	}
 
 	return 0;
 }
-- 
2.6.2

Re: [PATCH 05/28] PCI: xilinx: keep references to both IRQ domains

[Bjorn Helgaas]

Hi Paul,

Please capitalize the first word of your PCI changelog subjects.

On Mon, Nov 30, 2015 at 04:21:30PM +0000, Paul Burton wrote:
> pcie-xilinx creates 2 IRQ domains when built with MSI support: one for
> MSI interrupts & one for legacy INTx interrupts. However, it only kept a
> reference to the MSI IRQ domain. This means that any INTx interrupts
> that may occur would be mapped using the wrong domain, and that only the
> MSI IRQ domain would be removed along with the driver. Track both IRQ
> domains & clean up both as appropriate.

It looks like this fixes a problem in the original commit 8961def56845
("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver"), which
appeared in v3.18.  Does this need a stable backport tag?

It sounds like any device using INTx just won't work?  From later
patches, I surmise that this series might be related to using Xilinx
in a new MIPS Boston board.  If that's the case, and pre-v4.5 kernels
don't support that board anyway, a stable backport might not be
needed.  It *does* fix a leak even if you don't need INTx, but that
seems minor and probably not worth a stable backport all by itself.

I probably *would* add a 'Fixes: 8961def56845 ("PCI: xilinx: Add
Xilinx AXI PCIe Host Bridge IP driver")' line to leave breadcrumbs for
people backporting things.

This seems to be part of a larger series -- can these PCI patches go
through my tree, or do they all need to go together because of
dependencies on the rest of the series?

They all need acks from Michal, of course.

> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
> 
>  drivers/pci/host/pcie-xilinx.c | 58 ++++++++++++++++++++----------------------
>  1 file changed, 28 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
> index 3c7a0d5..c412a37 100644
> --- a/drivers/pci/host/pcie-xilinx.c
> +++ b/drivers/pci/host/pcie-xilinx.c
> @@ -105,6 +105,7 @@
>   * @root_busno: Root Bus number
>   * @dev: Device pointer
>   * @irq_domain: IRQ domain pointer
> + * @msi_irq_domain: MSI IRQ domain pointer
>   * @bus_range: Bus range
>   * @resources: Bus Resources
>   */
> @@ -115,6 +116,7 @@ struct xilinx_pcie_port {
>  	u8 root_busno;
>  	struct device *dev;
>  	struct irq_domain *irq_domain;
> +	struct irq_domain *msi_irq_domain;
>  	struct resource bus_range;
>  	struct list_head resources;
>  };
> @@ -291,7 +293,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
>  	if (hwirq < 0)
>  		return hwirq;
>  
> -	irq = irq_create_mapping(port->irq_domain, hwirq);
> +	irq = irq_create_mapping(port->msi_irq_domain, hwirq);
>  	if (!irq)
>  		return -EINVAL;
>  
> @@ -517,31 +519,21 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
>  
>  /**
>   * xilinx_pcie_free_irq_domain - Free IRQ domain
> - * @port: PCIe port information
> + * @domain: the IRQ domain to free
> + * @nr: the number of IRQs in the domain
>   */
> -static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
> +static void xilinx_pcie_free_irq_domain(struct irq_domain *domain, int nr)
>  {
>  	int i;
> -	u32 irq, num_irqs;
> -
> -	/* Free IRQ Domain */
> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> -
> -		free_pages(port->msi_pages, 0);
> -
> -		num_irqs = XILINX_NUM_MSI_IRQS;
> -	} else {
> -		/* INTx */
> -		num_irqs = 4;
> -	}
> +	u32 irq;
>  
> -	for (i = 0; i < num_irqs; i++) {
> -		irq = irq_find_mapping(port->irq_domain, i);
> +	for (i = 0; i < nr; i++) {
> +		irq = irq_find_mapping(domain, i);
>  		if (irq > 0)
>  			irq_dispose_mapping(irq);
>  	}
>  
> -	irq_domain_remove(port->irq_domain);
> +	irq_domain_remove(domain);
>  }
>  
>  /**
> @@ -571,20 +563,20 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
>  		return PTR_ERR(port->irq_domain);
>  	}
>  
> -	/* Setup MSI */
> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> -		port->irq_domain = irq_domain_add_linear(node,
> -							 XILINX_NUM_MSI_IRQS,
> -							 &msi_domain_ops,
> -							 &xilinx_pcie_msi_chip);
> -		if (!port->irq_domain) {
> -			dev_err(dev, "Failed to get a MSI IRQ domain\n");
> -			return PTR_ERR(port->irq_domain);
> -		}
> +	if (!IS_ENABLED(CONFIG_PCI_MSI))
> +		return 0;
>  
> -		xilinx_pcie_enable_msi(port);
> +	/* Setup MSI */
> +	port->msi_irq_domain = irq_domain_add_linear(node,
> +						     XILINX_NUM_MSI_IRQS,
> +						     &msi_domain_ops,
> +						     &xilinx_pcie_msi_chip);
> +	if (!port->msi_irq_domain) {
> +		dev_err(dev, "Failed to get a MSI IRQ domain\n");
> +		return PTR_ERR(port->msi_irq_domain);
>  	}
>  
> +	xilinx_pcie_enable_msi(port);
>  	return 0;
>  }
>  
> @@ -868,7 +860,13 @@ static int xilinx_pcie_remove(struct platform_device *pdev)
>  {
>  	struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
>  
> -	xilinx_pcie_free_irq_domain(port);
> +	xilinx_pcie_free_irq_domain(port->irq_domain, 4);
> +
> +	if (config_enabled(CONFIG_MSI)) {
> +		free_pages(port->msi_pages, 0);
> +		xilinx_pcie_free_irq_domain(port->msi_irq_domain,
> +					    XILINX_NUM_MSI_IRQS);
> +	}
>  
>  	return 0;
>  }
> -- 
> 2.6.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 06/28] PCI: xilinx: unify INTx & MSI interrupt FIFO decode

[Paul Burton]

When decoding either an INTx or MSI interrupt, the driver has no way to
know which it will pull out of the interrupt FIFO. If both were pending
then this would lead to either the interrupt being handled incorrectly
(MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by
MSI path). Unify the reading of the interrupt FIFO & act according to
the type of interrupt actually read.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/pcie-xilinx.c | 45 +++++++++++-------------------------------
 1 file changed, 12 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index c412a37..c6fe273 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = {
 static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 {
 	struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
-	u32 val, mask, status, msi_data;
+	u32 val, mask, status;
 
 	/* Read interrupt decode and mask registers */
 	val = pcie_read(port, XILINX_PCIE_REG_IDR);
@@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 		xilinx_pcie_clear_err_interrupts(port);
 	}
 
-	if (status & XILINX_PCIE_INTR_INTX) {
-		/* INTx interrupt received */
+	if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
+		/* Interrupt received */
 		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
 
 		/* Check whether interrupt valid */
@@ -447,41 +447,20 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 			return IRQ_HANDLED;
 		}
 
-		if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
-			/* Clear interrupt FIFO register 1 */
-			pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
-				   XILINX_PCIE_REG_RPIFR1);
-
-			/* Handle INTx Interrupt */
+		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
+			irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
+				XILINX_PCIE_RPIFR2_MSG_DATA;
+		} else {
 			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
 				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
-			generic_handle_irq(irq_find_mapping(port->irq_domain,
-							    val));
+			irq = irq_find_mapping(port->irq_domain, val);
 		}
-	}
 
-	if (status & XILINX_PCIE_INTR_MSI) {
-		/* MSI Interrupt */
-		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
+		/* Clear interrupt FIFO register 1 */
+		pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+			   XILINX_PCIE_REG_RPIFR1);
 
-		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
-			dev_warn(port->dev, "RP Intr FIFO1 read error\n");
-			return IRQ_HANDLED;
-		}
-
-		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
-			msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
-				   XILINX_PCIE_RPIFR2_MSG_DATA;
-
-			/* Clear interrupt FIFO register 1 */
-			pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
-				   XILINX_PCIE_REG_RPIFR1);
-
-			if (IS_ENABLED(CONFIG_PCI_MSI)) {
-				/* Handle MSI Interrupt */
-				generic_handle_irq(msi_data);
-			}
-		}
+		generic_handle_irq(irq);
 	}
 
 	if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
-- 
2.6.2

[PATCH 07/28] PCI: xilinx: always clear interrupt decode register

[Paul Burton]

If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO
then xilinx_pcie_intr_handler will print a warning & skip further
processing. However it did not clear the interrupt in the decode
register, so the same INTX or MSI interrupt would trigger again
immediately even though the FIFO is still empty. Clear the interrupt in
the decode register to avoid that situation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/pcie-xilinx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index c6fe273..3058a57 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 		/* Check whether interrupt valid */
 		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
 			dev_warn(port->dev, "RP Intr FIFO1 read error\n");
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
@@ -490,6 +490,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 	if (status & XILINX_PCIE_INTR_MST_ERRP)
 		dev_warn(port->dev, "Master error poison\n");
 
+out:
 	/* Clear the Interrupt Decode register */
 	pcie_write(port, status, XILINX_PCIE_REG_IDR);
 
-- 
2.6.2

[PATCH 08/28] PCI: xilinx: fix INTX irq dispatch

[Paul Burton]

The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This
matches what the hardware reports from the interrupt FIFO exactly, but
xilinx_pcie_intr_handler was adding 1 to that value to convert to the
range 1 to 4. Stop adding 1, such that all of INTA through to INTD fall
within the range of the IRQ domain.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/pcie-xilinx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3058a57..ac9da72 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -451,8 +451,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 			irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
 				XILINX_PCIE_RPIFR2_MSG_DATA;
 		} else {
-			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+			val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+				XILINX_PCIE_RPIFR1_INTR_SHIFT;
 			irq = irq_find_mapping(port->irq_domain, val);
 		}
 
-- 
2.6.2

[PATCH 09/28] PCI: xilinx: allow build on MIPS platforms

[Paul Burton]

Allow the xilinx-pcie driver to be built on MIPS platforms. This will be
used on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..a22e6c7 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -81,7 +81,7 @@ config PCI_KEYSTONE
 
 config PCIE_XILINX
 	bool "Xilinx AXI PCIe host bridge support"
-	depends on ARCH_ZYNQ
+	depends on ARCH_ZYNQ || MIPS
 	help
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
-- 
2.6.2

[PATCH 10/28] misc: pch_phub: allow build on MIPS platforms

[Paul Burton]

Allow the pch_phub driver to be build on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/misc/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 22892c7..cad146b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -469,7 +469,7 @@ config BMP085_SPI
 config PCH_PHUB
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) PHUB"
 	select GENERIC_NET_UTILS
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	help
 	  This driver is for PCH(Platform controller Hub) PHUB(Packet Hub) of
 	  Intel Topcliff which is an IOH(Input/Output Hub) for x86 embedded
-- 
2.6.2

[PATCH 11/28] dmaengine: pch_dma: allow build on MIPS platforms

[Paul Burton]

Allow the pch_dma driver to be built on MIPS platforms, in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/dma/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index e6cd1a3..0d2896c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -376,7 +376,7 @@ config NBPFAXI_DMA
 
 config PCH_DMA
 	tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	select DMA_ENGINE
 	help
 	  Enable support for Intel EG20T PCH DMA engine.
-- 
2.6.2

Re: [PATCH 11/28] dmaengine: pch_dma: allow build on MIPS platforms

[Vinod Koul]

On Mon, Nov 30, 2015 at 04:21:36PM +0000, Paul Burton wrote:
> Allow the pch_dma driver to be built on MIPS platforms, in preparation
> for use on the MIPS Boston board.

Acked-by: Vinod Koul <vinod.koul@intel.com>


-- 
~Vinod

[PATCH 12/28] gpio: pch: allow build on MIPS platforms

[Paul Burton]

Allow the pch_gpio driver to be built for MIPS platforms, in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/gpio/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b18bea0..19d7dd7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -952,7 +952,7 @@ config GPIO_ML_IOH
 
 config GPIO_PCH
 	tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7223/ML7831) GPIO"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	select GENERIC_IRQ_CHIP
 	help
 	  This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff
-- 
2.6.2

Re: [PATCH 12/28] gpio: pch: allow build on MIPS platforms

[Linus Walleij]

On Mon, Nov 30, 2015 at 5:21 PM, Paul Burton <paul.burton@imgtec.com> wrote:

> Allow the pch_gpio driver to be built for MIPS platforms, in preparation
> for use on the MIPS Boston board.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Patch applied to the GPIO tree.

All GPIO patches should go separately to the GPIO tree, especially
this merge window as I'm doing refactorings.

Yours,
Linus Walleij

[PATCH 13/28] gpio: pch: allow use from device tree

[Paul Burton]

Allow GPIOs from the gpio-pch driver to be referenced from device tree
by simply setting the struct gpio_chip of_node pointer to that of the
struct pci_dev.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/gpio/gpio-pch.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index 34ed176..56c9be4 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -394,6 +394,7 @@ static int pch_gpio_probe(struct pci_dev *pdev,
 	pci_set_drvdata(pdev, chip);
 	spin_lock_init(&chip->spinlock);
 	pch_gpio_setup(chip);
+	chip->gpio.of_node = pdev->dev.of_node;
 	ret = gpiochip_add(&chip->gpio);
 	if (ret) {
 		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
-- 
2.6.2

Re: [PATCH 13/28] gpio: pch: allow use from device tree

[Linus Walleij]

On Mon, Nov 30, 2015 at 5:21 PM, Paul Burton <paul.burton@imgtec.com> wrote:

> Allow GPIOs from the gpio-pch driver to be referenced from device tree
> by simply setting the struct gpio_chip of_node pointer to that of the
> struct pci_dev.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Patch applied.

Yours,
Linus Walleij

[PATCH 14/28] i2c: eg20t: allow build on MIPS platforms

[Paul Burton]

Allow the eg20t I2C driver to be built for MIPS platforms, in
preparation for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/i2c/busses/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 7b0aa82..69c46fe 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -516,7 +516,7 @@ config I2C_EFM32
 
 config I2C_EG20T
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	help
 	  This driver is for PCH(Platform controller Hub) I2C of EG20T which
 	  is an IOH(Input/Output Hub) for x86 embedded processor.
-- 
2.6.2

Re: [PATCH 14/28] i2c: eg20t: allow build on MIPS platforms

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 269 bytes --]

On Mon, Nov 30, 2015 at 04:21:39PM +0000, Paul Burton wrote:
> Allow the eg20t I2C driver to be built for MIPS platforms, in
> preparation for use on the MIPS Boston board.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Applied to for-next, thanks!


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[PATCH 15/28] i2c: eg20t: set i2c_adapter->dev.of_node

[Paul Burton]

Set the I2C adapter devices of_node to that of the PCI device, such that
I2C clients may be instantiated via device tree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/i2c/busses/i2c-eg20t.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 76e699f..137125b 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -795,6 +795,7 @@ static int pch_i2c_probe(struct pci_dev *pdev,
 		/* base_addr + offset; */
 		adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 
+		pch_adap->dev.of_node = pdev->dev.of_node;
 		pch_adap->dev.parent = &pdev->dev;
 
 		pch_i2c_init(&adap_info->pch_data[i]);
-- 
2.6.2

Re: [PATCH 15/28] i2c: eg20t: set i2c_adapter->dev.of_node

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 283 bytes --]

On Mon, Nov 30, 2015 at 04:21:40PM +0000, Paul Burton wrote:
> Set the I2C adapter devices of_node to that of the PCI device, such that
> I2C clients may be instantiated via device tree.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Applied to for-next, thanks!


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[PATCH 16/28] rtc: m41t80: add devicetree probe support

[Paul Burton]

Allow the m41t80 RTC driver to be probed via devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/rtc/rtc-m41t80.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c
index a82937e..d3b29fc 100644
--- a/drivers/rtc/rtc-m41t80.c
+++ b/drivers/rtc/rtc-m41t80.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/rtc.h>
 #include <linux/slab.h>
 #include <linux/mutex.h>
@@ -85,6 +86,14 @@ static const struct i2c_device_id m41t80_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, m41t80_id);
 
+#ifdef CONFIG_OF
+static const struct of_device_id m41t80_of_match[] = {
+	{ .compatible = "st,m41t81s", .name = "m41t81s" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, m41t80_of_match);
+#endif
+
 struct m41t80_data {
 	u8 features;
 	struct rtc_device *rtc;
@@ -637,6 +646,22 @@ static int m41t80_probe(struct i2c_client *client,
 	struct rtc_device *rtc = NULL;
 	struct rtc_time tm;
 	struct m41t80_data *clientdata = NULL;
+	const struct of_device_id *of_id;
+
+	if (!id && client->dev.of_node) {
+		of_id = of_match_node(of_match_ptr(m41t80_of_match),
+				      client->dev.of_node);
+		for (id = m41t80_id; id->name[0]; id++) {
+			if (strcmp(of_id->name, id->name) == 0)
+				break;
+		}
+		if (!id->name[0])
+			id = NULL;
+	}
+	if (!id) {
+		dev_err(&client->dev, "No i2c_device_id found\n");
+		return -EINVAL;
+	}
 
 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C
 				     | I2C_FUNC_SMBUS_BYTE_DATA))
@@ -728,6 +753,7 @@ static int m41t80_remove(struct i2c_client *client)
 static struct i2c_driver m41t80_driver = {
 	.driver = {
 		.name = "rtc-m41t80",
+		.of_match_table = of_match_ptr(m41t80_of_match),
 	},
 	.probe = m41t80_probe,
 	.remove = m41t80_remove,
-- 
2.6.2

Re: [PATCH 16/28] rtc: m41t80: add devicetree probe support

[Alexandre Belloni]

Hi,

On 30/11/2015 at 16:21:41 +0000, Paul Burton wrote :
> Allow the m41t80 RTC driver to be probed via devicetree.
> 

This patch is probably unnecessary as "m41t81s" is already part of
m41t80_id[] and will be matched with "st,m41t81s" by the i2c core. See
http://lxr.free-electrons.com/source/drivers/i2c/i2c-core.c#L700

I actually don't know how to get people to stop submitting that kind of
patches :)

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 17/28] spi: topcliff-pch: allow build for MIPS platforms

[Paul Burton]

Allow the topcliff-pch driver to be built for MIPS platforms, in
preparation for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8b9c2a3..7c78d52 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -585,7 +585,7 @@ config SPI_TEGRA20_SLINK
 
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	help
 	  SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
 	  used in some x86 embedded processors.
-- 
2.6.2

[PATCH 18/28] ptp: pch: allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index ee3de34..ee43549 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -74,7 +74,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
 	tristate "Intel PCH EG20T as PTP clock"
-	depends on X86_32 || COMPILE_TEST
+	depends on X86_32 || MIPS || COMPILE_TEST
 	depends on HAS_IOMEM && NET
 	select PTP_1588_CLOCK
 	help
-- 
2.6.2

Re: [PATCH 18/28] ptp: pch: allow build on MIPS platforms

[Richard Cochran]

On Mon, Nov 30, 2015 at 04:21:43PM +0000, Paul Burton wrote:
> Allow the ptp_pch driver to be built on MIPS platforms in preparation
> for use on the MIPS Boston board.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Acked-by: Richard Cochran <richardcochran@gmail.com>

[PATCH 19/28] net: pch_gbe: allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a352..4d3809a 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
 	tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	select MII
 	select PTP_1588_CLOCK_PCH
 	select NET_PTP_CLASSIFY
-- 
2.6.2

[PATCH 20/28] net: pch_gbe: clear interrupt FIFO during probe

[Paul Burton]

xilinx_pcie_init_port clears the pending interrupts in the interrupt
decode register, but does not clear the interrupt FIFO. This would lead
to spurious interrupts if any were present in the FIFO at probe time.
Clear the interrupt FIFO prior to the interrupt decode register in order
to start with a clean slate as expected.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/pci/host/pcie-xilinx.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index ac9da72..0edb612 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -566,6 +566,8 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
  */
 static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 {
+	u32 val;
+
 	if (xilinx_pcie_link_is_up(port))
 		dev_info(port->dev, "PCIe Link is UP\n");
 	else
@@ -575,6 +577,17 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 	pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
 		   XILINX_PCIE_REG_IMR);
 
+	/* Clear interrupt FIFO */
+	while (1) {
+		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
+
+		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID))
+			break;
+
+		pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+			   XILINX_PCIE_REG_RPIFR1);
+	}
+
 	/* Clear pending interrupts */
 	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
 			 XILINX_PCIE_IMR_ALL_MASK,
-- 
2.6.2

Re: [PATCH 20/28] net: pch_gbe: clear interrupt FIFO during probe

[Florian Fainelli]

On 30/11/15 08:21, Paul Burton wrote:
> xilinx_pcie_init_port clears the pending interrupts in the interrupt
> decode register, but does not clear the interrupt FIFO. This would lead
> to spurious interrupts if any were present in the FIFO at probe time.
> Clear the interrupt FIFO prior to the interrupt decode register in order
> to start with a clean slate as expected.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Seems like the subject should be "PCI: xilinx: ..." to be consistent
with the changes you are making to this driver earlier in the series?
-- 
Florian

[PATCH 21/28] net: pch_gbe: mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 3b98b263b..fde4c11 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2717,7 +2717,8 @@ err_free_netdev:
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+		GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
 	unsigned gpio = MINNOW_PHY_RESET_GPIO;
 	int ret;
 
@@ -2729,10 +2730,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 		return ret;
 	}
 
-	gpio_set_value(gpio, 0);
-	usleep_range(1250, 1500);
 	gpio_set_value(gpio, 1);
 	usleep_range(1250, 1500);
+	gpio_set_value(gpio, 0);
+	usleep_range(1250, 1500);
 
 	return ret;
 }
-- 
2.6.2

[PATCH 22/28] net: pch_gbe: pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h    |  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++-------
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 2a55d6d..884f90b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -582,15 +582,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:		PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:		Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate:	Bool, disable PHY hibernation
  * @platform_init:		Platform initialization callback, called from
  *				probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+	struct gpio_desc *phy_reset_gpio;
 	bool phy_tx_clk_delay;
 	bool phy_disable_hibernate;
-	int (*platform_init)(struct pci_dev *pdev);
+	int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index fde4c11..23d28f0 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 	pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+	struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+	if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+		return;
+
+	gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:	Pointer to the HW structure
@@ -2627,7 +2637,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 	adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
 	adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
 	if (adapter->pdata && adapter->pdata->platform_init)
-		adapter->pdata->platform_init(pdev);
+		adapter->pdata->platform_init(pdev, pdata);
+
+	if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+		pch_gbe_phy_set_reset(&adapter->hw, 1);
+		usleep_range(1250, 1500);
+		pch_gbe_phy_set_reset(&adapter->hw, 0);
+		usleep_range(1250, 1500);
+	}
 
 	adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
 					       PCI_DEVFN(12, 4));
@@ -2715,7 +2732,8 @@ err_free_netdev:
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+					struct pch_gbe_privdata *pdata)
 {
 	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
 		GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2724,16 +2742,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 
 	ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
 				    "minnow_phy_reset");
-	if (ret) {
+	if (!ret)
+		pdata->phy_reset_gpio = gpio_to_desc(gpio);
+	else
 		dev_err(&pdev->dev,
 			"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-		return ret;
-	}
-
-	gpio_set_value(gpio, 1);
-	usleep_range(1250, 1500);
-	gpio_set_value(gpio, 0);
-	usleep_range(1250, 1500);
 
 	return ret;
 }
-- 
2.6.2

[PATCH 23/28] net: pch_gbe: always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 23d28f0..824ff9e 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -378,10 +378,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
 	/* Read the MAC address. and store to the private data */
 	pch_gbe_mac_read_mac_addr(hw);
+	pch_gbe_phy_set_reset(hw, 1);
 	iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
 	iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 #endif
+	pch_gbe_phy_set_reset(hw, 0);
+	usleep_range(1250, 1500);
 	pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 	/* Setup the receive addresses */
 	pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.6.2

[PATCH 24/28] net: pch_gbe: add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 824ff9e..f2a9a38 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include <linux/net_tstamp.h>
 #include <linux/ptp_classify.h>
 #include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_gpio.h>
 
 #define DRV_VERSION     "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2594,13 +2596,41 @@ static void pch_gbe_remove(struct pci_dev *pdev)
 	free_netdev(netdev);
 }
 
+static int pch_gbe_parse_dt(struct pci_dev *pdev,
+			    struct pch_gbe_privdata **pdata)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct gpio_desc *gpio;
+
+	if (!config_enabled(CONFIG_OF) || !np)
+		return 0;
+
+	if (!*pdata)
+		*pdata = devm_kzalloc(&pdev->dev, sizeof(**pdata), GFP_KERNEL);
+	if (!*pdata)
+		return -ENOMEM;
+
+	gpio = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_ASIS);
+	if (IS_ERR(gpio))
+		return PTR_ERR(gpio);
+
+	(*pdata)->phy_reset_gpio = gpio;
+	return 0;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *pci_id)
 {
 	struct net_device *netdev;
 	struct pch_gbe_adapter *adapter;
+	struct pch_gbe_privdata *pdata;
 	int ret;
 
+	pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+	ret = pch_gbe_parse_dt(pdev, &pdata);
+	if (ret)
+		goto err_out;
+
 	ret = pcim_enable_device(pdev);
 	if (ret)
 		return ret;
@@ -2638,7 +2668,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 	adapter->pdev = pdev;
 	adapter->hw.back = adapter;
 	adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-	adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+	adapter->pdata = pdata;
 	if (adapter->pdata && adapter->pdata->platform_init)
 		adapter->pdata->platform_init(pdev, pdata);
 
@@ -2729,6 +2759,7 @@ err_free_adapter:
 	pch_gbe_hal_phy_hw_reset(&adapter->hw);
 err_free_netdev:
 	free_netdev(netdev);
+err_out:
 	return ret;
 }
 
-- 
2.6.2

Re: [PATCH 24/28] net: pch_gbe: add device tree support

[Andy Shevchenko]

On Mon, Nov 30, 2015 at 6:21 PM, Paul Burton <paul.burton@imgtec.com> wrote:
> Introduce support for retrieving the PHY reset GPIO from device tree,
> which will be used on the MIPS Boston development board. This requires
> support for probe deferral in order to work correctly, since the order
> of device probe is not guaranteed & typically the EG20T GPIO controller
> device will be probed after the ethernet MAC.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> index 824ff9e..f2a9a38 100644
> --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> @@ -23,6 +23,8 @@
>  #include <linux/net_tstamp.h>
>  #include <linux/ptp_classify.h>
>  #include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/of_gpio.h>
>
>  #define DRV_VERSION     "1.01"
>  const char pch_driver_version[] = DRV_VERSION;
> @@ -2594,13 +2596,41 @@ static void pch_gbe_remove(struct pci_dev *pdev)
>         free_netdev(netdev);
>  }
>
> +static int pch_gbe_parse_dt(struct pci_dev *pdev,
> +                           struct pch_gbe_privdata **pdata)

Why not to return pdata as it done in many other drivers?
You have ERR_PTR() macro to pass errors.

> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct gpio_desc *gpio;
> +
> +       if (!config_enabled(CONFIG_OF) || !np)

Before I saw IS_ENABLED(). Is this one a preferable new API?

> +               return 0;
> +
> +       if (!*pdata)
> +               *pdata = devm_kzalloc(&pdev->dev, sizeof(**pdata), GFP_KERNEL);
> +       if (!*pdata)
> +               return -ENOMEM;
> +
> +       gpio = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_ASIS);
> +       if (IS_ERR(gpio))
> +               return PTR_ERR(gpio);
> +
> +       (*pdata)->phy_reset_gpio = gpio;
> +       return 0;
> +}
> +
>  static int pch_gbe_probe(struct pci_dev *pdev,
>                           const struct pci_device_id *pci_id)
>  {
>         struct net_device *netdev;
>         struct pch_gbe_adapter *adapter;
> +       struct pch_gbe_privdata *pdata;
>         int ret;
>
> +       pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
> +       ret = pch_gbe_parse_dt(pdev, &pdata);

So, I didn;t see anything related to dt in that function.
Maybe you just call it always? In that case remove check for np.

> +       if (ret)
> +               goto err_out;
> +
>         ret = pcim_enable_device(pdev);
>         if (ret)
>                 return ret;
> @@ -2638,7 +2668,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
>         adapter->pdev = pdev;
>         adapter->hw.back = adapter;
>         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
> -       adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
> +       adapter->pdata = pdata;
>         if (adapter->pdata && adapter->pdata->platform_init)
>                 adapter->pdata->platform_init(pdev, pdata);
>
> @@ -2729,6 +2759,7 @@ err_free_adapter:
>         pch_gbe_hal_phy_hw_reset(&adapter->hw);
>  err_free_netdev:
>         free_netdev(netdev);
> +err_out:

Redundant.

>         return ret;
>  }

For now it's a common practice to mix styles in probe due to usage of
devres API.

-- 
With Best Regards,
Andy Shevchenko

[PATCH 25/28] net: pch_gbe: allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Bump up
the number of loops.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index f2a9a38..f650f45 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -321,7 +321,7 @@ static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 	u32 tmp;
 
 	/* wait busy */
-	tmp = 1000;
+	tmp = 10000;
 	while ((ioread32(reg) & bit) && --tmp)
 		cpu_relax();
 	if (!tmp)
-- 
2.6.2

[PATCH 26/28] MIPS: support for generating FIT (.itb) images

[Paul Burton]

Introduce support for generating Flattened Image Tree images containing
the kernel & platform-specific configuration such as a device tree
binary. The FIT format is supported by U-Boot and has a number of
advantages over the older legacy uImage format:

  - It includes device tree binaries inside the image without embedding
    them directly into the kernel ELF, allowing the bootloader to easily
    find & manipulate the DTB whilst still only requiring a single file
    to be loaded during boot or distributed to users.

  - It allows for an arbitrary number of images & configurations to be
    included in a single file. Once the code for various systems built
    around the MIPS Coherent Processing System architecture (ie.
    Imagination Technologies MIPS cores with optional CM, GIC & CPC) is
    consolidated sufficiently this will allow for a single binary to
    include multiple device trees & boot on multiple boards.

  - It allows for a choice of hash algorithms to verify the contents of
    the image.

  - It allows for cryptographically signed images should that ever be
    desired.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/Makefile          |  6 ++++-
 arch/mips/boot/Makefile     | 61 +++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/boot/skeleton.its | 24 ++++++++++++++++++
 3 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/skeleton.its

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 3f70ba5..bf4606f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -267,7 +267,8 @@ KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
 KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
 
 bootvars-y	= VMLINUX_LOAD_ADDRESS=$(load-y) \
-		  VMLINUX_ENTRY_ADDRESS=$(entry-y)
+		  VMLINUX_ENTRY_ADDRESS=$(entry-y) \
+		  PLATFORM_ITS=$(its-y)
 
 LDFLAGS			+= -m $(ld-emul)
 
@@ -307,6 +308,9 @@ boot-y			+= uImage.gz
 boot-y			+= uImage.lzma
 boot-y			+= uImage.lzo
 endif
+boot-y			+= vmlinux.itb
+boot-y			+= vmlinux.bz2.itb
+boot-y			+= vmlinux.gz.itb
 
 # compressed boot image targets (arch/mips/boot/compressed/)
 bootz-y			:= vmlinuz
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index acb1988..82de53d 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -100,3 +100,64 @@ $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
 $(obj)/uImage: $(obj)/uImage.$(suffix-y)
 	@ln -sf $(notdir $<) $@
 	@echo '  Image $@ is ready'
+
+#
+# Flattened Image Tree (.itb) images
+#
+
+targets += vmlinux.itb
+targets += vmlinux.gz.itb
+
+# Split a 64bit address into 2x32bit hex integers
+its_addr = $(shell echo $(1) | sed 's/0x\(........\)\(........\)/0x\1 0x\2/')
+
+its_load_addr := $(call its_addr,$(VMLINUX_LOAD_ADDRESS))
+its_entry_addr := $(call its_addr,$(VMLINUX_ENTRY_ADDRESS))
+
+its_files := $(patsubst %,$(srctree)/arch/mips/%,$(PLATFORM_ITS))
+its_inc := $(patsubst %,/include/ \"%\"\n,$(PLATFORM_ITS))
+
+quiet_cmd_gen-its = ITS     $@
+      cmd_gen-its = sed "s|__VMLINUX__|$(2)|g" $< | \
+		sed "s|__VMLINUX_COMPRESSION__|$(3)|g" | \
+		sed "s|__PLATFORM_INCLUDES__|$(its_inc)|g" | \
+		sed "s|__LOAD_ADDR__|$(its_load_addr)|g" | \
+		sed "s|__ENTRY_ADDR__|$(its_entry_addr)|g" \
+		>$@
+
+quiet_cmd_itb-image = ITB     $@
+      cmd_itb-image = \
+		env PATH="$(objtree)/scripts/dtc:$(PATH)" \
+		$(CONFIG_SHELL) $(MKIMAGE) \
+		-D "-I dts -O dtb -p 500 --include $(srctree)/arch/mips --include $(objtree)/arch/mips" \
+		-f $(3) $@
+
+$(obj)/vmlinux.its: $(srctree)/arch/mips/boot/skeleton.its $(its_files) FORCE
+	$(call if_changed,gen-its,boot/vmlinux.bin,none)
+
+$(obj)/vmlinux.itb: $(obj)/vmlinux.bin $(obj)/vmlinux.its FORCE
+	$(call if_changed,itb-image,none,$(obj)/vmlinux.its)
+
+$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/boot/skeleton.its $(its_files) FORCE
+	$(call if_changed,gen-its,boot/vmlinux.bin.bz2,bzip2)
+
+$(obj)/vmlinux.bz2.itb: $(obj)/vmlinux.bin.bz2 $(obj)/vmlinux.bz2.its FORCE
+	$(call if_changed,itb-image,bzip2,$(obj)/vmlinux.bz2.its)
+
+$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/boot/skeleton.its $(its_files) FORCE
+	$(call if_changed,gen-its,boot/vmlinux.bin.gz,gzip)
+
+$(obj)/vmlinux.gz.itb: $(obj)/vmlinux.bin.gz $(obj)/vmlinux.gz.its FORCE
+	$(call if_changed,itb-image,gzip,$(obj)/vmlinux.gz.its)
+
+$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/boot/skeleton.its $(its_files) FORCE
+	$(call if_changed,gen-its,boot/vmlinux.bin.lzma,lzmaip)
+
+$(obj)/vmlinux.lzma.itb: $(obj)/vmlinux.bin.lzma $(obj)/vmlinux.lzma.its FORCE
+	$(call if_changed,itb-image,lzma,$(obj)/vmlinux.lzma.its)
+
+$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/boot/skeleton.its $(its_files) FORCE
+	$(call if_changed,gen-its,boot/vmlinux.bin.lzo,lzoip)
+
+$(obj)/vmlinux.lzo.itb: $(obj)/vmlinux.bin.lzo $(obj)/vmlinux.lzo.its FORCE
+	$(call if_changed,itb-image,lzo,$(obj)/vmlinux.lzo.its)
diff --git a/arch/mips/boot/skeleton.its b/arch/mips/boot/skeleton.its
new file mode 100644
index 0000000..a49c3d2
--- /dev/null
+++ b/arch/mips/boot/skeleton.its
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/ {
+	description = "MIPS Linux";
+	#address-cells = <1>;
+
+	images {
+		kernel@0 {
+			description = "Linux";
+			data = /incbin/("__VMLINUX__");
+			type = "kernel";
+			arch = "mips";
+			os = "linux";
+			compression = "__VMLINUX_COMPRESSION__";
+			load = <__LOAD_ADDR__>;
+			entry = <__ENTRY_ADDR__>;
+			hash@1 {
+				algo = "sha1";
+			};
+		};
+	};
+};
+
+__PLATFORM_INCLUDES__
-- 
2.6.2

[PATCH 27/28] dt-bindings: mips: img,boston: Document img,boston binding

[Paul Burton]

Add documentation for the simple img,boston devicetree binding & the
boot protocol used to pass the devicetree to the kernel.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 Documentation/devicetree/bindings/mips/img/boston.txt | 15 +++++++++++++++
 MAINTAINERS                                           |  5 +++++
 2 files changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/img/boston.txt

diff --git a/Documentation/devicetree/bindings/mips/img/boston.txt b/Documentation/devicetree/bindings/mips/img/boston.txt
new file mode 100644
index 0000000..27b2806
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/img/boston.txt
@@ -0,0 +1,15 @@
+Imagination Technologies Boston Development Board
+=================================================
+
+Required properties:
+--------------------
+ - compatible: Must be "img,boston".
+
+Boot protocol:
+--------------
+In accordance with the MIPS UHI specification[1], the bootloader must pass the
+following arguments to the kernel:
+ - $a0: -2.
+ - $a1: KSEG0 address of the flattened device-tree blob.
+
+[1] http://prplfoundation.org/wiki/MIPS_documentation
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e156b2..a9cd996 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5435,6 +5435,11 @@ L:	linux-security-module@vger.kernel.org
 S:	Supported
 F:	security/integrity/ima/
 
+IMGTEC BOSTON PLATFORM SUPPORT
+M:	Paul Burton <paul.burton@imgtec.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/mips/img/boston.txt
+
 IMGTEC IR DECODER DRIVER
 M:	James Hogan <james.hogan@imgtec.com>
 S:	Maintained
-- 
2.6.2

Re: [PATCH 27/28] dt-bindings: mips: img,boston: Document img,boston binding

[Rob Herring]

On Mon, Nov 30, 2015 at 04:21:52PM +0000, Paul Burton wrote:
> Add documentation for the simple img,boston devicetree binding & the
> boot protocol used to pass the devicetree to the kernel.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
> 
>  Documentation/devicetree/bindings/mips/img/boston.txt | 15 +++++++++++++++
>  MAINTAINERS                                           |  5 +++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mips/img/boston.txt
> 
> diff --git a/Documentation/devicetree/bindings/mips/img/boston.txt b/Documentation/devicetree/bindings/mips/img/boston.txt
> new file mode 100644
> index 0000000..27b2806
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/img/boston.txt
> @@ -0,0 +1,15 @@
> +Imagination Technologies Boston Development Board
> +=================================================
> +
> +Required properties:
> +--------------------
> + - compatible: Must be "img,boston".

No SOC compatible in addition?

> +
> +Boot protocol:
> +--------------
> +In accordance with the MIPS UHI specification[1], the bootloader must pass the
> +following arguments to the kernel:
> + - $a0: -2.
> + - $a1: KSEG0 address of the flattened device-tree blob.

If this is standard, I don't know that we need to repeat it for every 
board.

Rob

> +
> +[1] http://prplfoundation.org/wiki/MIPS_documentation

[PATCH 28/28] MIPS: Boston board support

[Paul Burton]

Add support for the MIPS Boston development board. Boston is an
FPGA-based development board akin to the much older Malta board. As such
it's very configurable, but in broad terms it's built around a Xilinx
FPGA running a MIPS core & other logic, and 3 Xilinx PCIe root ports -
one of which is connected to an Intel EG20T Platform Controller Hub to
provide a base set of peripherals.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 MAINTAINERS                                        |   3 +
 arch/mips/Kbuild.platforms                         |   1 +
 arch/mips/Kconfig                                  |  39 ++++
 arch/mips/boot/dts/Makefile                        |   1 +
 arch/mips/boot/dts/img/Makefile                    |   7 +
 arch/mips/boot/dts/img/boston.dts                  | 201 +++++++++++++++++++++
 arch/mips/boston/Makefile                          |  12 ++
 arch/mips/boston/Platform                          |   8 +
 arch/mips/boston/init.c                            |  75 ++++++++
 arch/mips/boston/int.c                             |  33 ++++
 arch/mips/boston/time.c                            |  89 +++++++++
 arch/mips/boston/vmlinux.its                       |  23 +++
 arch/mips/configs/boston_defconfig                 | 170 +++++++++++++++++
 .../asm/mach-boston/cpu-feature-overrides.h        |  26 +++
 arch/mips/include/asm/mach-boston/irq.h            |  18 ++
 arch/mips/include/asm/mach-boston/spaces.h         |  20 ++
 16 files changed, 726 insertions(+)
 create mode 100644 arch/mips/boot/dts/img/Makefile
 create mode 100644 arch/mips/boot/dts/img/boston.dts
 create mode 100644 arch/mips/boston/Makefile
 create mode 100644 arch/mips/boston/Platform
 create mode 100644 arch/mips/boston/init.c
 create mode 100644 arch/mips/boston/int.c
 create mode 100644 arch/mips/boston/time.c
 create mode 100644 arch/mips/boston/vmlinux.its
 create mode 100644 arch/mips/configs/boston_defconfig
 create mode 100644 arch/mips/include/asm/mach-boston/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-boston/irq.h
 create mode 100644 arch/mips/include/asm/mach-boston/spaces.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a9cd996..a1e7f8f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5438,6 +5438,9 @@ F:	security/integrity/ima/
 IMGTEC BOSTON PLATFORM SUPPORT
 M:	Paul Burton <paul.burton@imgtec.com>
 S:	Maintained
+F:	arch/mips/boot/dts/img/boston.dts
+F:	arch/mips/boston/
+F:	arch/mips/include/asm/mach-boston/
 F:	Documentation/devicetree/bindings/mips/img/boston.txt
 
 IMGTEC IR DECODER DRIVER
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index a96c81d..b1ab69a 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -7,6 +7,7 @@ platforms += ath79
 platforms += bcm47xx
 platforms += bcm63xx
 platforms += bmips
+platforms += boston
 platforms += cavium-octeon
 platforms += cobalt
 platforms += dec
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6d11a41..74b4d19 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -216,6 +216,45 @@ config BCM63XX
 	help
 	 Support for BCM63XX based boards
 
+config BOSTON
+	bool "MIPS Boston board"
+	select ARCH_REQUIRE_GPIOLIB
+	select BOOT_ELF32
+	select BOOT_RAW
+	select BUILTIN_DTB
+	select CEVT_R4K
+	select COMMON_CLK
+	select CSRC_R4K
+	select DMA_NONCOHERENT
+	select HW_HAS_PCI
+	select IRQ_MIPS_CPU
+	select MIPS_CPU_SCACHE
+	select MIPS_GENERIC_PCI
+	select MIPS_GIC
+	select MIPS_L1_CACHE_SHIFT_6
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_CPU_MIPS32_R3_5
+	select SYS_HAS_CPU_MIPS32_R5
+	select SYS_HAS_CPU_MIPS32_R6
+	select SYS_HAS_CPU_MIPS64_R1
+	select SYS_HAS_CPU_MIPS64_R2
+	select SYS_HAS_CPU_MIPS64_R6
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_MIPS_CPS
+	select SYS_SUPPORTS_MULTITHREADING
+	select SYS_SUPPORTS_ZBOOT
+	select USE_OF
+	help
+	  This enables support for the MIPS Boston development board from
+	  Imagination Technologies. Boston is an FPGA-based development
+	  board aimed at evaluating MIPS CPUs & developing software for
+	  them. If you wish to build for such a board, select this.
+
 config MIPS_COBALT
 	bool "Cobalt Server"
 	select CEVT_R4K
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index a0bf516..a41417b 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -1,5 +1,6 @@
 dts-dirs	+= brcm
 dts-dirs	+= cavium-octeon
+dts-dirs	+= img
 dts-dirs	+= ingenic
 dts-dirs	+= lantiq
 dts-dirs	+= mti
diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile
new file mode 100644
index 0000000..6cc1737
--- /dev/null
+++ b/arch/mips/boot/dts/img/Makefile
@@ -0,0 +1,7 @@
+dtb-$(CONFIG_BOSTON)		+= boston.dtb
+
+# Force kbuild to make empty built-in.o if necessary
+obj-				+= dummy.o
+
+always				:= $(dtb-y)
+clean-files			:= *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
new file mode 100644
index 0000000..1104a68
--- /dev/null
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -0,0 +1,201 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "img,boston";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "img,mips";
+			reg = <0>;
+			clocks = <&clk_sys>;
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	clk_sys: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <10000000>;
+	};
+
+	axi4 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <>;
+
+		gic: interrupt-controller {
+			compatible = "mti,gic";
+
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			timer {
+				compatible = "mti,gic-timer";
+				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+				clocks = <&clk_sys>;
+			};
+		};
+
+		uart0: uart@17ffe000 {
+			compatible = "ns16550a";
+			reg = <0x17ffe000 0x1000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&clk_sys>;
+		};
+
+		lcd: lcd@17fff000 {
+			compatible = "img,boston-lcd";
+			reg = <0x17fff000 0x8>;
+		};
+
+		pci0: pci@10000000 {
+			compatible = "xlnx,axi-pcie-host-1.00.a";
+			device_type = "pci";
+			reg = <0x10000000 0x2000000>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+
+			ranges = <0x02000000 0 0x40000000 0x40000000 0 0x40000000>;
+
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pci0_intc 0>,
+					<0 0 0 2 &pci0_intc 1>,
+					<0 0 0 3 &pci0_intc 2>,
+					<0 0 0 4 &pci0_intc 3>;
+
+			pci0_intc: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		pci1: pci@12000000 {
+			compatible = "xlnx,axi-pcie-host-1.00.a";
+			device_type = "pci";
+			reg = <0x12000000 0x2000000>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+
+			ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>;
+
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pci1_intc 0>,
+					<0 0 0 2 &pci1_intc 1>,
+					<0 0 0 3 &pci1_intc 2>,
+					<0 0 0 4 &pci1_intc 3>;
+
+			pci1_intc: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		pci2: pci@14000000 {
+			compatible = "xlnx,axi-pcie-host-1.00.a";
+			device_type = "pci";
+			reg = <0x14000000 0x2000000>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+
+			ranges = <0x02000000 0 0x16000000 0x16000000 0 0x100000>;
+
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pci2_intc 0>,
+					<0 0 0 2 &pci2_intc 1>,
+					<0 0 0 3 &pci2_intc 2>,
+					<0 0 0 4 &pci2_intc 3>;
+
+			pci2_intc: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+
+			pci2_root@0,0,0 {
+				compatible = "pci10ee,7021";
+				reg = <0x00000000 0 0 0 0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+
+				eg20t_bridge@1,0,0 {
+					compatible = "pci8086,8800";
+					reg = <0x00010000 0 0 0 0>;
+
+					#address-cells = <3>;
+					#size-cells = <2>;
+					#interrupt-cells = <1>;
+
+					eg20t_mac@2,0,1 {
+						compatible = "pci8086,8802";
+						reg = <0x00020100 0 0 0 0>;
+						phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
+					};
+
+					eg20t_gpio: eg20t_gpio@2,0,2 {
+						compatible = "pci8086,8803";
+						reg = <0x00020200 0 0 0 0>;
+
+						gpio-controller;
+						#gpio-cells = <2>;
+					};
+
+					eg20t_i2c@2,12,2 {
+						compatible = "pci8086,8817";
+						reg = <0x00026200 0 0 0 0>;
+
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						rtc@0x68 {
+							compatible = "st,m41t81s";
+							reg = <0x68>;
+						};
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/arch/mips/boston/Makefile b/arch/mips/boston/Makefile
new file mode 100644
index 0000000..0a13246
--- /dev/null
+++ b/arch/mips/boston/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2015 Imagination Technologies
+# Author: Paul Burton <paul.burton@imgtec.com>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 2 of the License, or (at your
+# option) any later version.
+#
+obj-y	+= init.o
+obj-y	+= int.o
+obj-y	+= time.o
diff --git a/arch/mips/boston/Platform b/arch/mips/boston/Platform
new file mode 100644
index 0000000..d3dad1e
--- /dev/null
+++ b/arch/mips/boston/Platform
@@ -0,0 +1,8 @@
+#
+# MIPS Boston board
+#
+platform-$(CONFIG_BOSTON)	+= boston/
+cflags-$(CONFIG_BOSTON)		+= -I$(srctree)/arch/mips/include/asm/mach-boston
+load-$(CONFIG_BOSTON)		+= 0xffffffff80100000
+all-$(CONFIG_BOSTON)		:= $(COMPRESSION_FNAME).bin
+its-$(CONFIG_BOSTON)		+= boston/vmlinux.its
diff --git a/arch/mips/boston/init.c b/arch/mips/boston/init.c
new file mode 100644
index 0000000..4bab5ba
--- /dev/null
+++ b/arch/mips/boston/init.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/string.h>
+
+#include <asm/fw/fw.h>
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+
+void __init plat_mem_setup(void)
+{
+	if (fw_arg0 != -2)
+		panic("Device-tree not present");
+
+	__dt_setup_arch((void *)fw_arg1);
+	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+}
+
+void __init device_tree_init(void)
+{
+	unflatten_and_copy_device_tree();
+}
+
+static int __init publish_devices(void)
+{
+	if (!of_have_populated_dt())
+		panic("Device-tree not present");
+
+	if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
+		panic("Failed to populate DT");
+
+	return 0;
+}
+arch_initcall(publish_devices);
+
+phys_addr_t mips_cpc_default_phys_base(void)
+{
+	return 0x16200000;
+}
+
+phys_addr_t mips_cdmm_phys_base(void)
+{
+	return 0x16140000;
+}
+
+const char *get_system_type(void)
+{
+	return "MIPS Boston";
+}
+
+void __init prom_init(void)
+{
+	fw_init_cmdline();
+	mips_cm_probe();
+	mips_cpc_probe();
+	register_cps_smp_ops();
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
diff --git a/arch/mips/boston/int.c b/arch/mips/boston/int.c
new file mode 100644
index 0000000..4069424
--- /dev/null
+++ b/arch/mips/boston/int.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mips-cm.h>
+#include <asm/traps.h>
+
+static int be_handler(struct pt_regs *regs, int is_fixup)
+{
+	mips_cm_error_report();
+	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
+}
+
+void __init arch_init_irq(void)
+{
+	board_be_handler = be_handler;
+
+	if (!cpu_has_veic)
+		mips_cpu_irq_init();
+
+	irqchip_init();
+}
diff --git a/arch/mips/boston/time.c b/arch/mips/boston/time.c
new file mode 100644
index 0000000..a51710a
--- /dev/null
+++ b/arch/mips/boston/time.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/irqchip/mips-gic.h>
+#include <linux/types.h>
+
+#include <asm/irq.h>
+#include <asm/time.h>
+
+void __init plat_time_init(void)
+{
+	struct device_node *np;
+	struct clk *clk;
+
+	of_clk_init(NULL);
+	clocksource_probe();
+
+	np = of_get_cpu_node(0, NULL);
+	if (!np) {
+		pr_err("Failed to get CPU node\n");
+		return;
+	}
+
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk)) {
+		pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
+		return;
+	}
+
+	mips_hpt_frequency = clk_get_rate(clk) / 2;
+	clk_put(clk);
+}
+
+int get_c0_fdc_int(void)
+{
+	int mips_cpu_fdc_irq;
+
+	if (cpu_has_veic)
+		panic("Unimplemented!");
+	else if (gic_present)
+		mips_cpu_fdc_irq = gic_get_c0_fdc_int();
+	else if (cp0_fdc_irq >= 0)
+		mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
+	else
+		mips_cpu_fdc_irq = -1;
+
+	return mips_cpu_fdc_irq;
+}
+
+int get_c0_perfcount_int(void)
+{
+	int mips_cpu_perf_irq;
+
+	if (cpu_has_veic)
+		panic("Unimplemented!");
+	else if (gic_present)
+		mips_cpu_perf_irq = gic_get_c0_perfcount_int();
+	else if (cp0_perfcount_irq >= 0)
+		mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+	else
+		mips_cpu_perf_irq = -1;
+
+	return mips_cpu_perf_irq;
+}
+
+unsigned int get_c0_compare_int(void)
+{
+	int mips_cpu_timer_irq;
+
+	if (cpu_has_veic)
+		panic("Unimplemented!");
+	else if (gic_present)
+		mips_cpu_timer_irq = gic_get_c0_compare_int();
+	else
+		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+
+	return mips_cpu_timer_irq;
+}
diff --git a/arch/mips/boston/vmlinux.its b/arch/mips/boston/vmlinux.its
new file mode 100644
index 0000000..643ac63
--- /dev/null
+++ b/arch/mips/boston/vmlinux.its
@@ -0,0 +1,23 @@
+/ {
+	images {
+		fdt@boston {
+			description = "img,boston Device Tree";
+			data = /incbin/("boot/dts/img/boston.dtb");
+			type = "flat_dt";
+			arch = "mips";
+			compression = "none";
+			hash@1 {
+				algo = "sha1";
+			};
+		};
+	};
+
+	configurations {
+		default = "conf@boston";
+		conf@boston {
+			description = "Boot Linux kernel";
+			kernel = "kernel@0";
+			fdt = "fdt@boston";
+		};
+	};
+};
diff --git a/arch/mips/configs/boston_defconfig b/arch/mips/configs/boston_defconfig
new file mode 100644
index 0000000..43c1fce
--- /dev/null
+++ b/arch/mips/configs/boston_defconfig
@@ -0,0 +1,170 @@
+CONFIG_BOSTON=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R6=y
+CONFIG_64BIT=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_CPU_HAS_MSA=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_48=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_XILINX=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_PCH_PHUB=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+CONFIG_PCH_GBE=y
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_EG20T=y
+CONFIG_SPI=y
+CONFIG_SPI_TOPCLIFF_PCH=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCH=y
+# CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
+# CONFIG_VGA_ARB is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+# CONFIG_MMC_RICOH_MMC is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_DMADEVICES=y
+CONFIG_PCH_DMA=y
+CONFIG_AUXDISPLAY=y
+CONFIG_ASCII_LCD=y
+# CONFIG_MIPS_PLATFORM_DEVICES is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_FRAME_WARN=1024
+CONFIG_READABLE_ASM=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="earlycon console=ttyS0,57600"
+# CONFIG_CRYPTO_HW is not set
+CONFIG_LIBCRC32C=y
diff --git a/arch/mips/include/asm/mach-boston/cpu-feature-overrides.h b/arch/mips/include/asm/mach-boston/cpu-feature-overrides.h
new file mode 100644
index 0000000..e1bd9b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-boston/cpu-feature-overrides.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_BOSTON_CPU_FEATURE_OVERRIDES_H__
+#define __ASM_MACH_BOSTON_CPU_FEATURE_OVERRIDES_H__
+
+#define cpu_has_4kex			1
+#define cpu_has_4k_cache		1
+#define cpu_has_clo_clz			1
+#define cpu_has_counter			1
+#define cpu_has_divec			1
+#define cpu_has_llsc			1
+#define cpu_has_mcheck			1
+#define cpu_has_nofpuex			0
+#define cpu_has_tlb			1
+#define cpu_has_vce			0
+#define cpu_icache_snoops_remote_store	1
+
+#endif /* __ASM_MACH_BOSTON_CPU_FEATURE_OVERRIDES_H__ */
diff --git a/arch/mips/include/asm/mach-boston/irq.h b/arch/mips/include/asm/mach-boston/irq.h
new file mode 100644
index 0000000..95ac10c
--- /dev/null
+++ b/arch/mips/include/asm/mach-boston/irq.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_BOSTON_IRQ_H__
+#define __ASM_MACH_BOSTON_IRQ_H__
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_BOSTON_IRQ_H__ */
diff --git a/arch/mips/include/asm/mach-boston/spaces.h b/arch/mips/include/asm/mach-boston/spaces.h
new file mode 100644
index 0000000..e7f4c59
--- /dev/null
+++ b/arch/mips/include/asm/mach-boston/spaces.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_BOSTON_SPACES_H__
+#define __ASM_MACH_BOSTON_SPACES_H__
+
+#ifdef CONFIG_64BIT
+# define CAC_BASE _AC(0xa800000000000000, UL)
+#endif
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_MACH_BOSTON_SPACES_H__ */
-- 
2.6.2