From: Borislav Petkov <bp@alien8.de>
To: tthayer@opensource.altera.com
Cc: dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com
Subject: Re: [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC
Date: Fri, 4 Mar 2016 11:38:44 +0100 [thread overview]
Message-ID: <20160304103844.GC16291@pd.tnic> (raw)
In-Reply-To: <1456850301-22066-3-git-send-email-tthayer@opensource.altera.com>
On Tue, Mar 01, 2016 at 10:38:19AM -0600, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Addition of the Arria10 L2 Cache ECC handling. The major
> changes affect the L2 ECC registers not being grouped
> together. The Arria10 IRQ status needs to be mapped into
> a different region. The mapping occurs in the L2 specific
> function.
> Important changes include:
> 1) Move private data structure definition to altera_edac.h
> 2) Move Cyclone5 device defines to altera_edac.h
This should be a separate patch.
> 3) Split IRQ status and ECC enable/control into separate
> memory areas.
Ditto.
> 4) Add IRQ status mapping in L2 ECC dependency checks
> function.
Ditto...
> 5) Addition of register offsets in private data structure.
> 6) Changes to code to use register offset define.
> 7) Addition of Arria10 L2 cache private data.
> 8) Add IRQ flags to indicate Exclusive/Shared.
Do you see where I'm going with this?
Each patch should countain one logical change: add defines and move
struct, change functionality A, change functionality B, ...
The fact that you have to make a list of 8 important changes should
already give you a hint that it needs to be split.
As always, I'm going to need ACKs for the ARM stuff.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
next prev parent reply other threads:[~2016-03-04 10:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 16:38 [PATCH 1/5] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-01 16:38 ` [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding tthayer
2016-03-05 4:26 ` Rob Herring
2016-03-01 16:38 ` [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-04 10:38 ` Borislav Petkov [this message]
2016-03-04 15:42 ` Thor Thayer
2016-03-01 16:38 ` [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
2016-03-05 6:36 ` Dinh Nguyen
2016-03-01 16:38 ` [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer
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