From: Mark Rutland <mark.rutland@arm.com>
To: Stafford Horne <shorne@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Openrisc <openrisc@lists.librecores.org>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
Rob Herring <robh+dt@kernel.org>, Jonas Bonn <jonas@southpole.se>,
Krzysztof Kozlowski <krzk@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
Date: Thu, 31 Aug 2017 11:41:10 +0100 [thread overview]
Message-ID: <20170831104110.GD15031@leverpostej> (raw)
In-Reply-To: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne@gmail.com>
On Thu, Aug 31, 2017 at 07:03:11AM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP. This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: Added defconfig]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++
> arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
> 2 files changed, 124 insertions(+)
> create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
> create mode 100644 arch/openrisc/configs/simple_smp_defconfig
>
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> + compatible = "opencores,or1ksim";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&pic>;
> +
> + chosen {
> + bootargs = "console=uart,mmio,0x90000000,115200";
> + };
Any reason this isn't using stdout-path?
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x00000000 0x02000000>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + compatible = "opencores,or1200-rtlsvn481";
> + reg = <0>;
> + clock-frequency = <20000000>;
> + };
> + cpu@1 {
> + compatible = "opencores,or1200-rtlsvn481";
> + reg = <1>;
> + clock-frequency = <20000000>;
> + };
> + };
No enable-method or similar?
Is your SMP bringup/teardown architected?
> +
> + ompic: ompic {
> + compatible = "ompic";
This needs a vendor prefix.
Thanks,
Mark.
next prev parent reply other threads:[~2017-08-31 10:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-09-01 8:02 ` [OpenRISC] " Geert Uytterhoeven
2017-09-01 8:03 ` Geert Uytterhoeven
2017-09-01 8:26 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
2017-09-01 8:06 ` [OpenRISC] " Geert Uytterhoeven
2017-09-01 8:28 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-08-31 7:46 ` Peter Zijlstra
2017-08-31 9:01 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
2017-08-31 9:28 ` Marc Zyngier
2017-09-01 1:24 ` Stafford Horne
2017-09-01 17:25 ` Marc Zyngier
2017-09-03 22:12 ` Stafford Horne
2017-09-04 7:35 ` Marc Zyngier
2017-08-31 10:59 ` Mark Rutland
2017-09-01 13:59 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 06/13] openrisc: initial SMP support Stafford Horne
2017-08-30 22:02 ` [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-08-30 22:02 ` [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-08-30 22:02 ` [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-08-31 10:41 ` Mark Rutland [this message]
2017-08-31 13:05 ` Stafford Horne
2017-09-11 22:37 ` Pavel Machek
2017-09-11 22:55 ` Stafford Horne
2017-09-12 7:47 ` Pavel Machek
2017-09-12 22:15 ` Stafford Horne
2017-08-30 22:03 ` [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-08-30 22:03 ` [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-08-30 22:03 ` [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne
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