From: "'Greg KH'" <gregkh@linuxfoundation.org>
To: Dhaval Rajeshbhai Shah <DSHAH@xilinx.com>
Cc: "arnd@arndb.de" <arnd@arndb.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
Hyun Kwon <hyunk@xilinx.com>
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
Date: Wed, 6 Dec 2017 08:56:04 +0100 [thread overview]
Message-ID: <20171206075604.GA920@kroah.com> (raw)
In-Reply-To: <BY2PR0201MB18791CC7DF99F50CCF0DC904C1320@BY2PR0201MB1879.namprd02.prod.outlook.com>
On Wed, Dec 06, 2017 at 06:01:37AM +0000, Dhaval Rajeshbhai Shah wrote:
> Hi Greg k-h,
>
> Thanks a lot for the review.
>
> Replies inline.
As they should be, perhaps you need a better email client :)
>
> > +config XILINX_VCU
> > + tristate "Xilinx VCU Init"
> > + default n
>
> That's always the default, no need for this.
> [Dhaval ] : I will remove that.
This style of replying is very odd, please use the normal format in the
future.
> > + help
> > + Driver for the Xilinx VCU Init based on the logicoreIP.
>
> You need a lot more help text here to explain what this driver is, what it is for, and who would need it.
> [Dhaval ] : I will provide more help text to provide more help on driver.
>
> Also, why is this a misc driver?
> [Dhaval ] : this driver is for the logicoreIP which is created to support the Processing system and Programmable logic isolation and to provide the clock related information. So this is not a VCU driver and but just a intermediate driver which supports logicoreIP. That's why no subsystem for this.
Then you need to explain this a lot better, posting a random driver
for submission that is expected to be used by another one isn't ok.
Post the whole patch series please, we do not add infrastructure to the
kernel that is not used right then.
thanks,
greg k-h
next prev parent reply other threads:[~2017-12-06 7:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-05 11:43 [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
2017-12-05 12:18 ` Arnd Bergmann
2017-12-05 12:38 ` Dhaval Rajeshbhai Shah
2017-12-05 13:32 ` Arnd Bergmann
2017-12-06 5:44 ` Dhaval Rajeshbhai Shah
2017-12-05 13:30 ` Greg KH
2017-12-06 6:01 ` Dhaval Rajeshbhai Shah
2017-12-06 7:56 ` 'Greg KH' [this message]
2017-12-06 9:05 ` Dhaval Rajeshbhai Shah
2017-12-06 9:15 ` 'Greg KH'
2017-12-06 9:38 ` Dhaval Rajeshbhai Shah
2017-12-07 10:06 ` Philippe Ombredanne
2017-12-07 10:30 ` Dhaval Rajeshbhai Shah
2017-12-07 10:47 ` Greg Kroah-Hartman
2017-12-07 21:31 ` [PATCH v2 0/2] Documentation and driver of logicoreIP Dhaval Shah
2017-12-07 21:31 ` [PATCH v2 1/2] Documentation: devicetree: Add DT bindings to xlnx_vcu driver Dhaval Shah
2017-12-12 20:07 ` Rob Herring
2017-12-13 5:12 ` Dhaval Rajeshbhai Shah
2017-12-07 21:31 ` [PATCH v2 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
2017-12-07 21:47 ` Philippe Ombredanne
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