From: "'Greg KH'" <gregkh@linuxfoundation.org>
To: Dhaval Rajeshbhai Shah <DSHAH@xilinx.com>
Cc: "arnd@arndb.de" <arnd@arndb.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
Hyun Kwon <hyunk@xilinx.com>
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
Date: Wed, 6 Dec 2017 10:15:53 +0100 [thread overview]
Message-ID: <20171206091553.GB23022@kroah.com> (raw)
In-Reply-To: <BY2PR0201MB18791F4BB190F52A100AB94EC1320@BY2PR0201MB1879.namprd02.prod.outlook.com>
On Wed, Dec 06, 2017 at 09:05:51AM +0000, Dhaval Rajeshbhai Shah wrote:
> > Then you need to explain this a lot better, posting a random driver for
> > submission that is expected to be used by another one isn't ok.
> > Post the whole patch series please, we do not add infrastructure to the
> > kernel that is not used right then.
> Can I remove the export api and header file and make this driver generic for the logicoreIP? No other driver will depend on that. This will help us to remove the isolation between the Programmable system and Programmable logic by configuring the logicoreIp register set.
I don't know, let's see what that patch submission looks like. If it
doesn't do anything, that's not really a good idea :)
What's wrong with just submitting your entire driver series? Why break
it up like this? That's normally not a good idea, you want us to review
it in a "whole" idea, not piece-meal.
thanks,
greg k-h
next prev parent reply other threads:[~2017-12-06 9:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-05 11:43 [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
2017-12-05 12:18 ` Arnd Bergmann
2017-12-05 12:38 ` Dhaval Rajeshbhai Shah
2017-12-05 13:32 ` Arnd Bergmann
2017-12-06 5:44 ` Dhaval Rajeshbhai Shah
2017-12-05 13:30 ` Greg KH
2017-12-06 6:01 ` Dhaval Rajeshbhai Shah
2017-12-06 7:56 ` 'Greg KH'
2017-12-06 9:05 ` Dhaval Rajeshbhai Shah
2017-12-06 9:15 ` 'Greg KH' [this message]
2017-12-06 9:38 ` Dhaval Rajeshbhai Shah
2017-12-07 10:06 ` Philippe Ombredanne
2017-12-07 10:30 ` Dhaval Rajeshbhai Shah
2017-12-07 10:47 ` Greg Kroah-Hartman
2017-12-07 21:31 ` [PATCH v2 0/2] Documentation and driver of logicoreIP Dhaval Shah
2017-12-07 21:31 ` [PATCH v2 1/2] Documentation: devicetree: Add DT bindings to xlnx_vcu driver Dhaval Shah
2017-12-12 20:07 ` Rob Herring
2017-12-13 5:12 ` Dhaval Rajeshbhai Shah
2017-12-07 21:31 ` [PATCH v2 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
2017-12-07 21:47 ` Philippe Ombredanne
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