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From: Mark Brown <broonie@kernel.org>
To: "Andreas Färber" <afaerber@suse.de>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>,
	linux-kernel@vger.kernel.org,
	Ionela Voinescu <ionela.voinescu@imgtec.com>,
	Ezequiel Garcia <ezequiel.garcia@imgtec.com>,
	linux-spi@vger.kernel.org
Subject: Re: [PATCH 10/15] spi: img-spfi: Implement dual and quad mode
Date: Mon, 30 Jul 2018 16:30:34 +0100	[thread overview]
Message-ID: <20180730153034.GM5789@sirena.org.uk> (raw)
In-Reply-To: <20180722212010.3979-11-afaerber@suse.de>

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On Sun, Jul 22, 2018 at 11:20:05PM +0200, Andreas Färber wrote:

>  #define SPFI_CONTROL_GET_DMA			BIT(9)
> -#define SPFI_CONTROL_SE			BIT(8)
> +#define SPFI_CONTROL_SE				BIT(8)
> +#define SPFI_CONTROL_TX_RX			BIT(1)

Random reindent of _SE there?

> +			/*
> +			 * Disable SPFI for it not to interfere with
> +			 * pending transactions
> +			 */
> +			spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)
> +			& ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);
>  			return 0;

The indentation on the second line of the write is very confusing, it
should be indented relative to the first line.

> +	if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&
> +		/*
> +		 * For duplex mode (both the tx and rx buffers are !NULL) the
> +		 * CMD, ADDR, and DUMMY byte parts of the transaction register
> +		 * should always be 0 and therefore the pending transfer
> +		 * technique cannot be used.
> +		 */
> +		(xfer->tx_buf) && (!xfer->rx_buf) &&
> +		(xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) {
> +		transact = (1 & SPFI_TRANSACTION_CMD_MASK) <<

This is again *really* hard to read - having the comment in the middle
of the condidional for the if statement, then indenting the code within
the if statement to the same depth is just super confusing.  

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  reply	other threads:[~2018-07-30 15:30 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-22 21:19 [PATCH 00/15] MIPS: pistachio: Creator Ci40 aka Marduk SPI-UART Andreas Färber
2018-07-22 21:19 ` [PATCH 01/15] MIPS: dts: img: pistachio_marduk: Reorder nodes Andreas Färber
2018-07-22 21:19 ` [PATCH 02/15] MIPS: dts: img: pistachio_marduk: Cleanups Andreas Färber
2018-07-22 21:19 ` [PATCH 03/15] MIPS: dts: img: pistachio: Rename spim0-clk pin node label Andreas Färber
2018-07-22 21:19 ` [PATCH 04/15] MIPS: dts: img: pistachio_marduk: Switch mmc to 1 bit mode Andreas Färber
2018-07-24 22:15   ` Andreas Färber
2018-07-22 21:20 ` [PATCH 05/15] MIPS: dts: img: pistachio_marduk: Enable SPIM0 Andreas Färber
2018-07-22 21:20 ` [PATCH 06/15] MIPS: dts: img: pistachio_marduk: Add 6Lowpan node Andreas Färber
2018-07-24  0:06   ` Paul Burton
2018-07-22 21:20 ` [PATCH 07/15] MIPS: dts: img: pistachio_marduk: Add SPI UART node Andreas Färber
2018-07-22 21:20 ` [PATCH 08/15] MIPS: dts: img: pistachio_marduk: Add user LEDs Andreas Färber
2018-07-22 21:20 ` [PATCH 09/15] dmaengine: img-mdc: Handle early status read Andreas Färber
2018-07-24 11:36   ` Vinod Koul
2018-07-22 21:20 ` [PATCH 10/15] spi: img-spfi: Implement dual and quad mode Andreas Färber
2018-07-30 15:30   ` Mark Brown [this message]
2018-07-22 21:20 ` [PATCH 11/15] spi: img-spfi: Set device select bits for SPFI port state Andreas Färber
2018-07-22 21:20 ` [PATCH 12/15] spi: img-spfi: Use device 0 configuration for all devices Andreas Färber
2018-07-22 21:20 ` [PATCH 13/15] spi: img-spfi: RX maximum burst size for DMA is 8 Andreas Färber
2018-07-30 15:34   ` Mark Brown
2018-07-22 21:20 ` [PATCH 14/15] spi: img-spfi: Finish every transfer cleanly Andreas Färber
2018-07-30 15:35   ` Mark Brown
2018-07-22 21:20 ` [PATCH 15/15] clk: pistachio: Fix wrong SDHost card speed Andreas Färber
2018-07-25 23:43   ` Stephen Boyd
2018-07-31 21:21   ` Rob Herring

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