From: Andi Kleen <ak@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Kan Liang <kan.liang@linux.intel.com>,
peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
linux-kernel@vger.kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont
Date: Wed, 3 Oct 2018 07:33:00 -0700 [thread overview]
Message-ID: <20181003143300.GH32651@tassilo.jf.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1810030803260.1435@nanos.tec.linutronix.de>
> There is another variant of model/stepping micro code verification code in
> intel_snb_pebs_broken(). Can we please make this table based and use a
> common function? That's certainly not the last quirk we're going to have.
I have a patch to add a table driven microcode matcher for another fix.
Will post shortly.
-Andi
next prev parent reply other threads:[~2018-10-03 14:33 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 21:30 [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont kan.liang
2018-10-03 6:10 ` Thomas Gleixner
2018-10-03 13:32 ` Liang, Kan
2018-10-03 13:55 ` Thomas Gleixner
2018-10-03 14:15 ` Liang, Kan
2018-10-03 14:24 ` Thomas Gleixner
2018-10-03 14:25 ` Liang, Kan
2018-10-03 14:27 ` Borislav Petkov
2018-10-03 14:33 ` Andi Kleen [this message]
2018-10-03 15:41 ` Peter Zijlstra
2018-10-03 15:49 ` Borislav Petkov
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