From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Kan Liang <kan.liang@linux.intel.com>,
mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org,
eranian@google.com, ak@linux.intel.com,
alexander.shishkin@linux.intel.com
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont
Date: Wed, 3 Oct 2018 17:41:32 +0200 [thread overview]
Message-ID: <20181003154132.GA19272@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <alpine.DEB.2.21.1810030803260.1435@nanos.tec.linutronix.de>
On Wed, Oct 03, 2018 at 08:10:31AM +0200, Thomas Gleixner wrote:
> On Tue, 2 Oct 2018, kan.liang@linux.intel.com wrote:
>
> There is another variant of model/stepping micro code verification code in
> intel_snb_pebs_broken(). Can we please make this table based and use a
> common function? That's certainly not the last quirk we're going to have.
>
> We already have a table based variant of ucode checking in
> bad_spectre_microcode(). It's trivial enough to generalize that.
apic_check_deadline_errata() is another one. That one already uses the
x86_cpu_id thing, but still plays silly games for steppings. So if we're
going to build a new microcode table matcher...
next prev parent reply other threads:[~2018-10-03 15:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 21:30 [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont kan.liang
2018-10-03 6:10 ` Thomas Gleixner
2018-10-03 13:32 ` Liang, Kan
2018-10-03 13:55 ` Thomas Gleixner
2018-10-03 14:15 ` Liang, Kan
2018-10-03 14:24 ` Thomas Gleixner
2018-10-03 14:25 ` Liang, Kan
2018-10-03 14:27 ` Borislav Petkov
2018-10-03 14:33 ` Andi Kleen
2018-10-03 15:41 ` Peter Zijlstra [this message]
2018-10-03 15:49 ` Borislav Petkov
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