* [PATCH v3] ARM: imx6plus: enable internal routing of clk_enet_ref where possible
@ 2020-06-24 15:22 Sven Van Asbroeck
2020-06-24 17:55 ` Fabio Estevam
0 siblings, 1 reply; 3+ messages in thread
From: Sven Van Asbroeck @ 2020-06-24 15:22 UTC (permalink / raw)
To: shawnguo, fugang.duan
Cc: Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-arm-kernel, linux-kernel
On imx6, the ethernet reference clock (clk_enet_ref) can be generated
by either the imx6, or an external source (e.g. an oscillator or the
PHY). When generated by the imx6, the clock source (from ANATOP)
must be routed to the input of clk_enet_ref via two pads on the SoC,
typically via a dedicated track on the PCB.
On an imx6 plus however, there is a new setting which enables this
clock to be routed internally on the SoC, from its ANATOP clock
source, straight to clk_enet_ref, without having to go through
the SoC pads.
Board designs where the clock is generated by the imx6 should not
be affected by routing the clock internally. Therefore on a plus,
we can enable internal routing by default.
Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
---
v2 -> v3:
- remove check for imx6q, which is already implied when
of_machine_is_compatible("fsl,imx6qp")
v1 -> v2:
- Fabio Estevam: use of_machine_is_compatible() to determine if we
are running on an imx6 plus.
To: Shawn Guo <shawnguo@kernel.org>
To: Andy Duan <fugang.duan@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 85c084a716ab..a760779b934e 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void)
else
pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+ /*
+ * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to
+ * be the PTP clock source, instead of having to be routed through
+ * pads.
+ * Board designs which route the ANATOP/CCM clock through pads are
+ * unaffected when routing happens internally. So on these designs,
+ * route internally by default.
+ */
+ if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP &&
+ of_machine_is_compatible("fsl,imx6qp")) {
+ if (!IS_ERR(gpr))
+ regmap_update_bits(gpr, IOMUXC_GPR5,
+ IMX6Q_GPR5_ENET_TXCLK_SEL,
+ IMX6Q_GPR5_ENET_TXCLK_SEL);
+ else
+ pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+ }
+
clk_put(enet_ref);
put_ptp_clk:
clk_put(ptp_clk);
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d4b5e527a7a3..eb65d48da0df 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -240,6 +240,7 @@
#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9)
#define IMX6Q_GPR5_SATA_SW_PD BIT(10)
#define IMX6Q_GPR5_SATA_SW_RST BIT(11)
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3] ARM: imx6plus: enable internal routing of clk_enet_ref where possible
2020-06-24 15:22 [PATCH v3] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Sven Van Asbroeck
@ 2020-06-24 17:55 ` Fabio Estevam
2020-06-24 18:24 ` Sven Van Asbroeck
0 siblings, 1 reply; 3+ messages in thread
From: Fabio Estevam @ 2020-06-24 17:55 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: Shawn Guo, Fugang Duan, Sascha Hauer, Pengutronix Kernel Team,
NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
Hi Sven,
On Wed, Jun 24, 2020 at 12:23 PM Sven Van Asbroeck <thesven73@gmail.com> wrote:
> + /*
> + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to
> + * be the PTP clock source, instead of having to be routed through
> + * pads.
> + * Board designs which route the ANATOP/CCM clock through pads are
> + * unaffected when routing happens internally. So on these designs,
> + * route internally by default.
> + */
> + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP &&
> + of_machine_is_compatible("fsl,imx6qp")) {
> + if (!IS_ERR(gpr))
We could avoid checking for if (!IS_ERR(gpr)) two times in a row if
the following patch is applied before yours:
https://pastebin.com/raw/Ftkq2VVp
What do you think?
Thanks
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3] ARM: imx6plus: enable internal routing of clk_enet_ref where possible
2020-06-24 17:55 ` Fabio Estevam
@ 2020-06-24 18:24 ` Sven Van Asbroeck
0 siblings, 0 replies; 3+ messages in thread
From: Sven Van Asbroeck @ 2020-06-24 18:24 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Fugang Duan, Sascha Hauer, Pengutronix Kernel Team,
NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
Hi Fabio,
On Wed, Jun 24, 2020 at 1:55 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> We could avoid checking for if (!IS_ERR(gpr)) two times in a row if
> the following patch is applied before yours:
> https://pastebin.com/raw/Ftkq2VVp
>
> What do you think?
I think this is a good idea.
I was never fully comfortable with checking IS_ERR(gpr) twice, but I
know from experience that minimal patches are more likely
to be accepted.
Shawn / Andy, what do you think? Should I re-spin this as a patch
set, with Fabio's patch in front?
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-06-24 15:22 [PATCH v3] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Sven Van Asbroeck
2020-06-24 17:55 ` Fabio Estevam
2020-06-24 18:24 ` Sven Van Asbroeck
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