* [PATCH] MIPS: Loongson64: Add UART node for LS7A PCH
@ 2020-09-17 12:39 Tiezhu Yang
2020-09-21 20:25 ` Thomas Bogendoerfer
0 siblings, 1 reply; 2+ messages in thread
From: Tiezhu Yang @ 2020-09-17 12:39 UTC (permalink / raw)
To: Thomas Bogendoerfer, Rob Herring, Huacai Chen, Jiaxun Yang
Cc: linux-mips, devicetree, linux-kernel, Xuefeng Li
When I update the latest kernel on the Loongson platform used with
LS7A bridge chip, the serial console has no output, this is because
the machine uses LS7A UART0 instead of CPU UART0, add UART node for
LS7A PCH to enhance the compatibility.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 39 +++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index e574a06..f99a7a1 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -19,6 +19,45 @@
#interrupt-cells = <2>;
};
+ ls7a_uart0: serial@10080000 {
+ compatible = "ns16550a";
+ reg = <0 0x10080000 0 0x100>;
+ clock-frequency = <50000000>;
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ ls7a_uart1: serial@10080100 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x10080100 0 0x100>;
+ clock-frequency = <50000000>;
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ ls7a_uart2: serial@10080200 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x10080200 0 0x100>;
+ clock-frequency = <50000000>;
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ ls7a_uart3: serial@10080300 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x10080300 0 0x100>;
+ clock-frequency = <50000000>;
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
pci@1a000000 {
compatible = "loongson,ls7a-pci";
device_type = "pci";
--
2.1.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] MIPS: Loongson64: Add UART node for LS7A PCH
2020-09-17 12:39 [PATCH] MIPS: Loongson64: Add UART node for LS7A PCH Tiezhu Yang
@ 2020-09-21 20:25 ` Thomas Bogendoerfer
0 siblings, 0 replies; 2+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-21 20:25 UTC (permalink / raw)
To: Tiezhu Yang
Cc: Rob Herring, Huacai Chen, Jiaxun Yang, linux-mips, devicetree,
linux-kernel, Xuefeng Li
On Thu, Sep 17, 2020 at 08:39:01PM +0800, Tiezhu Yang wrote:
> When I update the latest kernel on the Loongson platform used with
> LS7A bridge chip, the serial console has no output, this is because
> the machine uses LS7A UART0 instead of CPU UART0, add UART node for
> LS7A PCH to enhance the compatibility.
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 39 +++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 2+ messages in thread
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