From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Cc: suzuki.poulose@arm.com, leo.yan@linaro.org,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
rdunlap@infradead.org
Subject: Re: [PATCH] coresight-pmu.h: Fix a typo
Date: Fri, 26 Mar 2021 09:32:13 -0600 [thread overview]
Message-ID: <20210326153213.GA2009902@xps15> (raw)
In-Reply-To: <20210326142244.17504-1-unixbhaskar@gmail.com>
Hi Bhaskar,
On Fri, Mar 26, 2021 at 07:52:44PM +0530, Bhaskar Chowdhury wrote:
>
> s/orignally/originally/
Even if the change is trivial this changelog is insufficient. Moreover, if you
found the problem with an automated tool, please add the name of the tool to the
changelog.
Thanks,
Mathieu
>
> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
> ---
> include/linux/coresight-pmu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
> index 4ac5c081af93..2d5c29e3cb8a 100644
> --- a/include/linux/coresight-pmu.h
> +++ b/include/linux/coresight-pmu.h
> @@ -14,7 +14,7 @@
> * Below are the definition of bit offsets for perf option, and works as
> * arbitrary values for all ETM versions.
> *
> - * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,
> + * Most of them are originally from ETMv3.5/PTM's ETMCR config, therefore,
> * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
> * directly use below macros as config bits.
> */
> --
> 2.26.2
>
next prev parent reply other threads:[~2021-03-26 15:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 14:22 [PATCH] coresight-pmu.h: Fix a typo Bhaskar Chowdhury
2021-03-26 15:32 ` Mathieu Poirier [this message]
2021-03-26 19:53 ` Bhaskar Chowdhury
2021-03-29 14:38 ` Mathieu Poirier
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