* [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported
@ 2023-03-18 2:48 Lu Baolu
2023-03-24 4:49 ` Tian, Kevin
0 siblings, 1 reply; 3+ messages in thread
From: Lu Baolu @ 2023-03-18 2:48 UTC (permalink / raw)
To: iommu
Cc: Joerg Roedel, Will Deacon, Robin Murphy, Kevin Tian,
Raghunathan Srinivasan, Jacob Pan, linux-kernel, Lu Baolu
The VT-d spec states (section 11.4.2) that hardware implementations
reporting second-stage translation support (SSTS) field as Clear also
report the SAGAW field as 0. Reflect this in the sanity check of
alloc_iommu().
Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by default")
Suggested-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/dmar.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index 6acfe879589c..23828d189c2a 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1071,7 +1071,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)
}
err = -EINVAL;
- if (cap_sagaw(iommu->cap) == 0) {
+ if (!cap_sagaw(iommu->cap) &&
+ (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) {
pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
iommu->name);
drhd->ignored = 1;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* RE: [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported
2023-03-18 2:48 [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported Lu Baolu
@ 2023-03-24 4:49 ` Tian, Kevin
2023-03-24 8:50 ` Baolu Lu
0 siblings, 1 reply; 3+ messages in thread
From: Tian, Kevin @ 2023-03-24 4:49 UTC (permalink / raw)
To: Lu Baolu, iommu@lists.linux.dev
Cc: Joerg Roedel, Will Deacon, Robin Murphy, Srinivasan, Raghunathan,
Jacob Pan, linux-kernel@vger.kernel.org
> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Saturday, March 18, 2023 10:48 AM
>
> The VT-d spec states (section 11.4.2) that hardware implementations
> reporting second-stage translation support (SSTS) field as Clear also
> report the SAGAW field as 0. Reflect this in the sanity check of
> alloc_iommu().
>
> Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by
> default")
> Suggested-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel/dmar.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index 6acfe879589c..23828d189c2a 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -1071,7 +1071,8 @@ static int alloc_iommu(struct dmar_drhd_unit
> *drhd)
> }
>
> err = -EINVAL;
> - if (cap_sagaw(iommu->cap) == 0) {
> + if (!cap_sagaw(iommu->cap) &&
> + (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) {
> pr_info("%s: No supported address widths. Not attempting
> DMA translation.\n",
> iommu->name);
> drhd->ignored = 1;
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
btw I wonder whether it's cleaner to record separate agaw values for
stage1/stage2 instead of picking a minimal set from both in
__iommu_calculate_sagaw().
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported
2023-03-24 4:49 ` Tian, Kevin
@ 2023-03-24 8:50 ` Baolu Lu
0 siblings, 0 replies; 3+ messages in thread
From: Baolu Lu @ 2023-03-24 8:50 UTC (permalink / raw)
To: Tian, Kevin, iommu@lists.linux.dev
Cc: baolu.lu, Joerg Roedel, Will Deacon, Robin Murphy,
Srinivasan, Raghunathan, Jacob Pan, linux-kernel@vger.kernel.org
On 2023/3/24 12:49, Tian, Kevin wrote:
>> From: Lu Baolu <baolu.lu@linux.intel.com>
>> Sent: Saturday, March 18, 2023 10:48 AM
>>
>> The VT-d spec states (section 11.4.2) that hardware implementations
>> reporting second-stage translation support (SSTS) field as Clear also
>> report the SAGAW field as 0. Reflect this in the sanity check of
>> alloc_iommu().
>>
>> Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by
>> default")
>> Suggested-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com>
>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>> ---
>> drivers/iommu/intel/dmar.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
>> index 6acfe879589c..23828d189c2a 100644
>> --- a/drivers/iommu/intel/dmar.c
>> +++ b/drivers/iommu/intel/dmar.c
>> @@ -1071,7 +1071,8 @@ static int alloc_iommu(struct dmar_drhd_unit
>> *drhd)
>> }
>>
>> err = -EINVAL;
>> - if (cap_sagaw(iommu->cap) == 0) {
>> + if (!cap_sagaw(iommu->cap) &&
>> + (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) {
>> pr_info("%s: No supported address widths. Not attempting
>> DMA translation.\n",
>> iommu->name);
>> drhd->ignored = 1;
>
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
>
> btw I wonder whether it's cleaner to record separate agaw values for
> stage1/stage2 instead of picking a minimal set from both in
> __iommu_calculate_sagaw().
That's better. The agaw could be picked according to which stage the
domain is used for translation.
Best regards,
baolu
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-03-18 2:48 [PATCH 1/1] iommu/vt-d: Allow zero SAGAW if second-stage not supported Lu Baolu
2023-03-24 4:49 ` Tian, Kevin
2023-03-24 8:50 ` Baolu Lu
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