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From: Bjorn Helgaas <helgaas@kernel.org>
To: Martin Mares <mj@ucw.cz>
Cc: "Pali Rohár" <pali@kernel.org>,
	"Gustavo Pimentel" <Gustavo.Pimentel@synopsys.com>,
	"Mateusz Nowicki" <mateusz.nowicki@solidigm.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>
Subject: [PATCH 6/8] lspci: Print PCIe Interrupt Message Numbers consistently
Date: Wed, 18 Oct 2023 11:08:34 -0500	[thread overview]
Message-ID: <20231018160836.1361510-7-helgaas@kernel.org> (raw)
In-Reply-To: <20231018160836.1361510-1-helgaas@kernel.org>

From: Bjorn Helgaas <bhelgaas@google.com>

Several Capabilities include MSI/MSI-X Interrupt Message Numbers, which
were decoded in various ways:

  - MSI %02x                             PCIe Capability
  - IntMsg %d                            AER Capability
  - INT Msg #%d                          DPC Capability
  - Interrupt Message Number %03x        SR-IOV Capability
  - Interrupt Message Number %03x        DOE Capability

Print them all using the same format:

  + IntMsgNum %d

This better matches the "Interrupt Message Number" terminology used in the
spec, e.g., PCIe r6.0, sec 7.5.3.2.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 ls-caps.c  | 2 +-
 ls-ecaps.c | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index 6c5b73bf2dca..fce9502bd29a 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1436,7 +1436,7 @@ cap_express(struct device *d, int where, int cap)
     default:
       printf("Unknown type %d", type);
   }
-  printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+  printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
   if (verbose < 2)
     return type;
 
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 6028607e8217..5bc7a6907349 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -191,7 +191,7 @@ cap_aer(struct device *d, int where, int type)
 
       l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
       printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
-	    "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
+	    "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
 	    FLAG(l, PCI_ERR_ROOT_COR_RCV),
 	    FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
 	    FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
@@ -221,7 +221,7 @@ static void cap_dpc(struct device *d, int where)
     return;
 
   l = get_conf_word(d, where + PCI_DPC_CAP);
-  printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
+  printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
     PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
     FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
 
@@ -371,7 +371,7 @@ cap_sriov(struct device *d, int where)
     return;
 
   l = get_conf_long(d, where + PCI_IOV_CAP);
-  printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
+  printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
 	FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
   w = get_conf_word(d, where + PCI_IOV_CTRL);
   printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
@@ -1394,7 +1394,7 @@ cap_doe(struct device *d, int where)
   printf("\t\tDOECap: IntSup%c\n",
 	 FLAG(l, PCI_DOE_CAP_INT_SUPP));
   if (l & PCI_DOE_CAP_INT_SUPP)
-    printf("\t\t\tInterrupt Message Number %03x\n",
+    printf("\t\t\tIntMsgNum %d\n",
 	   PCI_DOE_CAP_INT_MSG(l));
 
   l = get_conf_long(d, where + PCI_DOE_CTL);
-- 
2.34.1


  parent reply	other threads:[~2023-10-18 16:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-18 16:08 [PATCH 0/8] lspci: Decode more DevCtl2 fields Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 1/8] lspci: Reorder PCIe DevCtl2 fields to match spec Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 2/8] lspci: Decode PCIe DevCtl2 ID-Based Ordering Enables Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 3/8] lspci: Decode PCIe DevCtl2 Emergency Power Reduction Request Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 4/8] lspci: Decode PCIe DevCtl2 End-to-End TLP Prefix Blocking Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 5/8] lspci: Decode PCIe LnkCtl Link Disable as 'LnkDisable' Bjorn Helgaas
2023-10-18 16:08 ` Bjorn Helgaas [this message]
2023-10-18 16:08 ` [PATCH 7/8] lspci: Remove spurious colon (':') from PCIe PTM decoding Bjorn Helgaas
2023-10-18 16:08 ` [PATCH 8/8] setpci: Fix man page typo Bjorn Helgaas
2023-10-18 18:57 ` [PATCH 0/8] lspci: Decode more DevCtl2 fields Martin Mareš

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