[Patch v2 0/2] memory: tegra: Skip restricted register access from Guest

[Patch v2 0/2] memory: tegra: Skip restricted register access from Guest

[Sumit Gupta]

MC SID and Broadbast channel register access is restricted for Guest VM.
But the Tegra MC driver is considering both these regions as mandatory
and causes error on access. Change that to consider both the regions as
optional in SoC's from Tegra186 onwards. Then skip access to the
restricted registers from Guest if its region is not present in Guest DT
and hence not mapped.
Previously, the solution in [1] was not accepted. Now, handled the
problem with this alternate solution.

---
v1[1] -> v2:
- consider broadcast channel registers also as restricted along with sid.
- make sid and broadcast regions optional and access if present in dt.
- update the yaml file.

Sumit Gupta (2):
  dt-bindings: make sid and broadcast reg optional
  memory: tegra: make sid and broadcast regions optional

 .../nvidia,tegra186-mc.yaml                   | 18 +++++++--------
 drivers/memory/tegra/mc.c                     |  9 +++++++-
 drivers/memory/tegra/mc.h                     | 18 +++++++--------
 drivers/memory/tegra/tegra186.c               | 22 ++++++++++---------
 4 files changed, 38 insertions(+), 29 deletions(-)

[1] https://lore.kernel.org/lkml/20240206114852.8472-1-sumitg@nvidia.com/

-- 
2.17.1

[Patch v2 1/2] dt-bindings: make sid and broadcast reg optional

[Sumit Gupta]

MC SID and Broadbast channel register access is restricted for Guest VM.
Make both the regions as optional for SoC's from Tegra186 onwards.
Tegra MC driver will skip access to the restricted registers from Guest
if the respective regions are not present in the memory-controller node
of Guest DT.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
 .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..c52c259f7ec5 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -146,17 +146,17 @@ allOf:
     then:
       properties:
         reg:
-          maxItems: 6
+          maxItems: 4
           description: 5 memory controller channels and 1 for stream-id registers
 
         reg-names:
           items:
-            - const: sid
-            - const: broadcast
             - const: ch0
             - const: ch1
             - const: ch2
             - const: ch3
+            - const: sid
+            - const: broadcast
 
   - if:
       properties:
@@ -165,13 +165,11 @@ allOf:
     then:
       properties:
         reg:
-          minItems: 18
+          minItems: 16
           description: 17 memory controller channels and 1 for stream-id registers
 
         reg-names:
           items:
-            - const: sid
-            - const: broadcast
             - const: ch0
             - const: ch1
             - const: ch2
@@ -188,6 +186,8 @@ allOf:
             - const: ch13
             - const: ch14
             - const: ch15
+            - const: sid
+            - const: broadcast
 
   - if:
       properties:
@@ -196,13 +196,11 @@ allOf:
     then:
       properties:
         reg:
-          minItems: 18
+          minItems: 16
           description: 17 memory controller channels and 1 for stream-id registers
 
         reg-names:
           items:
-            - const: sid
-            - const: broadcast
             - const: ch0
             - const: ch1
             - const: ch2
@@ -219,6 +217,8 @@ allOf:
             - const: ch13
             - const: ch14
             - const: ch15
+            - const: sid
+            - const: broadcast
 
 additionalProperties: false
 
-- 
2.17.1

Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional

[Rob Herring]

On Tue, 02 Apr 2024 18:56:25 +0530, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
> Make both the regions as optional for SoC's from Tegra186 onwards.
> Tegra MC driver will skip access to the restricted registers from Guest
> if the respective regions are not present in the memory-controller node
> of Guest DT.
> 
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
>  .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg: [[0, 46137344, 0, 65536], [0, 46202880, 0, 65536], [0, 46268416, 0, 65536], [0, 46333952, 0, 65536], [0, 46399488, 0, 65536], [0, 46465024, 0, 65536]] is too long
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:0: 'ch0' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:1: 'ch1' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:2: 'ch2' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:3: 'ch3' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:4: 'sid' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:5: 'broadcast' was expected
	from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240402132626.24693-2-sumitg@nvidia.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional

[Jon Hunter]

On 02/04/2024 14:26, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
> Make both the regions as optional for SoC's from Tegra186 onwards.
> Tegra MC driver will skip access to the restricted registers from Guest
> if the respective regions are not present in the memory-controller node
> of Guest DT.
> 
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
>   .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> index 935d63d181d9..c52c259f7ec5 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> @@ -146,17 +146,17 @@ allOf:
>       then:
>         properties:
>           reg:
> -          maxItems: 6
> +          maxItems: 4

minItems?

Jon

-- 
nvpublic

Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional

[Krzysztof Kozlowski]

On 02/04/2024 21:15, Jon Hunter wrote:
> 
> 
> On 02/04/2024 14:26, Sumit Gupta wrote:
>> MC SID and Broadbast channel register access is restricted for Guest VM.
>> Make both the regions as optional for SoC's from Tegra186 onwards.
>> Tegra MC driver will skip access to the restricted registers from Guest
>> if the respective regions are not present in the memory-controller node
>> of Guest DT.
>>
>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>> ---
>>   .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
>>   1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>> index 935d63d181d9..c52c259f7ec5 100644
>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>> @@ -146,17 +146,17 @@ allOf:
>>       then:
>>         properties:
>>           reg:
>> -          maxItems: 6
>> +          maxItems: 4
> 
> minItems?
> 

If the intention was to make it variable, then yes, missing minItems.
But more important: why patch was sent without any testing?

Best regards,
Krzysztof

Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional

[Sumit Gupta]

>>
>> On 02/04/2024 14:26, Sumit Gupta wrote:
>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>> Tegra MC driver will skip access to the restricted registers from Guest
>>> if the respective regions are not present in the memory-controller node
>>> of Guest DT.
>>>
>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>> ---
>>>    .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
>>>    1 file changed, 9 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> index 935d63d181d9..c52c259f7ec5 100644
>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> @@ -146,17 +146,17 @@ allOf:
>>>        then:
>>>          properties:
>>>            reg:
>>> -          maxItems: 6
>>> +          maxItems: 4
>>
>> minItems?
>>
> 
> If the intention was to make it variable, then yes, missing minItems.
> But more important: why patch was sent without any testing?
> 
> Best regards,
> Krzysztof
> 

I tested yaml file after doing the change for Tegra194 and Tegra234.
Changed the Tegra186 entry later and didn't verify that. My bad as
missed the obvious. Will correct the yaml file and send v3.

Will wait if any comments on 'Patch 2' before sending v3.

Best Regards,
Sumit Gupta

[Patch v2 2/2] memory: tegra: make sid and broadcast regions optional

[Sumit Gupta]

MC SID and Broadbast channel register access is restricted for Guest VM.
In Tegra MC driver, consider both the regions as optional and skip
access to restricted registers from Guest if a region is not present
in Guest DT.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
 drivers/memory/tegra/mc.c       |  9 ++++++++-
 drivers/memory/tegra/mc.h       | 18 +++++++++---------
 drivers/memory/tegra/tegra186.c | 22 ++++++++++++----------
 3 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 224b488794e5..d819dab1b223 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -899,6 +899,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
 
 static int tegra_mc_probe(struct platform_device *pdev)
 {
+	struct resource *res;
 	struct tegra_mc *mc;
 	u64 mask;
 	int err;
@@ -923,7 +924,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
 	/* length of MC tick in nanoseconds */
 	mc->tick = 30;
 
-	mc->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (mc->soc->num_channels) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
+		if (res)
+			mc->regs = devm_ioremap_resource(&pdev->dev, res);
+	} else {
+		mc->regs = devm_platform_ioremap_resource(pdev, 0);
+	}
 	if (IS_ERR(mc->regs))
 		return PTR_ERR(mc->regs);
 
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index c3f6655bec60..5cdb9451f364 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -112,11 +112,11 @@ icc_provider_to_tegra_mc(struct icc_provider *provider)
 static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
 			      unsigned long offset)
 {
-	if (!mc->bcast_ch_regs)
-		return 0;
-
-	if (ch == MC_BROADCAST_CHANNEL)
+	if (ch == MC_BROADCAST_CHANNEL) {
+		if (!mc->bcast_ch_regs)
+			return 0;
 		return readl_relaxed(mc->bcast_ch_regs + offset);
+	}
 
 	return readl_relaxed(mc->ch_regs[ch] + offset);
 }
@@ -124,13 +124,13 @@ static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
 				u32 value, unsigned long offset)
 {
-	if (!mc->bcast_ch_regs)
-		return;
-
-	if (ch == MC_BROADCAST_CHANNEL)
+	if (ch == MC_BROADCAST_CHANNEL) {
+		if (!mc->bcast_ch_regs)
+			return;
 		writel_relaxed(value, mc->bcast_ch_regs + offset);
-	else
+	} else {
 		writel_relaxed(value, mc->ch_regs[ch] + offset);
+	}
 }
 
 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 1b3183951bfe..7b5e9bd13ffd 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -26,20 +26,16 @@
 static int tegra186_mc_probe(struct tegra_mc *mc)
 {
 	struct platform_device *pdev = to_platform_device(mc->dev);
+	struct resource *res;
 	unsigned int i;
 	char name[8];
 	int err;
 
-	mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
-	if (IS_ERR(mc->bcast_ch_regs)) {
-		if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
-			dev_warn(&pdev->dev,
-				 "Broadcast channel is missing, please update your device-tree\n");
-			mc->bcast_ch_regs = NULL;
-			goto populate;
-		}
-
-		return PTR_ERR(mc->bcast_ch_regs);
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "broadcast");
+	if (res) {
+		mc->bcast_ch_regs = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(mc->bcast_ch_regs))
+			return PTR_ERR(mc->bcast_ch_regs);
 	}
 
 	mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
@@ -121,6 +117,9 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
 	if (!tegra_dev_iommu_get_stream_id(dev, &sid))
 		return 0;
 
+	if (!mc->regs)
+		return 0;
+
 	while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
 					   index, &args)) {
 		if (args.np == mc->dev->of_node && args.args_count != 0) {
@@ -146,6 +145,9 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
 #if IS_ENABLED(CONFIG_IOMMU_API)
 	unsigned int i;
 
+	if (!mc->regs)
+		return 0;
+
 	for (i = 0; i < mc->soc->num_clients; i++) {
 		const struct tegra_mc_client *client = &mc->soc->clients[i];
 
-- 
2.17.1