Re: [PATCH v2, 2/3] usb: dwc3: core: add p3p2tranok quirk

[Thinh Nguyen <Thinh.Nguyen@synopsys.com>]

Sorry for the delay response regarding this.

On Wed, Jun 19, 2024, joswang wrote:
> Hi Thinh
> 
> The workaround solution provided by your company for this issue is as follows:
>   Workaround：if the phy support direct P3 to P2 transition，program
> GUSB3PIPECTL.P3P2Tranok=1
> 
> As the databook mentions:
> This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
> This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
> 
> For Synopsys PHY, if this bit is set to "1", will it cause unknown problems?
> Please help confirm this, thank you!
> 

That depends on what your use case and requirements are.

I've reviewed this case. The impact to this issue is that power state
change may take longer than expected. It may violate the PIPE spec, but
functionally, at least for how linux drivers are handled, I'm not clear
on how this will impact the typical user.

Can you help clarify your use case and what does this resolve beside the
fact that it workaround the increase latency/response time.

Thanks,
Thinh