* [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs
@ 2024-07-30 18:54 Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Avadhut Naik @ 2024-07-30 18:54 UTC (permalink / raw)
To: x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: linux-kernel, bp, tony.luck, rafael, tglx, mingo, rostedt, lenb,
mchehab, james.morse, airlied, yazen.ghannam, john.allen,
avadnaik
This patchset adds a new wrapper for struct mce to prevent its bloating
and export vendor specific error information. Additionally, support is
also introduced for two new "syndrome" MSRs used in newer AMD Scalable
MCA (SMCA) systems. Also, a new "FRU Text in MCA" feature that uses these
new "syndrome" MSRs has been addded.
Patch 1 adds the new wrapper structure mce_hw_err for the struct mce
while also modifying the mce_record tracepoint to use the new wrapper.
Patch 2 adds support for the new "syndrome" registers. They are read/printed
wherever the existing MCA_SYND register is used.
Patch 3 updates the function that pulls MCA information from UEFI x86
Common Platform Error Records (CPERs) to handle systems that support the
new registers.
Patch 4 adds support to the AMD MCE decoder module to detect and use the
"FRU Text in MCA" feature which leverages the new registers.
NOTE:
This set was initially submitted as part of the larger MCA Updates set.
v1: https://lore.kernel.org/linux-edac/20231118193248.1296798-1-yazen.ghannam@amd.com/
v2: https://lore.kernel.org/linux-edac/20240404151359.47970-1-yazen.ghannam@amd.com/
However, since the MCA Updates set has been split up into smaller sets,
this set, going forward, will be submitted independently.
Having said that, this set set depends on and applies cleanly on top of
the below two sets.
[1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghannam@amd.com/
[2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghannam@amd.com/
Changes in v2:
- Drop dependencies on sets [1] and [2] above and rebase on top of
tip/master.
Changes in v3:
- Move wrapper changes required in mce_read_aux() and mce_no_way_out()
from second patch to the first patch.
- Modify commit messages for second and fourth patch per feedback
received.
- Add comments to explain purpose of the new wrapper structure.
- Incorporate suggested touchup in the third patch.
- Remove call to memset() for the frutext string in the fourth patch.
Instead, just ensure that the string is NULL terminated.
- Fix SoB chains on all patches to properly reflect the patch path.
Links:
v1: https://lore.kernel.org/linux-edac/20240530211620.1829453-1-avadhut.naik@amd.com/
v2: https://lore.kernel.org/linux-edac/20240625195624.2565741-1-avadhut.naik@amd.com/
Avadhut Naik (2):
x86/mce: Add wrapper for struct mce to export vendor specific info
x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers
Yazen Ghannam (2):
x86/mce/apei: Handle variable register array size
EDAC/mce_amd: Add support for FRU Text in MCA
arch/x86/include/asm/mce.h | 34 +++-
arch/x86/include/uapi/asm/mce.h | 3 +-
arch/x86/kernel/cpu/mce/amd.c | 33 ++--
arch/x86/kernel/cpu/mce/apei.c | 118 ++++++++++----
arch/x86/kernel/cpu/mce/core.c | 201 ++++++++++++++----------
arch/x86/kernel/cpu/mce/dev-mcelog.c | 2 +-
arch/x86/kernel/cpu/mce/genpool.c | 20 +--
arch/x86/kernel/cpu/mce/inject.c | 4 +-
arch/x86/kernel/cpu/mce/internal.h | 4 +-
drivers/acpi/acpi_extlog.c | 2 +-
drivers/acpi/nfit/mce.c | 2 +-
drivers/edac/i7core_edac.c | 2 +-
drivers/edac/igen6_edac.c | 2 +-
drivers/edac/mce_amd.c | 27 +++-
drivers/edac/pnd2_edac.c | 2 +-
drivers/edac/sb_edac.c | 2 +-
drivers/edac/skx_common.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
drivers/ras/amd/fmpm.c | 2 +-
drivers/ras/cec.c | 2 +-
include/trace/events/mce.h | 51 +++---
21 files changed, 331 insertions(+), 186 deletions(-)
base-commit: dee974604f7870167161cbe51e8f3b9c2858de34
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info
2024-07-30 18:54 [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
@ 2024-07-30 18:54 ` Avadhut Naik
2024-08-03 15:24 ` kernel test robot
2024-07-30 18:54 ` [PATCH v3 2/4] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Avadhut Naik
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Avadhut Naik @ 2024-07-30 18:54 UTC (permalink / raw)
To: x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: linux-kernel, bp, tony.luck, rafael, tglx, mingo, rostedt, lenb,
mchehab, james.morse, airlied, yazen.ghannam, john.allen,
avadnaik
Currently, exporting new additional machine check error information
involves adding new fields for the same at the end of the struct mce.
This additional information can then be consumed through mcelog or
tracepoint.
However, as new MSRs are being added (and will be added in the future)
by CPU vendors on their newer CPUs with additional machine check error
information to be exported, the size of struct mce will balloon on some
CPUs, unnecessarily, since those fields are vendor-specific. Moreover,
different CPU vendors may export the additional information in varying
sizes.
The problem particularly intensifies since struct mce is exposed to
userspace as part of UAPI. It's bloating through vendor-specific data
should be avoided to limit the information being sent out to userspace.
Add a new structure mce_hw_err to wrap the existing struct mce. The same
will prevent its ballooning since vendor-specifc data, if any, can now be
exported through a union within the wrapper structure and through
__dynamic_array in mce_record tracepoint.
Furthermore, new internal kernel fields can be added to the wrapper
struct without impacting the user space API.
[Yazen: Add last commit message paragraph.]
Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
Changes in v2:
[1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghannam@amd.com/
[2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghannam@amd.com/
1. Drop dependencies on sets [1] and [2] above and rebase on top of
tip/master.
Changes in v3:
1. Move wrapper changes required in mce_read_aux() and mce_no_way_out()
to this patch from the second patch.
2. Fix SoB chain to properly reflect the patch path.
---
arch/x86/include/asm/mce.h | 10 +-
arch/x86/kernel/cpu/mce/amd.c | 29 ++--
arch/x86/kernel/cpu/mce/apei.c | 54 ++++---
arch/x86/kernel/cpu/mce/core.c | 189 ++++++++++++++----------
arch/x86/kernel/cpu/mce/dev-mcelog.c | 2 +-
arch/x86/kernel/cpu/mce/genpool.c | 20 +--
arch/x86/kernel/cpu/mce/inject.c | 4 +-
arch/x86/kernel/cpu/mce/internal.h | 4 +-
drivers/acpi/acpi_extlog.c | 2 +-
drivers/acpi/nfit/mce.c | 2 +-
drivers/edac/i7core_edac.c | 2 +-
drivers/edac/igen6_edac.c | 2 +-
drivers/edac/mce_amd.c | 2 +-
drivers/edac/pnd2_edac.c | 2 +-
drivers/edac/sb_edac.c | 2 +-
drivers/edac/skx_common.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
drivers/ras/amd/fmpm.c | 2 +-
drivers/ras/cec.c | 2 +-
include/trace/events/mce.h | 42 +++---
20 files changed, 210 insertions(+), 166 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 3ad29b128943..ba2b3a5f999e 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -187,6 +187,14 @@ enum mce_notifier_prios {
MCE_PRIO_HIGHEST = MCE_PRIO_CEC
};
+/**
+ * struct mce_hw_err - Hardware Error Record.
+ * @m: Machine Check record.
+ */
+struct mce_hw_err {
+ struct mce m;
+};
+
struct notifier_block;
extern void mce_register_decode_chain(struct notifier_block *nb);
extern void mce_unregister_decode_chain(struct notifier_block *nb);
@@ -222,7 +230,7 @@ static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
#endif
void mce_setup(struct mce *m);
-void mce_log(struct mce *m);
+void mce_log(struct mce_hw_err *err);
DECLARE_PER_CPU(struct device *, mce_device);
/* Maximum number of MCA banks per CPU. */
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 9a0133ef7e20..cb7dc0b1aa50 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -778,29 +778,32 @@ bool amd_mce_usable_address(struct mce *m)
static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
{
- struct mce m;
+ struct mce_hw_err err;
+ struct mce *m = &err.m;
- mce_setup(&m);
+ memset(&err, 0, sizeof(struct mce_hw_err));
- m.status = status;
- m.misc = misc;
- m.bank = bank;
- m.tsc = rdtsc();
+ mce_setup(m);
- if (m.status & MCI_STATUS_ADDRV) {
- m.addr = addr;
+ m->status = status;
+ m->misc = misc;
+ m->bank = bank;
+ m->tsc = rdtsc();
- smca_extract_err_addr(&m);
+ if (m->status & MCI_STATUS_ADDRV) {
+ m->addr = addr;
+
+ smca_extract_err_addr(m);
}
if (mce_flags.smca) {
- rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
+ rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);
- if (m.status & MCI_STATUS_SYNDV)
- rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
+ if (m->status & MCI_STATUS_SYNDV)
+ rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);
}
- mce_log(&m);
+ mce_log(&err);
}
DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
index 7f7309ff67d0..b8f4e75fb8a7 100644
--- a/arch/x86/kernel/cpu/mce/apei.c
+++ b/arch/x86/kernel/cpu/mce/apei.c
@@ -28,9 +28,12 @@
void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
{
- struct mce m;
+ struct mce_hw_err err;
+ struct mce *m = &err.m;
int lsb;
+ memset(&err, 0, sizeof(struct mce_hw_err));
+
if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
return;
@@ -44,30 +47,33 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
else
lsb = PAGE_SHIFT;
- mce_setup(&m);
- m.bank = -1;
+ mce_setup(m);
+ m->bank = -1;
/* Fake a memory read error with unknown channel */
- m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
- m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb;
+ m->status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
+ m->misc = (MCI_MISC_ADDR_PHYS << 6) | lsb;
if (severity >= GHES_SEV_RECOVERABLE)
- m.status |= MCI_STATUS_UC;
+ m->status |= MCI_STATUS_UC;
if (severity >= GHES_SEV_PANIC) {
- m.status |= MCI_STATUS_PCC;
- m.tsc = rdtsc();
+ m->status |= MCI_STATUS_PCC;
+ m->tsc = rdtsc();
}
- m.addr = mem_err->physical_addr;
- mce_log(&m);
+ m->addr = mem_err->physical_addr;
+ mce_log(&err);
}
EXPORT_SYMBOL_GPL(apei_mce_report_mem_error);
int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
{
const u64 *i_mce = ((const u64 *) (ctx_info + 1));
+ struct mce_hw_err err;
+ struct mce *m = &err.m;
unsigned int cpu;
- struct mce m;
+
+ memset(&err, 0, sizeof(struct mce_hw_err));
if (!boot_cpu_has(X86_FEATURE_SMCA))
return -EINVAL;
@@ -97,29 +103,29 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
if (ctx_info->reg_arr_size < 48)
return -EINVAL;
- mce_setup(&m);
+ mce_setup(m);
- m.extcpu = -1;
- m.socketid = -1;
+ m->extcpu = -1;
+ m->socketid = -1;
for_each_possible_cpu(cpu) {
if (cpu_data(cpu).topo.initial_apicid == lapic_id) {
- m.extcpu = cpu;
- m.socketid = cpu_data(m.extcpu).topo.pkg_id;
+ m->extcpu = cpu;
+ m->socketid = cpu_data(m->extcpu).topo.pkg_id;
break;
}
}
- m.apicid = lapic_id;
- m.bank = (ctx_info->msr_addr >> 4) & 0xFF;
- m.status = *i_mce;
- m.addr = *(i_mce + 1);
- m.misc = *(i_mce + 2);
+ m->apicid = lapic_id;
+ m->bank = (ctx_info->msr_addr >> 4) & 0xFF;
+ m->status = *i_mce;
+ m->addr = *(i_mce + 1);
+ m->misc = *(i_mce + 2);
/* Skipping MCA_CONFIG */
- m.ipid = *(i_mce + 4);
- m.synd = *(i_mce + 5);
+ m->ipid = *(i_mce + 4);
+ m->synd = *(i_mce + 5);
- mce_log(&m);
+ mce_log(&err);
return 0;
}
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index b85ec7a4ec9e..ab9f1d606438 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -88,7 +88,7 @@ struct mca_config mca_cfg __read_mostly = {
.monarch_timeout = -1
};
-static DEFINE_PER_CPU(struct mce, mces_seen);
+static DEFINE_PER_CPU(struct mce_hw_err, hw_errs_seen);
static unsigned long mce_need_notify;
/*
@@ -136,9 +136,9 @@ void mce_setup(struct mce *m)
DEFINE_PER_CPU(struct mce, injectm);
EXPORT_PER_CPU_SYMBOL_GPL(injectm);
-void mce_log(struct mce *m)
+void mce_log(struct mce_hw_err *err)
{
- if (!mce_gen_pool_add(m))
+ if (!mce_gen_pool_add(err))
irq_work_queue(&mce_irq_work);
}
EXPORT_SYMBOL_GPL(mce_log);
@@ -159,8 +159,10 @@ void mce_unregister_decode_chain(struct notifier_block *nb)
}
EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
-static void __print_mce(struct mce *m)
+static void __print_mce(struct mce_hw_err *err)
{
+ struct mce *m = &err->m;
+
pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
m->extcpu,
(m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
@@ -202,9 +204,11 @@ static void __print_mce(struct mce *m)
m->microcode);
}
-static void print_mce(struct mce *m)
+static void print_mce(struct mce_hw_err *err)
{
- __print_mce(m);
+ struct mce *m = &err->m;
+
+ __print_mce(err);
if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
@@ -239,7 +243,7 @@ static const char *mce_dump_aux_info(struct mce *m)
return NULL;
}
-static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
+static noinstr void mce_panic(const char *msg, struct mce_hw_err *final, char *exp)
{
struct llist_node *pending;
struct mce_evt_llist *l;
@@ -270,20 +274,22 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
pending = mce_gen_pool_prepare_records();
/* First print corrected ones that are still unlogged */
llist_for_each_entry(l, pending, llnode) {
- struct mce *m = &l->mce;
+ struct mce_hw_err *err = &l->err;
+ struct mce *m = &err->m;
if (!(m->status & MCI_STATUS_UC)) {
- print_mce(m);
+ print_mce(err);
if (!apei_err)
apei_err = apei_write_mce(m);
}
}
/* Now print uncorrected but with the final one last */
llist_for_each_entry(l, pending, llnode) {
- struct mce *m = &l->mce;
+ struct mce_hw_err *err = &l->err;
+ struct mce *m = &err->m;
if (!(m->status & MCI_STATUS_UC))
continue;
- if (!final || mce_cmp(m, final)) {
- print_mce(m);
+ if (!final || mce_cmp(m, &final->m)) {
+ print_mce(err);
if (!apei_err)
apei_err = apei_write_mce(m);
}
@@ -291,12 +297,12 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
if (final) {
print_mce(final);
if (!apei_err)
- apei_err = apei_write_mce(final);
+ apei_err = apei_write_mce(&final->m);
}
if (exp)
pr_emerg(HW_ERR "Machine check: %s\n", exp);
- memmsg = mce_dump_aux_info(final);
+ memmsg = mce_dump_aux_info(&final->m);
if (memmsg)
pr_emerg(HW_ERR "Machine check: %s\n", memmsg);
@@ -311,9 +317,9 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
* panic.
*/
if (kexec_crash_loaded()) {
- if (final && (final->status & MCI_STATUS_ADDRV)) {
+ if (final && (final->m.status & MCI_STATUS_ADDRV)) {
struct page *p;
- p = pfn_to_online_page(final->addr >> PAGE_SHIFT);
+ p = pfn_to_online_page(final->m.addr >> PAGE_SHIFT);
if (p)
SetPageHWPoison(p);
}
@@ -562,13 +568,13 @@ EXPORT_SYMBOL_GPL(mce_is_correctable);
static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce_hw_err *err = (struct mce_hw_err *)data;
- if (!m)
+ if (!err)
return NOTIFY_DONE;
/* Emit the trace record: */
- trace_mce_record(m);
+ trace_mce_record(err);
set_bit(0, &mce_need_notify);
@@ -585,7 +591,8 @@ static struct notifier_block early_nb = {
static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce_hw_err *err = (struct mce_hw_err *)data;
+ struct mce *mce = &err->m;
unsigned long pfn;
if (!mce || !mce_usable_address(mce))
@@ -612,13 +619,13 @@ static struct notifier_block mce_uc_nb = {
static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce_hw_err *err = (struct mce_hw_err *)data;
- if (!m)
+ if (!err)
return NOTIFY_DONE;
- if (mca_cfg.print_all || !m->kflags)
- __print_mce(m);
+ if (mca_cfg.print_all || !(err->m.kflags))
+ __print_mce(err);
return NOTIFY_DONE;
}
@@ -632,8 +639,10 @@ static struct notifier_block mce_default_nb = {
/*
* Read ADDR and MISC registers.
*/
-static noinstr void mce_read_aux(struct mce *m, int i)
+static noinstr void mce_read_aux(struct mce_hw_err *err, int i)
{
+ struct mce *m = &err->m;
+
if (m->status & MCI_STATUS_MISCV)
m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
@@ -680,26 +689,29 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
{
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
- struct mce m;
+ struct mce_hw_err err;
+ struct mce *m = &err.m;
int i;
+ memset(&err, 0, sizeof(struct mce_hw_err));
+
this_cpu_inc(mce_poll_count);
- mce_gather_info(&m, NULL);
+ mce_gather_info(m, NULL);
if (flags & MCP_TIMESTAMP)
- m.tsc = rdtsc();
+ m->tsc = rdtsc();
for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
if (!mce_banks[i].ctl || !test_bit(i, *b))
continue;
- m.misc = 0;
- m.addr = 0;
- m.bank = i;
+ m->misc = 0;
+ m->addr = 0;
+ m->bank = i;
barrier();
- m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
+ m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
/*
* Update storm tracking here, before checking for the
@@ -709,17 +721,17 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
* storm status.
*/
if (!mca_cfg.cmci_disabled)
- mce_track_storm(&m);
+ mce_track_storm(m);
/* If this entry is not valid, ignore it */
- if (!(m.status & MCI_STATUS_VAL))
+ if (!(m->status & MCI_STATUS_VAL))
continue;
/*
* If we are logging everything (at CPU online) or this
* is a corrected error, then we must log it.
*/
- if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
+ if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC))
goto log_it;
/*
@@ -729,20 +741,20 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
* everything else.
*/
if (!mca_cfg.ser) {
- if (m.status & MCI_STATUS_UC)
+ if (m->status & MCI_STATUS_UC)
continue;
goto log_it;
}
/* Log "not enabled" (speculative) errors */
- if (!(m.status & MCI_STATUS_EN))
+ if (!(m->status & MCI_STATUS_EN))
goto log_it;
/*
* Log UCNA (SDM: 15.6.3 "UCR Error Classification")
* UC == 1 && PCC == 0 && S == 0
*/
- if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
+ if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S))
goto log_it;
/*
@@ -756,20 +768,20 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
if (flags & MCP_DONTLOG)
goto clear_it;
- mce_read_aux(&m, i);
- m.severity = mce_severity(&m, NULL, NULL, false);
+ mce_read_aux(&err, i);
+ m->severity = mce_severity(m, NULL, NULL, false);
/*
* Don't get the IP here because it's unlikely to
* have anything to do with the actual error location.
*/
- if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
+ if (mca_cfg.dont_log_ce && !mce_usable_address(m))
goto clear_it;
if (flags & MCP_QUEUE_LOG)
- mce_gen_pool_add(&m);
+ mce_gen_pool_add(&err);
else
- mce_log(&m);
+ mce_log(&err);
clear_it:
/*
@@ -893,9 +905,10 @@ static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_reg
* Do a quick check if any of the events requires a panic.
* This decides if we keep the events around or clear them.
*/
-static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
+static __always_inline int mce_no_way_out(struct mce_hw_err *err, char **msg, unsigned long *validp,
struct pt_regs *regs)
{
+ struct mce *m = &err->m;
char *tmp = *msg;
int i;
@@ -913,7 +926,7 @@ static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned lo
m->bank = i;
if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
- mce_read_aux(m, i);
+ mce_read_aux(err, i);
*msg = tmp;
return 1;
}
@@ -1005,6 +1018,7 @@ static noinstr int mce_timed_out(u64 *t, const char *msg)
static void mce_reign(void)
{
int cpu;
+ struct mce_hw_err *err = NULL;
struct mce *m = NULL;
int global_worst = 0;
char *msg = NULL;
@@ -1015,11 +1029,13 @@ static void mce_reign(void)
* Grade the severity of the errors of all the CPUs.
*/
for_each_possible_cpu(cpu) {
- struct mce *mtmp = &per_cpu(mces_seen, cpu);
+ struct mce_hw_err *etmp = &per_cpu(hw_errs_seen, cpu);
+ struct mce *mtmp = &etmp->m;
if (mtmp->severity > global_worst) {
global_worst = mtmp->severity;
- m = &per_cpu(mces_seen, cpu);
+ err = &per_cpu(hw_errs_seen, cpu);
+ m = &err->m;
}
}
@@ -1031,7 +1047,7 @@ static void mce_reign(void)
if (m && global_worst >= MCE_PANIC_SEVERITY) {
/* call mce_severity() to get "msg" for panic */
mce_severity(m, NULL, &msg, true);
- mce_panic("Fatal machine check", m, msg);
+ mce_panic("Fatal machine check", err, msg);
}
/*
@@ -1048,11 +1064,11 @@ static void mce_reign(void)
mce_panic("Fatal machine check from unknown source", NULL, NULL);
/*
- * Now clear all the mces_seen so that they don't reappear on
+ * Now clear all the hw_errs_seen so that they don't reappear on
* the next mce.
*/
for_each_possible_cpu(cpu)
- memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
+ memset(&per_cpu(hw_errs_seen, cpu), 0, sizeof(struct mce_hw_err));
}
static atomic_t global_nwo;
@@ -1256,12 +1272,13 @@ static noinstr bool mce_check_crashing_cpu(void)
}
static __always_inline int
-__mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
+__mc_scan_banks(struct mce_hw_err *err, struct pt_regs *regs, struct mce *final,
unsigned long *toclear, unsigned long *valid_banks, int no_way_out,
int *worst)
{
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
struct mca_config *cfg = &mca_cfg;
+ struct mce *m = &err->m;
int severity, i, taint = 0;
for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
@@ -1307,7 +1324,7 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
if (severity == MCE_NO_SEVERITY)
continue;
- mce_read_aux(m, i);
+ mce_read_aux(err, i);
/* assuming valid severity level != 0 */
m->severity = severity;
@@ -1317,7 +1334,7 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
* done in #MC context, where instrumentation is disabled.
*/
instrumentation_begin();
- mce_log(m);
+ mce_log(err);
instrumentation_end();
if (severity > *worst) {
@@ -1387,8 +1404,9 @@ static void kill_me_never(struct callback_head *cb)
set_mce_nospec(pfn);
}
-static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *))
+static void queue_task_work(struct mce_hw_err *err, char *msg, void (*func)(struct callback_head *))
{
+ struct mce *m = &err->m;
int count = ++current->mce_count;
/* First call, save all the details */
@@ -1402,11 +1420,12 @@ static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callba
/* Ten is likely overkill. Don't expect more than two faults before task_work() */
if (count > 10)
- mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
+ mce_panic("Too many consecutive machine checks while accessing user data",
+ err, msg);
/* Second or later call, make sure page address matches the one from first call */
if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
- mce_panic("Consecutive machine checks to different user pages", m, msg);
+ mce_panic("Consecutive machine checks to different user pages", err, msg);
/* Do not call task_work_add() more than once */
if (count > 1)
@@ -1455,8 +1474,14 @@ noinstr void do_machine_check(struct pt_regs *regs)
int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0;
DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 };
DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 };
- struct mce m, *final;
+ struct mce_hw_err *final;
+ struct mce_hw_err err;
char *msg = NULL;
+ struct mce *m;
+
+ memset(&err, 0, sizeof(struct mce_hw_err));
+
+ m = &err.m;
if (unlikely(mce_flags.p5))
return pentium_machine_check(regs);
@@ -1494,13 +1519,13 @@ noinstr void do_machine_check(struct pt_regs *regs)
this_cpu_inc(mce_exception_count);
- mce_gather_info(&m, regs);
- m.tsc = rdtsc();
+ mce_gather_info(m, regs);
+ m->tsc = rdtsc();
- final = this_cpu_ptr(&mces_seen);
- *final = m;
+ final = this_cpu_ptr(&hw_errs_seen);
+ final->m = *m;
- no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
+ no_way_out = mce_no_way_out(&err, &msg, valid_banks, regs);
barrier();
@@ -1509,15 +1534,15 @@ noinstr void do_machine_check(struct pt_regs *regs)
* Assume the worst for now, but if we find the
* severity is MCE_AR_SEVERITY we have other options.
*/
- if (!(m.mcgstatus & MCG_STATUS_RIPV))
+ if (!(m->mcgstatus & MCG_STATUS_RIPV))
kill_current_task = 1;
/*
* Check if this MCE is signaled to only this logical processor,
* on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL ||
- m.cpuvendor == X86_VENDOR_ZHAOXIN)
- lmce = m.mcgstatus & MCG_STATUS_LMCES;
+ if (m->cpuvendor == X86_VENDOR_INTEL ||
+ m->cpuvendor == X86_VENDOR_ZHAOXIN)
+ lmce = m->mcgstatus & MCG_STATUS_LMCES;
/*
* Local machine check may already know that we have to panic.
@@ -1528,12 +1553,12 @@ noinstr void do_machine_check(struct pt_regs *regs)
*/
if (lmce) {
if (no_way_out)
- mce_panic("Fatal local machine check", &m, msg);
+ mce_panic("Fatal local machine check", &err, msg);
} else {
order = mce_start(&no_way_out);
}
- taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
+ taint = __mc_scan_banks(&err, regs, &final->m, toclear, valid_banks, no_way_out, &worst);
if (!no_way_out)
mce_clear_state(toclear);
@@ -1548,7 +1573,7 @@ noinstr void do_machine_check(struct pt_regs *regs)
no_way_out = worst >= MCE_PANIC_SEVERITY;
if (no_way_out)
- mce_panic("Fatal machine check on current CPU", &m, msg);
+ mce_panic("Fatal machine check on current CPU", &err, msg);
}
} else {
/*
@@ -1560,8 +1585,8 @@ noinstr void do_machine_check(struct pt_regs *regs)
* make sure we have the right "msg".
*/
if (worst >= MCE_PANIC_SEVERITY) {
- mce_severity(&m, regs, &msg, true);
- mce_panic("Local fatal machine check!", &m, msg);
+ mce_severity(m, regs, &msg, true);
+ mce_panic("Local fatal machine check!", &err, msg);
}
}
@@ -1579,16 +1604,16 @@ noinstr void do_machine_check(struct pt_regs *regs)
goto out;
/* Fault was in user mode and we need to take some action */
- if ((m.cs & 3) == 3) {
+ if ((m->cs & 3) == 3) {
/* If this triggers there is no way to recover. Die hard. */
BUG_ON(!on_thread_stack() || !user_mode(regs));
- if (!mce_usable_address(&m))
- queue_task_work(&m, msg, kill_me_now);
+ if (!mce_usable_address(m))
+ queue_task_work(&err, msg, kill_me_now);
else
- queue_task_work(&m, msg, kill_me_maybe);
+ queue_task_work(&err, msg, kill_me_maybe);
- } else if (m.mcgstatus & MCG_STATUS_SEAM_NR) {
+ } else if (m->mcgstatus & MCG_STATUS_SEAM_NR) {
/*
* Saved RIP on stack makes it look like the machine check
* was taken in the kernel on the instruction following
@@ -1600,8 +1625,8 @@ noinstr void do_machine_check(struct pt_regs *regs)
* not occur there. Mark the page as poisoned so it won't
* be added to free list when the guest is terminated.
*/
- if (mce_usable_address(&m)) {
- struct page *p = pfn_to_online_page(m.addr >> PAGE_SHIFT);
+ if (mce_usable_address(m)) {
+ struct page *p = pfn_to_online_page(m->addr >> PAGE_SHIFT);
if (p)
SetPageHWPoison(p);
@@ -1616,13 +1641,13 @@ noinstr void do_machine_check(struct pt_regs *regs)
* corresponding exception handler which would do that is the
* proper one.
*/
- if (m.kflags & MCE_IN_KERNEL_RECOV) {
+ if (m->kflags & MCE_IN_KERNEL_RECOV) {
if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
- mce_panic("Failed kernel mode recovery", &m, msg);
+ mce_panic("Failed kernel mode recovery", &err, msg);
}
- if (m.kflags & MCE_IN_KERNEL_COPYIN)
- queue_task_work(&m, msg, kill_me_never);
+ if (m->kflags & MCE_IN_KERNEL_COPYIN)
+ queue_task_work(&err, msg, kill_me_never);
}
out:
diff --git a/arch/x86/kernel/cpu/mce/dev-mcelog.c b/arch/x86/kernel/cpu/mce/dev-mcelog.c
index a05ac0716ecf..4a0e3bb4a4fb 100644
--- a/arch/x86/kernel/cpu/mce/dev-mcelog.c
+++ b/arch/x86/kernel/cpu/mce/dev-mcelog.c
@@ -36,7 +36,7 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
static int dev_mce_log(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
unsigned int entry;
if (mce->kflags & MCE_HANDLED_CEC)
diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c
index 4284749ec803..3337ea5c428d 100644
--- a/arch/x86/kernel/cpu/mce/genpool.c
+++ b/arch/x86/kernel/cpu/mce/genpool.c
@@ -31,15 +31,15 @@ static LLIST_HEAD(mce_event_llist);
*/
static bool is_duplicate_mce_record(struct mce_evt_llist *t, struct mce_evt_llist *l)
{
+ struct mce_hw_err *err1, *err2;
struct mce_evt_llist *node;
- struct mce *m1, *m2;
- m1 = &t->mce;
+ err1 = &t->err;
llist_for_each_entry(node, &l->llnode, llnode) {
- m2 = &node->mce;
+ err2 = &node->err;
- if (!mce_cmp(m1, m2))
+ if (!mce_cmp(&err1->m, &err2->m))
return true;
}
return false;
@@ -73,9 +73,9 @@ struct llist_node *mce_gen_pool_prepare_records(void)
void mce_gen_pool_process(struct work_struct *__unused)
{
+ struct mce_hw_err *err;
struct llist_node *head;
struct mce_evt_llist *node, *tmp;
- struct mce *mce;
head = llist_del_all(&mce_event_llist);
if (!head)
@@ -83,8 +83,8 @@ void mce_gen_pool_process(struct work_struct *__unused)
head = llist_reverse_order(head);
llist_for_each_entry_safe(node, tmp, head, llnode) {
- mce = &node->mce;
- blocking_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
+ err = &node->err;
+ blocking_notifier_call_chain(&x86_mce_decoder_chain, 0, err);
gen_pool_free(mce_evt_pool, (unsigned long)node, sizeof(*node));
}
}
@@ -94,11 +94,11 @@ bool mce_gen_pool_empty(void)
return llist_empty(&mce_event_llist);
}
-int mce_gen_pool_add(struct mce *mce)
+int mce_gen_pool_add(struct mce_hw_err *err)
{
struct mce_evt_llist *node;
- if (filter_mce(mce))
+ if (filter_mce(&err->m))
return -EINVAL;
if (!mce_evt_pool)
@@ -110,7 +110,7 @@ int mce_gen_pool_add(struct mce *mce)
return -ENOMEM;
}
- memcpy(&node->mce, mce, sizeof(*mce));
+ memcpy(&node->err, err, sizeof(*err));
llist_add(&node->llnode, &mce_event_llist);
return 0;
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 49ed3428785d..c65a5c4e2f22 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -502,6 +502,7 @@ static void prepare_msrs(void *info)
static void do_inject(void)
{
+ struct mce_hw_err err;
u64 mcg_status = 0;
unsigned int cpu = i_mce.extcpu;
u8 b = i_mce.bank;
@@ -517,7 +518,8 @@ static void do_inject(void)
i_mce.status |= MCI_STATUS_SYNDV;
if (inj_type == SW_INJ) {
- mce_log(&i_mce);
+ err.m = i_mce;
+ mce_log(&err);
return;
}
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 01f8f03969e6..c79cb5b00e4c 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -26,12 +26,12 @@ extern struct blocking_notifier_head x86_mce_decoder_chain;
struct mce_evt_llist {
struct llist_node llnode;
- struct mce mce;
+ struct mce_hw_err err;
};
void mce_gen_pool_process(struct work_struct *__unused);
bool mce_gen_pool_empty(void);
-int mce_gen_pool_add(struct mce *mce);
+int mce_gen_pool_add(struct mce_hw_err *err);
int mce_gen_pool_init(void);
struct llist_node *mce_gen_pool_prepare_records(void);
diff --git a/drivers/acpi/acpi_extlog.c b/drivers/acpi/acpi_extlog.c
index ca87a0939135..4864191918db 100644
--- a/drivers/acpi/acpi_extlog.c
+++ b/drivers/acpi/acpi_extlog.c
@@ -134,7 +134,7 @@ static int print_extlog_rcd(const char *pfx,
static int extlog_print(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
int bank = mce->bank;
int cpu = mce->extcpu;
struct acpi_hest_generic_status *estatus, *tmp;
diff --git a/drivers/acpi/nfit/mce.c b/drivers/acpi/nfit/mce.c
index d48a388b796e..b917988db794 100644
--- a/drivers/acpi/nfit/mce.c
+++ b/drivers/acpi/nfit/mce.c
@@ -13,7 +13,7 @@
static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
struct acpi_nfit_desc *acpi_desc;
struct nfit_spa *nfit_spa;
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 91e0a88ef904..d1e47cba0ff2 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1810,7 +1810,7 @@ static void i7core_check_error(struct mem_ctl_info *mci, struct mce *m)
static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
struct i7core_dev *i7_dev;
struct mem_ctl_info *mci;
diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c
index 0fe75eed8973..d73e9f0600ee 100644
--- a/drivers/edac/igen6_edac.c
+++ b/drivers/edac/igen6_edac.c
@@ -919,7 +919,7 @@ static int ecclog_nmi_handler(unsigned int cmd, struct pt_regs *regs)
static int ecclog_mce_handler(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
char *type;
if (mce->kflags & MCE_HANDLED_CEC)
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 8130c3dc64da..c5fae99de781 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -792,7 +792,7 @@ static const char *decode_error_status(struct mce *m)
static int
amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce *m = &((struct mce_hw_err *)data)->m;
unsigned int fam = x86_family(m->cpuid);
int ecc;
diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c
index f93f2f2b1cf2..a3008f6eb2b1 100644
--- a/drivers/edac/pnd2_edac.c
+++ b/drivers/edac/pnd2_edac.c
@@ -1366,7 +1366,7 @@ static void pnd2_unregister_mci(struct mem_ctl_info *mci)
*/
static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
struct mem_ctl_info *mci;
struct dram_addr daddr;
char *type;
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index e5c05a876947..4dadb9975b23 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -3255,7 +3255,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
struct mem_ctl_info *mci;
char *type;
diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c
index 8d18099fd528..21f9d2c22c81 100644
--- a/drivers/edac/skx_common.c
+++ b/drivers/edac/skx_common.c
@@ -644,7 +644,7 @@ static bool skx_error_in_mem(const struct mce *m)
int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *mce = (struct mce *)data;
+ struct mce *mce = &((struct mce_hw_err *)data)->m;
struct decoded_addr res;
struct mem_ctl_info *mci;
char *type;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index d0307c55da50..fea085ef663e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -4158,7 +4158,7 @@ static struct amdgpu_device *find_adev(uint32_t node_id)
static int amdgpu_bad_page_notifier(struct notifier_block *nb,
unsigned long val, void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce *m = &((struct mce_hw_err *)data)->m;
struct amdgpu_device *adev = NULL;
uint32_t gpu_id = 0;
uint32_t umc_inst = 0, ch_inst = 0;
diff --git a/drivers/ras/amd/fmpm.c b/drivers/ras/amd/fmpm.c
index 90de737fbc90..78dd4b192992 100644
--- a/drivers/ras/amd/fmpm.c
+++ b/drivers/ras/amd/fmpm.c
@@ -400,7 +400,7 @@ static void retire_dram_row(u64 addr, u64 id, u32 cpu)
static int fru_handle_mem_poison(struct notifier_block *nb, unsigned long val, void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce *m = &((struct mce_hw_err *)data)->m;
struct fru_rec *rec;
if (!mce_is_memory_error(m))
diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
index e440b15fbabc..be785746f587 100644
--- a/drivers/ras/cec.c
+++ b/drivers/ras/cec.c
@@ -534,7 +534,7 @@ static int __init create_debugfs_nodes(void)
static int cec_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
- struct mce *m = (struct mce *)data;
+ struct mce *m = &((struct mce_hw_err *)data)->m;
if (!m)
return NOTIFY_DONE;
diff --git a/include/trace/events/mce.h b/include/trace/events/mce.h
index f0f7b3cb2041..65aba1afcd07 100644
--- a/include/trace/events/mce.h
+++ b/include/trace/events/mce.h
@@ -19,9 +19,9 @@
TRACE_EVENT(mce_record,
- TP_PROTO(struct mce *m),
+ TP_PROTO(struct mce_hw_err *err),
- TP_ARGS(m),
+ TP_ARGS(err),
TP_STRUCT__entry(
__field( u64, mcgcap )
@@ -46,25 +46,25 @@ TRACE_EVENT(mce_record,
),
TP_fast_assign(
- __entry->mcgcap = m->mcgcap;
- __entry->mcgstatus = m->mcgstatus;
- __entry->status = m->status;
- __entry->addr = m->addr;
- __entry->misc = m->misc;
- __entry->synd = m->synd;
- __entry->ipid = m->ipid;
- __entry->ip = m->ip;
- __entry->tsc = m->tsc;
- __entry->ppin = m->ppin;
- __entry->walltime = m->time;
- __entry->cpu = m->extcpu;
- __entry->cpuid = m->cpuid;
- __entry->apicid = m->apicid;
- __entry->socketid = m->socketid;
- __entry->cs = m->cs;
- __entry->bank = m->bank;
- __entry->cpuvendor = m->cpuvendor;
- __entry->microcode = m->microcode;
+ __entry->mcgcap = err->m.mcgcap;
+ __entry->mcgstatus = err->m.mcgstatus;
+ __entry->status = err->m.status;
+ __entry->addr = err->m.addr;
+ __entry->misc = err->m.misc;
+ __entry->synd = err->m.synd;
+ __entry->ipid = err->m.ipid;
+ __entry->ip = err->m.ip;
+ __entry->tsc = err->m.tsc;
+ __entry->ppin = err->m.ppin;
+ __entry->walltime = err->m.time;
+ __entry->cpu = err->m.extcpu;
+ __entry->cpuid = err->m.cpuid;
+ __entry->apicid = err->m.apicid;
+ __entry->socketid = err->m.socketid;
+ __entry->cs = err->m.cs;
+ __entry->bank = err->m.bank;
+ __entry->cpuvendor = err->m.cpuvendor;
+ __entry->microcode = err->m.microcode;
),
TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR: %016Lx, MISC: %016Lx, SYND: %016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcode: %x",
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/4] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers
2024-07-30 18:54 [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
@ 2024-07-30 18:54 ` Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 3/4] x86/mce/apei: Handle variable register array size Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 4/4] EDAC/mce_amd: Add support for FRU Text in MCA Avadhut Naik
3 siblings, 0 replies; 6+ messages in thread
From: Avadhut Naik @ 2024-07-30 18:54 UTC (permalink / raw)
To: x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: linux-kernel, bp, tony.luck, rafael, tglx, mingo, rostedt, lenb,
mchehab, james.morse, airlied, yazen.ghannam, john.allen,
avadnaik
Starting with Zen4, AMD's Scalable MCA systems incorporate two new
registers: MCA_SYND1 and MCA_SYND2.
These registers will include supplemental error information in addition
to the existing MCA_SYND register. The data within these registers is
considered valid if MCA_STATUS[SyndV] is set.
Userspace error decoding tools like the rasdaemon gather related hardware
error information through the tracepoints. As such, these two registers
should be exported through the mce_record tracepoint so that tools like
rasdaemon can parse them and output the supplemental error information
like FRU Text contained in them.
[Yazen: Drop Yazen's Co-developed-by tag and moved SoB tag.]
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
Changes in v2:
[1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghannam@amd.com/
[2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghannam@amd.com/
1. Drop dependencies on sets [1] and [2] above and rebase on top of
tip/master.
Changes in v3:
1. Move wrapper changes required in mce_read_aux() and mce_no_way_out()
from this patch to the first patch.
2. Add comments to explain the new wrapper's purpose.
3. Modify commit message per feedback received.
4. Fix SoB chain to properly reflect the patch path.
---
arch/x86/include/asm/mce.h | 22 ++++++++++++++++++++++
arch/x86/include/uapi/asm/mce.h | 3 ++-
arch/x86/kernel/cpu/mce/amd.c | 5 ++++-
arch/x86/kernel/cpu/mce/core.c | 9 ++++++++-
drivers/edac/mce_amd.c | 10 +++++++---
include/trace/events/mce.h | 9 +++++++--
6 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ba2b3a5f999e..a5be7463c78a 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -122,6 +122,9 @@
#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
+/* Registers MISC2 to MISC4 are at offsets B to D. */
+#define MSR_AMD64_SMCA_MC0_SYND1 0xc000200e
+#define MSR_AMD64_SMCA_MC0_SYND2 0xc000200f
#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
@@ -132,6 +135,8 @@
#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
+#define MSR_AMD64_SMCA_MCx_SYND1(x) (MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x))
+#define MSR_AMD64_SMCA_MCx_SYND2(x) (MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x))
#define XEC(x, mask) (((x) >> 16) & mask)
@@ -190,9 +195,26 @@ enum mce_notifier_prios {
/**
* struct mce_hw_err - Hardware Error Record.
* @m: Machine Check record.
+ * @vendor: Vendor-specific error information.
+ *
+ * Vendor-specific fields should not be added to struct mce.
+ * Instead, vendors should export their vendor-specific data
+ * through their structure in the vendor union below.
+ *
+ * AMD's vendor data is parsed by error decoding tools for
+ * supplemental error information. Thus, current offsets of
+ * existing fields must be maintained.
+ * Only add new fields at the end of AMD's vendor structure.
*/
struct mce_hw_err {
struct mce m;
+
+ union vendor_info {
+ struct {
+ u64 synd1; /* MCA_SYND1 MSR */
+ u64 synd2; /* MCA_SYND2 MSR */
+ } amd;
+ } vendor;
};
struct notifier_block;
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
index db9adc081c5a..cb6b48a7c22b 100644
--- a/arch/x86/include/uapi/asm/mce.h
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -8,7 +8,8 @@
/*
* Fields are zero when not available. Also, this struct is shared with
* userspace mcelog and thus must keep existing fields at current offsets.
- * Only add new fields to the end of the structure
+ * Only add new, shared fields to the end of the structure.
+ * Do not add vendor-specific fields.
*/
struct mce {
__u64 status; /* Bank's MCi_STATUS MSR */
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index cb7dc0b1aa50..a2a5fb940bb6 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -799,8 +799,11 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
if (mce_flags.smca) {
rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);
- if (m->status & MCI_STATUS_SYNDV)
+ if (m->status & MCI_STATUS_SYNDV) {
rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);
+ rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1);
+ rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2);
+ }
}
mce_log(&err);
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index ab9f1d606438..c8089d7a8e9b 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -189,6 +189,10 @@ static void __print_mce(struct mce_hw_err *err)
if (mce_flags.smca) {
if (m->synd)
pr_cont("SYND %llx ", m->synd);
+ if (err->vendor.amd.synd1)
+ pr_cont("SYND1 %llx ", err->vendor.amd.synd1);
+ if (err->vendor.amd.synd2)
+ pr_cont("SYND2 %llx ", err->vendor.amd.synd2);
if (m->ipid)
pr_cont("IPID %llx ", m->ipid);
}
@@ -664,8 +668,11 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i)
if (mce_flags.smca) {
m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
- if (m->status & MCI_STATUS_SYNDV)
+ if (m->status & MCI_STATUS_SYNDV) {
m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
+ err->vendor.amd.synd1 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(i));
+ err->vendor.amd.synd2 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(i));
+ }
}
}
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index c5fae99de781..aea68999c849 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -792,7 +792,8 @@ static const char *decode_error_status(struct mce *m)
static int
amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
{
- struct mce *m = &((struct mce_hw_err *)data)->m;
+ struct mce_hw_err *err = (struct mce_hw_err *)data;
+ struct mce *m = &err->m;
unsigned int fam = x86_family(m->cpuid);
int ecc;
@@ -850,8 +851,11 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
if (boot_cpu_has(X86_FEATURE_SMCA)) {
pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
- if (m->status & MCI_STATUS_SYNDV)
- pr_cont(", Syndrome: 0x%016llx", m->synd);
+ if (m->status & MCI_STATUS_SYNDV) {
+ pr_cont(", Syndrome: 0x%016llx\n", m->synd);
+ pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx",
+ err->vendor.amd.synd1, err->vendor.amd.synd2);
+ }
pr_cont("\n");
diff --git a/include/trace/events/mce.h b/include/trace/events/mce.h
index 65aba1afcd07..1e7d5696b3ba 100644
--- a/include/trace/events/mce.h
+++ b/include/trace/events/mce.h
@@ -43,6 +43,8 @@ TRACE_EVENT(mce_record,
__field( u8, bank )
__field( u8, cpuvendor )
__field( u32, microcode )
+ __field( u8, len )
+ __dynamic_array(u8, v_data, sizeof(err->vendor))
),
TP_fast_assign(
@@ -65,9 +67,11 @@ TRACE_EVENT(mce_record,
__entry->bank = err->m.bank;
__entry->cpuvendor = err->m.cpuvendor;
__entry->microcode = err->m.microcode;
+ __entry->len = sizeof(err->vendor);
+ memcpy(__get_dynamic_array(v_data), &err->vendor, sizeof(err->vendor));
),
- TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR: %016Lx, MISC: %016Lx, SYND: %016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcode: %x",
+ TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016llx, IPID: %016llx, ADDR: %016llx, MISC: %016llx, SYND: %016llx, RIP: %02x:<%016llx>, TSC: %llx, PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcode: %x, vendor data: %s",
__entry->cpu,
__entry->mcgcap, __entry->mcgstatus,
__entry->bank, __entry->status,
@@ -83,7 +87,8 @@ TRACE_EVENT(mce_record,
__entry->walltime,
__entry->socketid,
__entry->apicid,
- __entry->microcode)
+ __entry->microcode,
+ __print_array(__get_dynamic_array(v_data), __entry->len / 8, 8))
);
#endif /* _TRACE_MCE_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/4] x86/mce/apei: Handle variable register array size
2024-07-30 18:54 [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 2/4] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Avadhut Naik
@ 2024-07-30 18:54 ` Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 4/4] EDAC/mce_amd: Add support for FRU Text in MCA Avadhut Naik
3 siblings, 0 replies; 6+ messages in thread
From: Avadhut Naik @ 2024-07-30 18:54 UTC (permalink / raw)
To: x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: linux-kernel, bp, tony.luck, rafael, tglx, mingo, rostedt, lenb,
mchehab, james.morse, airlied, yazen.ghannam, john.allen,
avadnaik
From: Yazen Ghannam <yazen.ghannam@amd.com>
ACPI Boot Error Record Table (BERT) is being used by the kernel to
report errors that occurred in a previous boot. On some modern AMD
systems, these very errors within the BERT are reported through the
x86 Common Platform Error Record (CPER) format which consists of one
or more Processor Context Information Structures. These context
structures provide a starting address and represent an x86 MSR range
in which the data constitutes a contiguous set of MSRs starting from,
and including the starting address.
It's common, for AMD systems that implement this behavior, that the
MSR range represents the MCAX register space used for the Scalable MCA
feature. The apei_smca_report_x86_error() function decodes and passes
this information through the MCE notifier chain. However, this function
assumes a fixed register size based on the original HW/FW implementation.
This assumption breaks with the addition of two new MCAX registers viz.
MCA_SYND1 and MCA_SYND2. These registers are added at the end of the
MCAX register space, so they won't be included when decoding the CPER
data.
Rework apei_smca_report_x86_error() to support a variable register array
size. This covers any case where the MSR context information starts at
the MCAX address for MCA_STATUS and ends at any other register within
the MCAX register space.
Add code comments indicating the MCAX register at each offset.
[Yazen: Add Avadhut as co-developer for wrapper changes.]
Co-developed-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
Changes in v2:
[1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghannam@amd.com/
[2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghannam@amd.com/
1. Drop dependencies on sets [1] and [2] above and rebase on top of
tip/master.
Changes in v3:
1. Incorporate suggested touchup.
2. Fix SoB chain to properly reflect the patch path.
---
arch/x86/kernel/cpu/mce/apei.c | 72 +++++++++++++++++++++++++++-------
1 file changed, 58 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
index b8f4e75fb8a7..5949fc103be4 100644
--- a/arch/x86/kernel/cpu/mce/apei.c
+++ b/arch/x86/kernel/cpu/mce/apei.c
@@ -69,9 +69,9 @@ EXPORT_SYMBOL_GPL(apei_mce_report_mem_error);
int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
{
const u64 *i_mce = ((const u64 *) (ctx_info + 1));
+ unsigned int cpu, num_regs;
struct mce_hw_err err;
struct mce *m = &err.m;
- unsigned int cpu;
memset(&err, 0, sizeof(struct mce_hw_err));
@@ -91,16 +91,12 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
return -EINVAL;
/*
- * The register array size must be large enough to include all the
- * SMCA registers which need to be extracted.
- *
* The number of registers in the register array is determined by
* Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2.
- * The register layout is fixed and currently the raw data in the
- * register array includes 6 SMCA registers which the kernel can
- * extract.
+ * Sanity-check registers array size.
*/
- if (ctx_info->reg_arr_size < 48)
+ num_regs = ctx_info->reg_arr_size >> 3;
+ if (!num_regs)
return -EINVAL;
mce_setup(m);
@@ -118,12 +114,60 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
m->apicid = lapic_id;
m->bank = (ctx_info->msr_addr >> 4) & 0xFF;
- m->status = *i_mce;
- m->addr = *(i_mce + 1);
- m->misc = *(i_mce + 2);
- /* Skipping MCA_CONFIG */
- m->ipid = *(i_mce + 4);
- m->synd = *(i_mce + 5);
+
+ /*
+ * The SMCA register layout is fixed and includes 16 registers.
+ * The end of the array may be variable, but the beginning is known.
+ * Cap the number of registers to expected max (15).
+ */
+ if (num_regs > 15)
+ num_regs = 15;
+
+ switch (num_regs) {
+ /* MCA_SYND2 */
+ case 15:
+ err.vendor.amd.synd2 = *(i_mce + 14);
+ fallthrough;
+ /* MCA_SYND1 */
+ case 14:
+ err.vendor.amd.synd1 = *(i_mce + 13);
+ fallthrough;
+ /* MCA_MISC4 */
+ case 13:
+ /* MCA_MISC3 */
+ case 12:
+ /* MCA_MISC2 */
+ case 11:
+ /* MCA_MISC1 */
+ case 10:
+ /* MCA_DEADDR */
+ case 9:
+ /* MCA_DESTAT */
+ case 8:
+ /* reserved */
+ case 7:
+ /* MCA_SYND */
+ case 6:
+ m->synd = *(i_mce + 5);
+ fallthrough;
+ /* MCA_IPID */
+ case 5:
+ m->ipid = *(i_mce + 4);
+ fallthrough;
+ /* MCA_CONFIG */
+ case 4:
+ /* MCA_MISC0 */
+ case 3:
+ m->misc = *(i_mce + 2);
+ fallthrough;
+ /* MCA_ADDR */
+ case 2:
+ m->addr = *(i_mce + 1);
+ fallthrough;
+ /* MCA_STATUS */
+ case 1:
+ m->status = *i_mce;
+ }
mce_log(&err);
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 4/4] EDAC/mce_amd: Add support for FRU Text in MCA
2024-07-30 18:54 [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
` (2 preceding siblings ...)
2024-07-30 18:54 ` [PATCH v3 3/4] x86/mce/apei: Handle variable register array size Avadhut Naik
@ 2024-07-30 18:54 ` Avadhut Naik
3 siblings, 0 replies; 6+ messages in thread
From: Avadhut Naik @ 2024-07-30 18:54 UTC (permalink / raw)
To: x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: linux-kernel, bp, tony.luck, rafael, tglx, mingo, rostedt, lenb,
mchehab, james.morse, airlied, yazen.ghannam, john.allen,
avadnaik
From: Yazen Ghannam <yazen.ghannam@amd.com>
A new "FRU Text in MCA" feature is defined where the Field Replaceable
Unit (FRU) Text for a device is represented by a string in the new
MCA_SYND1 and MCA_SYND2 registers. This feature is supported per MCA
bank, and it is advertised by the McaFruTextInMca bit (MCA_CONFIG[9]).
The FRU Text is populated dynamically for each individual error state
(MCA_STATUS, MCA_ADDR, et al.). This handles the case where an MCA bank
covers multiple devices, for example, a Unified Memory Controller (UMC)
bank that manages two DIMMs.
Since MCA_CONFIG[9] is instrumental in decoding FRU Text, it has to be
exported through the mce_record tracepoint so that userspace tools like
the rasdaemon can determine if FRU Text has been reported through the
MCA_SYND1 and MCA_SYND2 registers and output it.
[Yazen: Add Avadhut as co-developer for wrapper changes.]
Co-developed-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
Changes in v2:
[1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghannam@amd.com/
[2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghannam@amd.com/
1. Drop dependencies on sets [1] and [2] above and rebase on top of
tip/master.
Changes in v3:
1. Modify commit message per feedback provided.
2. Remove call to memset() for the string frutext. Instead, just ensure
that it is NULL terminated.
2. Fix SoB chain to properly reflect the patch path.
---
arch/x86/include/asm/mce.h | 2 ++
arch/x86/kernel/cpu/mce/amd.c | 1 +
arch/x86/kernel/cpu/mce/apei.c | 2 ++
arch/x86/kernel/cpu/mce/core.c | 3 +++
drivers/edac/mce_amd.c | 21 ++++++++++++++-------
5 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index a5be7463c78a..377a5469ed7e 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -61,6 +61,7 @@
* - TCC bit is present in MCx_STATUS.
*/
#define MCI_CONFIG_MCAX 0x1
+#define MCI_CONFIG_FRUTEXT BIT_ULL(9)
#define MCI_IPID_MCATYPE 0xFFFF0000
#define MCI_IPID_HWID 0xFFF
@@ -213,6 +214,7 @@ struct mce_hw_err {
struct {
u64 synd1; /* MCA_SYND1 MSR */
u64 synd2; /* MCA_SYND2 MSR */
+ u64 config; /* MCA_CONFIG MSR */
} amd;
} vendor;
};
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index a2a5fb940bb6..00b6fa987094 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -798,6 +798,7 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
if (mce_flags.smca) {
rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);
+ rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), err.vendor.amd.config);
if (m->status & MCI_STATUS_SYNDV) {
rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);
diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
index 5949fc103be4..db2677f3023a 100644
--- a/arch/x86/kernel/cpu/mce/apei.c
+++ b/arch/x86/kernel/cpu/mce/apei.c
@@ -156,6 +156,8 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
fallthrough;
/* MCA_CONFIG */
case 4:
+ err.vendor.amd.config = *(i_mce + 3);
+ fallthrough;
/* MCA_MISC0 */
case 3:
m->misc = *(i_mce + 2);
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index c8089d7a8e9b..054188aac2ee 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -195,6 +195,8 @@ static void __print_mce(struct mce_hw_err *err)
pr_cont("SYND2 %llx ", err->vendor.amd.synd2);
if (m->ipid)
pr_cont("IPID %llx ", m->ipid);
+ if (err->vendor.amd.config)
+ pr_cont("CONFIG %llx ", err->vendor.amd.config);
}
pr_cont("\n");
@@ -667,6 +669,7 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i)
if (mce_flags.smca) {
m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
+ err->vendor.amd.config = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(i));
if (m->status & MCI_STATUS_SYNDV) {
m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index aea68999c849..f7f7ea0a5292 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -795,6 +795,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
struct mce_hw_err *err = (struct mce_hw_err *)data;
struct mce *m = &err->m;
unsigned int fam = x86_family(m->cpuid);
+ u64 mca_config = err->vendor.amd.config;
int ecc;
if (m->kflags & MCE_HANDLED_CEC)
@@ -814,11 +815,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"));
if (boot_cpu_has(X86_FEATURE_SMCA)) {
- u32 low, high;
- u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
-
- if (!rdmsr_safe(addr, &low, &high) &&
- (low & MCI_CONFIG_MCAX))
+ if (mca_config & MCI_CONFIG_MCAX)
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
@@ -853,8 +850,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
if (m->status & MCI_STATUS_SYNDV) {
pr_cont(", Syndrome: 0x%016llx\n", m->synd);
- pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx",
- err->vendor.amd.synd1, err->vendor.amd.synd2);
+ if (mca_config & MCI_CONFIG_FRUTEXT) {
+ char frutext[17];
+ frutext[16] = '\0';
+
+ memcpy(&frutext[0], &err->vendor.amd.synd1, 8);
+ memcpy(&frutext[8], &err->vendor.amd.synd2, 8);
+
+ pr_emerg(HW_ERR "FRU Text: %s", frutext);
+ } else {
+ pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx",
+ err->vendor.amd.synd1, err->vendor.amd.synd2);
+ }
}
pr_cont("\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info
2024-07-30 18:54 ` [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
@ 2024-08-03 15:24 ` kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2024-08-03 15:24 UTC (permalink / raw)
To: Avadhut Naik, x86, linux-trace-kernel, linux-edac, linux-acpi
Cc: oe-kbuild-all, linux-kernel, bp, tony.luck, rafael, tglx, mingo,
rostedt, lenb, mchehab, james.morse, airlied, yazen.ghannam,
john.allen, avadnaik
Hi Avadhut,
kernel test robot noticed the following build warnings:
[auto build test WARNING on dee974604f7870167161cbe51e8f3b9c2858de34]
url: https://github.com/intel-lab-lkp/linux/commits/Avadhut-Naik/x86-mce-Add-wrapper-for-struct-mce-to-export-vendor-specific-info/20240801-192550
base: dee974604f7870167161cbe51e8f3b9c2858de34
patch link: https://lore.kernel.org/r/20240730185406.3709876-2-avadhut.naik%40amd.com
patch subject: [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info
config: x86_64-randconfig-071-20240803 (https://download.01.org/0day-ci/archive/20240803/202408032312.5lkzepQe-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240803/202408032312.5lkzepQe-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408032312.5lkzepQe-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> vmlinux.o: warning: objtool: do_machine_check+0x6e: call to __asan_memset() leaves .noinstr.text section
vmlinux.o: warning: objtool: intel_idle_ibrs+0x11: call to sched_smt_active() leaves .noinstr.text section
objdump-func vmlinux.o do_machine_check:
0000 00000000000025a0 <do_machine_check>:
0000 25a0: f3 0f 1e fa endbr64
0004 25a4: 41 57 push %r15
0006 25a6: b9 10 00 00 00 mov $0x10,%ecx
000b 25ab: 31 f6 xor %esi,%esi
000d 25ad: ba 80 00 00 00 mov $0x80,%edx
0012 25b2: 41 56 push %r14
0014 25b4: 41 55 push %r13
0016 25b6: 41 54 push %r12
0018 25b8: 55 push %rbp
0019 25b9: 48 89 fd mov %rdi,%rbp
001c 25bc: 53 push %rbx
001d 25bd: 48 81 ec c8 00 00 00 sub $0xc8,%rsp
0024 25c4: 65 48 8b 04 25 28 00 00 00 mov %gs:0x28,%rax
002d 25cd: 48 89 84 24 c0 00 00 00 mov %rax,0xc0(%rsp)
0035 25d5: 31 c0 xor %eax,%eax
0037 25d7: 48 8d 5c 24 30 lea 0x30(%rsp),%rbx
003c 25dc: c7 44 24 1c 00 00 00 00 movl $0x0,0x1c(%rsp)
0044 25e4: 48 c7 84 24 b0 00 00 00 00 00 00 00 movq $0x0,0xb0(%rsp)
0050 25f0: 48 89 df mov %rbx,%rdi
0053 25f3: 48 c7 84 24 b8 00 00 00 00 00 00 00 movq $0x0,0xb8(%rsp)
005f 25ff: 48 c7 44 24 20 00 00 00 00 movq $0x0,0x20(%rsp)
0068 2608: f3 48 ab rep stos %rax,%es:(%rdi)
006b 260b: 48 89 df mov %rbx,%rdi
006e 260e: e8 00 00 00 00 call 2613 <do_machine_check+0x73> 260f: R_X86_64_PLT32 __asan_memset-0x4
0073 2613: f6 05 00 00 00 00 60 testb $0x60,0x0(%rip) # 261a <do_machine_check+0x7a> 2615: R_X86_64_PC32 mce_flags-0x5
007a 261a: 0f 85 de 04 00 00 jne 2afe <do_machine_check+0x55e>
0080 2620: f6 05 00 00 00 00 20 testb $0x20,0x0(%rip) # 2627 <do_machine_check+0x87> 2622: R_X86_64_PC32 mca_cfg-0x5
0087 2627: 0f 84 20 08 00 00 je 2e4d <do_machine_check+0x8ad>
008d 262d: f6 05 00 00 00 00 01 testb $0x1,0x0(%rip) # 2634 <do_machine_check+0x94> 262f: R_X86_64_PC32 mce_flags-0x4
0094 2634: 0f 85 f1 04 00 00 jne 2b2b <do_machine_check+0x58b>
009a 263a: c7 44 24 1c 00 00 00 00 movl $0x0,0x1c(%rsp)
00a2 2642: ff 05 00 00 00 00 incl 0x0(%rip) # 2648 <do_machine_check+0xa8> 2644: R_X86_64_PC32 mce_exception_count-0x4
00a8 2648: 48 89 ee mov %rbp,%rsi
00ab 264b: 48 89 df mov %rbx,%rdi
00ae 264e: e8 dd fe ff ff call 2530 <mce_gather_info>
00b3 2653: 0f 31 rdtsc
00b5 2655: 48 c1 e2 20 shl $0x20,%rdx
00b9 2659: 48 09 d0 or %rdx,%rax
00bc 265c: 48 8b 54 24 30 mov 0x30(%rsp),%rdx
00c1 2661: 48 89 44 24 58 mov %rax,0x58(%rsp)
00c6 2666: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 266d <do_machine_check+0xcd> 2669: R_X86_64_PC32 .data+0xb2884
00cd 266d: 48 8b 44 24 60 mov 0x60(%rsp),%rax
00d2 2672: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2679 <do_machine_check+0xd9> 2675: R_X86_64_PC32 .data+0xb285c
00d9 2679: 48 8b 54 24 38 mov 0x38(%rsp),%rdx
00de 267e: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 2685 <do_machine_check+0xe5> 2681: R_X86_64_PC32 .data+0xb288c
00e5 2685: 48 8b 44 24 68 mov 0x68(%rsp),%rax
00ea 268a: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2691 <do_machine_check+0xf1> 268d: R_X86_64_PC32 .data+0xb2864
00f1 2691: 48 8b 54 24 40 mov 0x40(%rsp),%rdx
00f6 2696: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 269d <do_machine_check+0xfd> 2699: R_X86_64_PC32 .data+0xb2894
00fd 269d: 48 8b 44 24 70 mov 0x70(%rsp),%rax
0102 26a2: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 26a9 <do_machine_check+0x109> 26a5: R_X86_64_PC32 .data+0xb286c
0109 26a9: 48 8b 54 24 48 mov 0x48(%rsp),%rdx
010e 26ae: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 26b5 <do_machine_check+0x115> 26b1: R_X86_64_PC32 .data+0xb289c
0115 26b5: 48 8b 44 24 78 mov 0x78(%rsp),%rax
011a 26ba: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 26c1 <do_machine_check+0x121> 26bd: R_X86_64_PC32 .data+0xb2874
0121 26c1: 48 8b 54 24 50 mov 0x50(%rsp),%rdx
0126 26c6: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 26cd <do_machine_check+0x12d> 26c9: R_X86_64_PC32 .data+0xb28a4
012d 26cd: 48 8b 84 24 80 00 00 00 mov 0x80(%rsp),%rax
0135 26d5: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 26dc <do_machine_check+0x13c> 26d8: R_X86_64_PC32 .data+0xb287c
013c 26dc: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 26e3 <do_machine_check+0x143> 26df: R_X86_64_PC32 .data+0xb28ac
0143 26e3: 48 8b 84 24 88 00 00 00 mov 0x88(%rsp),%rax
014b 26eb: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 26f2 <do_machine_check+0x152> 26ee: R_X86_64_PC32 .data+0xb28b4
0152 26f2: 48 8b 84 24 90 00 00 00 mov 0x90(%rsp),%rax
015a 26fa: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 2701 <do_machine_check+0x161> 26fd: R_X86_64_PC32 .data+0xb28bc
0161 2701: 48 8b 84 24 98 00 00 00 mov 0x98(%rsp),%rax
0169 2709: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 2710 <do_machine_check+0x170> 270c: R_X86_64_PC32 .data+0xb28c4
0170 2710: 48 8b 84 24 a0 00 00 00 mov 0xa0(%rsp),%rax
0178 2718: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 271f <do_machine_check+0x17f> 271b: R_X86_64_PC32 .data+0xb28cc
017f 271f: 48 8b 84 24 a8 00 00 00 mov 0xa8(%rsp),%rax
0187 2727: 48 89 05 00 00 00 00 mov %rax,0x0(%rip) # 272e <do_machine_check+0x18e> 272a: R_X86_64_PC32 .data+0xb28d4
018e 272e: 48 8b 44 24 20 mov 0x20(%rsp),%rax
0193 2733: 48 89 44 24 28 mov %rax,0x28(%rsp)
0198 2738: 8b 05 00 00 00 00 mov 0x0(%rip),%eax # 273e <do_machine_check+0x19e> 273a: R_X86_64_PC32 mce_num_banks-0x4
019e 273e: 49 be ff ef 00 00 00 00 80 7f movabs $0x7f8000000000efff,%r14
01a8 2748: 45 31 e4 xor %r12d,%r12d
01ab 274b: 49 bd 50 01 00 00 00 00 80 3d movabs $0x3d80000000000150,%r13
01b5 2755: 85 c0 test %eax,%eax
01b7 2757: 75 57 jne 27b0 <do_machine_check+0x210>
01b9 2759: e9 e3 00 00 00 jmp 2841 <do_machine_check+0x2a1>
01be 275e: a8 08 test $0x8,%al
01c0 2760: 74 18 je 277a <do_machine_check+0x1da>
01c2 2762: 41 83 fc 01 cmp $0x1,%r12d
01c6 2766: 75 12 jne 277a <do_machine_check+0x1da>
01c8 2768: f6 44 24 35 08 testb $0x8,0x35(%rsp)
01cd 276d: 74 0b je 277a <do_machine_check+0x1da>
01cf 276f: 0f b7 85 88 00 00 00 movzwl 0x88(%rbp),%eax
01d6 2776: 88 44 24 70 mov %al,0x70(%rsp)
01da 277a: b9 01 00 00 00 mov $0x1,%ecx
01df 277f: 48 8d 54 24 28 lea 0x28(%rsp),%rdx
01e4 2784: 48 89 ee mov %rbp,%rsi
01e7 2787: 48 89 df mov %rbx,%rdi
01ea 278a: 44 88 64 24 71 mov %r12b,0x71(%rsp)
01ef 278f: e8 00 00 00 00 call 2794 <do_machine_check+0x1f4> 2790: R_X86_64_PLT32 mce_severity-0x4
01f4 2794: 83 f8 06 cmp $0x6,%eax
01f7 2797: 0f 8f 08 05 00 00 jg 2ca5 <do_machine_check+0x705>
01fd 279d: 41 83 c4 01 add $0x1,%r12d
0201 27a1: 8b 05 00 00 00 00 mov 0x0(%rip),%eax # 27a7 <do_machine_check+0x207> 27a3: R_X86_64_PC32 mce_num_banks-0x4
0207 27a7: 41 39 c4 cmp %eax,%r12d
020a 27aa: 0f 83 91 00 00 00 jae 2841 <do_machine_check+0x2a1>
0210 27b0: e9 00 00 00 00 jmp 27b5 <do_machine_check+0x215> 27b1: R_X86_64_PC32 .altinstr_aux+0xe66
0215 27b5: 44 89 e7 mov %r12d,%edi
0218 27b8: c1 e7 04 shl $0x4,%edi
021b 27bb: 81 ef ff df ff 3f sub $0x3fffdfff,%edi
0221 27c1: e8 00 00 00 00 call 27c6 <do_machine_check+0x226> 27c2: R_X86_64_PLT32 mce_rdmsrl-0x4
0226 27c6: 48 89 44 24 30 mov %rax,0x30(%rsp)
022b 27cb: 48 85 c0 test %rax,%rax
022e 27ce: 79 cd jns 279d <do_machine_check+0x1fd>
0230 27d0: 49 63 c4 movslq %r12d,%rax
0233 27d3: 48 0f ab 84 24 b0 00 00 00 bts %rax,0xb0(%rsp)
023c 27dc: 0f b6 05 00 00 00 00 movzbl 0x0(%rip),%eax # 27e3 <do_machine_check+0x243> 27df: R_X86_64_PC32 mce_flags-0x4
0243 27e3: 45 85 e4 test %r12d,%r12d
0246 27e6: 0f 85 72 ff ff ff jne 275e <do_machine_check+0x1be>
024c 27ec: 84 c0 test %al,%al
024e 27ee: 0f 89 6a ff ff ff jns 275e <do_machine_check+0x1be>
0254 27f4: 48 8b 44 24 48 mov 0x48(%rsp),%rax
0259 27f9: a8 03 test $0x3,%al
025b 27fb: 0f 85 79 ff ff ff jne 277a <do_machine_check+0x1da>
0261 2801: 48 8b 54 24 30 mov 0x30(%rsp),%rdx
0266 2806: 4c 21 f2 and %r14,%rdx
0269 2809: 4c 39 ea cmp %r13,%rdx
026c 280c: 0f 85 68 ff ff ff jne 277a <do_machine_check+0x1da>
0272 2812: 48 83 c8 02 or $0x2,%rax
0276 2816: 48 89 44 24 48 mov %rax,0x48(%rsp)
027b 281b: 48 8b 85 80 00 00 00 mov 0x80(%rbp),%rax
0282 2822: 48 89 44 24 50 mov %rax,0x50(%rsp)
0287 2827: 0f b7 85 88 00 00 00 movzwl 0x88(%rbp),%eax
028e 282e: 88 44 24 70 mov %al,0x70(%rsp)
0292 2832: e9 43 ff ff ff jmp 277a <do_machine_check+0x1da>
0297 2837: 42 8d 3c a5 01 04 00 00 lea 0x401(,%r12,4),%edi
029f 283f: eb 80 jmp 27c1 <do_machine_check+0x221>
02a1 2841: 31 c0 xor %eax,%eax
02a3 2843: 89 44 24 1c mov %eax,0x1c(%rsp)
02a7 2847: 48 8b 44 24 48 mov 0x48(%rsp),%rax
02ac 284c: 48 89 44 24 08 mov %rax,0x8(%rsp)
02b1 2851: 0f b6 44 24 68 movzbl 0x68(%rsp),%eax
02b6 2856: 84 c0 test %al,%al
02b8 2858: 0f 84 1e 04 00 00 je 2c7c <do_machine_check+0x6dc>
02be 285e: c7 44 24 04 01 00 00 00 movl $0x1,0x4(%rsp)
02c6 2866: 3c 0a cmp $0xa,%al
02c8 2868: 0f 84 0e 04 00 00 je 2c7c <do_machine_check+0x6dc>
02ce 286e: 44 8b 7c 24 1c mov 0x1c(%rsp),%r15d
02d3 2873: c7 44 24 14 ff ff ff ff movl $0xffffffff,0x14(%rsp)
02db 287b: 45 85 ff test %r15d,%r15d
02de 287e: 0f 85 c4 04 00 00 jne 2d48 <do_machine_check+0x7a8>
02e4 2884: 8b 15 00 00 00 00 mov 0x0(%rip),%edx # 288a <do_machine_check+0x2ea> 2886: R_X86_64_PC32 mce_num_banks-0x4
02ea 288a: 45 31 e4 xor %r12d,%r12d
02ed 288d: c7 04 24 00 00 00 00 movl $0x0,(%rsp)
02f4 2894: 85 d2 test %edx,%edx
02f6 2896: 0f 84 de 00 00 00 je 297a <do_machine_check+0x3da>
02fc 289c: 45 31 f6 xor %r14d,%r14d
02ff 289f: 4d 63 ee movslq %r14d,%r13
0302 28a2: 4c 0f b3 ac 24 b8 00 00 00 btr %r13,0xb8(%rsp)
030b 28ab: 4c 0f a3 ac 24 b0 00 00 00 bt %r13,0xb0(%rsp)
0314 28b4: 0f 83 a8 00 00 00 jae 2962 <do_machine_check+0x3c2>
031a 28ba: 4c 89 e8 mov %r13,%rax
031d 28bd: 48 c1 e0 04 shl $0x4,%rax
0321 28c1: 48 83 b8 00 00 00 00 00 cmpq $0x0,0x0(%rax) 28c4: R_X86_64_32S mce_banks_array
0329 28c9: 0f 84 93 00 00 00 je 2962 <do_machine_check+0x3c2>
032f 28cf: 48 c7 44 24 38 00 00 00 00 movq $0x0,0x38(%rsp)
0338 28d8: 48 c7 44 24 40 00 00 00 00 movq $0x0,0x40(%rsp)
0341 28e1: 44 88 74 24 71 mov %r14b,0x71(%rsp)
0346 28e6: e9 00 00 00 00 jmp 28eb <do_machine_check+0x34b> 28e7: R_X86_64_PC32 .altinstr_aux+0xe78
034b 28eb: 44 89 f7 mov %r14d,%edi
034e 28ee: c1 e7 04 shl $0x4,%edi
0351 28f1: 81 ef ff df ff 3f sub $0x3fffdfff,%edi
0357 28f7: e8 00 00 00 00 call 28fc <do_machine_check+0x35c> 28f8: R_X86_64_PLT32 mce_rdmsrl-0x4
035c 28fc: 48 89 44 24 30 mov %rax,0x30(%rsp)
0361 2901: 48 85 c0 test %rax,%rax
0364 2904: 79 5c jns 2962 <do_machine_check+0x3c2>
0366 2906: f6 05 00 00 00 00 04 testb $0x4,0x0(%rip) # 290d <do_machine_check+0x36d> 2908: R_X86_64_PC32 mca_cfg-0x5
036d 290d: 48 ba 00 00 00 00 00 00 00 01 movabs $0x100000000000000,%rdx
0377 2917: 48 b9 00 00 00 00 00 00 00 20 movabs $0x2000000000000000,%rcx
0381 2921: 48 0f 44 d1 cmove %rcx,%rdx
0385 2925: 48 85 d0 test %rdx,%rax
0388 2928: 75 05 jne 292f <do_machine_check+0x38f>
038a 292a: 45 85 ff test %r15d,%r15d
038d 292d: 74 33 je 2962 <do_machine_check+0x3c2>
038f 292f: 31 d2 xor %edx,%edx
0391 2931: b9 01 00 00 00 mov $0x1,%ecx
0396 2936: 48 89 ee mov %rbp,%rsi
0399 2939: 48 89 df mov %rbx,%rdi
039c 293c: e8 00 00 00 00 call 2941 <do_machine_check+0x3a1> 293d: R_X86_64_PLT32 mce_severity-0x4
03a1 2941: 41 83 c4 01 add $0x1,%r12d
03a5 2945: 8d 50 ff lea -0x1(%rax),%edx
03a8 2948: 83 fa 01 cmp $0x1,%edx
03ab 294b: 0f 86 0f 02 00 00 jbe 2b60 <do_machine_check+0x5c0>
03b1 2951: 4c 0f ab ac 24 b8 00 00 00 bts %r13,0xb8(%rsp)
03ba 295a: 85 c0 test %eax,%eax
03bc 295c: 0f 85 10 02 00 00 jne 2b72 <do_machine_check+0x5d2>
03c2 2962: 41 83 c6 01 add $0x1,%r14d
03c6 2966: 8b 05 00 00 00 00 mov 0x0(%rip),%eax # 296c <do_machine_check+0x3cc> 2968: R_X86_64_PC32 mce_num_banks-0x4
03cc 296c: 41 39 c6 cmp %eax,%r14d
03cf 296f: 0f 82 2a ff ff ff jb 289f <do_machine_check+0x2ff>
03d5 2975: 44 8b 7c 24 1c mov 0x1c(%rsp),%r15d
03da 297a: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2981 <do_machine_check+0x3e1> 297d: R_X86_64_PC32 .data+0xb285c
03e1 2981: 48 89 54 24 30 mov %rdx,0x30(%rsp)
03e6 2986: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 298d <do_machine_check+0x3ed> 2989: R_X86_64_PC32 .data+0xb2864
03ed 298d: 48 89 54 24 38 mov %rdx,0x38(%rsp)
03f2 2992: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2999 <do_machine_check+0x3f9> 2995: R_X86_64_PC32 .data+0xb286c
03f9 2999: 48 89 54 24 40 mov %rdx,0x40(%rsp)
03fe 299e: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29a5 <do_machine_check+0x405> 29a1: R_X86_64_PC32 .data+0xb2874
0405 29a5: 48 89 54 24 48 mov %rdx,0x48(%rsp)
040a 29aa: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29b1 <do_machine_check+0x411> 29ad: R_X86_64_PC32 .data+0xb287c
0411 29b1: 48 89 54 24 50 mov %rdx,0x50(%rsp)
0416 29b6: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29bd <do_machine_check+0x41d> 29b9: R_X86_64_PC32 .data+0xb2884
041d 29bd: 48 89 54 24 58 mov %rdx,0x58(%rsp)
0422 29c2: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29c9 <do_machine_check+0x429> 29c5: R_X86_64_PC32 .data+0xb288c
0429 29c9: 48 89 54 24 60 mov %rdx,0x60(%rsp)
042e 29ce: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29d5 <do_machine_check+0x435> 29d1: R_X86_64_PC32 .data+0xb2894
0435 29d5: 48 89 54 24 68 mov %rdx,0x68(%rsp)
043a 29da: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29e1 <do_machine_check+0x441> 29dd: R_X86_64_PC32 .data+0xb289c
0441 29e1: 48 89 54 24 70 mov %rdx,0x70(%rsp)
0446 29e6: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29ed <do_machine_check+0x44d> 29e9: R_X86_64_PC32 .data+0xb28a4
044d 29ed: 48 89 54 24 78 mov %rdx,0x78(%rsp)
0452 29f2: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 29f9 <do_machine_check+0x459> 29f5: R_X86_64_PC32 .data+0xb28ac
0459 29f9: 48 89 94 24 80 00 00 00 mov %rdx,0x80(%rsp)
0461 2a01: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2a08 <do_machine_check+0x468> 2a04: R_X86_64_PC32 .data+0xb28b4
0468 2a08: 48 89 94 24 88 00 00 00 mov %rdx,0x88(%rsp)
0470 2a10: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2a17 <do_machine_check+0x477> 2a13: R_X86_64_PC32 .data+0xb28bc
0477 2a17: 48 89 94 24 90 00 00 00 mov %rdx,0x90(%rsp)
047f 2a1f: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2a26 <do_machine_check+0x486> 2a22: R_X86_64_PC32 .data+0xb28c4
0486 2a26: 48 89 94 24 98 00 00 00 mov %rdx,0x98(%rsp)
048e 2a2e: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2a35 <do_machine_check+0x495> 2a31: R_X86_64_PC32 .data+0xb28cc
0495 2a35: 48 89 94 24 a0 00 00 00 mov %rdx,0xa0(%rsp)
049d 2a3d: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 2a44 <do_machine_check+0x4a4> 2a40: R_X86_64_PC32 .data+0xb28d4
04a4 2a44: 48 89 94 24 a8 00 00 00 mov %rdx,0xa8(%rsp)
04ac 2a4c: 45 85 ff test %r15d,%r15d
04af 2a4f: 75 40 jne 2a91 <do_machine_check+0x4f1>
04b1 2a51: 8b 15 00 00 00 00 mov 0x0(%rip),%edx # 2a57 <do_machine_check+0x4b7> 2a53: R_X86_64_PC32 mce_num_banks-0x4
04b7 2a57: 85 d2 test %edx,%edx
04b9 2a59: 74 36 je 2a91 <do_machine_check+0x4f1>
04bb 2a5b: 41 be 01 20 00 c0 mov $0xc0002001,%r14d
04c1 2a61: 49 63 c7 movslq %r15d,%rax
04c4 2a64: 48 0f a3 84 24 b8 00 00 00 bt %rax,0xb8(%rsp)
04cd 2a6d: 73 0f jae 2a7e <do_machine_check+0x4de>
04cf 2a6f: e9 00 00 00 00 jmp 2a74 <do_machine_check+0x4d4> 2a70: R_X86_64_PC32 .altinstr_aux+0xe8a
04d4 2a74: 44 89 f7 mov %r14d,%edi
04d7 2a77: 31 f6 xor %esi,%esi
04d9 2a79: e8 52 f2 ff ff call 1cd0 <mce_wrmsrl>
04de 2a7e: 41 83 c7 01 add $0x1,%r15d
04e2 2a82: 8b 05 00 00 00 00 mov 0x0(%rip),%eax # 2a88 <do_machine_check+0x4e8> 2a84: R_X86_64_PC32 mce_num_banks-0x4
04e8 2a88: 41 83 c6 10 add $0x10,%r14d
04ec 2a8c: 41 39 c7 cmp %eax,%r15d
04ef 2a8f: 72 d0 jb 2a61 <do_machine_check+0x4c1>
04f1 2a91: 8b 54 24 04 mov 0x4(%rsp),%edx
04f5 2a95: 85 d2 test %edx,%edx
04f7 2a97: 0f 84 66 02 00 00 je 2d03 <do_machine_check+0x763>
04fd 2a9d: 83 3c 24 06 cmpl $0x6,(%rsp)
0501 2aa1: 0f 8f 1f 03 00 00 jg 2dc6 <do_machine_check+0x826>
0507 2aa7: 90 nop
0508 2aa8: 45 85 e4 test %r12d,%r12d
050b 2aab: 0f 85 01 03 00 00 jne 2db2 <do_machine_check+0x812>
0511 2ab1: 83 3c 24 06 cmpl $0x6,(%rsp)
0515 2ab5: 74 07 je 2abe <do_machine_check+0x51e>
0517 2ab7: f6 44 24 08 01 testb $0x1,0x8(%rsp)
051c 2abc: 75 33 jne 2af1 <do_machine_check+0x551>
051e 2abe: 0f b6 44 24 70 movzbl 0x70(%rsp),%eax
0523 2ac3: 83 e0 03 and $0x3,%eax
0526 2ac6: 3c 03 cmp $0x3,%al
0528 2ac8: 0f 84 98 02 00 00 je 2d66 <do_machine_check+0x7c6>
052e 2ace: f6 44 24 49 10 testb $0x10,0x49(%rsp)
0533 2ad3: 0f 85 34 03 00 00 jne 2e0d <do_machine_check+0x86d>
0539 2ad9: 48 8b 84 24 a8 00 00 00 mov 0xa8(%rsp),%rax
0541 2ae1: a8 40 test $0x40,%al
0543 2ae3: 0f 85 f4 01 00 00 jne 2cdd <do_machine_check+0x73d>
0549 2ae9: a8 80 test $0x80,%al
054b 2aeb: 0f 85 d3 01 00 00 jne 2cc4 <do_machine_check+0x724>
0551 2af1: 90 nop
0552 2af2: 31 f6 xor %esi,%esi
0554 2af4: bf 7a 01 00 00 mov $0x17a,%edi
0559 2af9: e8 d2 f1 ff ff call 1cd0 <mce_wrmsrl>
055e 2afe: 48 8b 84 24 c0 00 00 00 mov 0xc0(%rsp),%rax
0566 2b06: 65 48 2b 04 25 28 00 00 00 sub %gs:0x28,%rax
056f 2b0f: 0f 85 77 03 00 00 jne 2e8c <do_machine_check+0x8ec>
0575 2b15: 48 81 c4 c8 00 00 00 add $0xc8,%rsp
057c 2b1c: 5b pop %rbx
057d 2b1d: 5d pop %rbp
057e 2b1e: 41 5c pop %r12
0580 2b20: 41 5d pop %r13
0582 2b22: 41 5e pop %r14
0584 2b24: 41 5f pop %r15
0586 2b26: e9 00 00 00 00 jmp 2b2b <do_machine_check+0x58b> 2b27: R_X86_64_PLT32 __x86_return_thunk-0x4
058b 2b2b: e8 50 f9 ff ff call 2480 <quirk_skylake_repmov>
0590 2b30: 84 c0 test %al,%al
0592 2b32: 0f 84 02 fb ff ff je 263a <do_machine_check+0x9a>
0598 2b38: 31 f6 xor %esi,%esi
059a 2b3a: bf 7a 01 00 00 mov $0x17a,%edi
059f 2b3f: e8 8c f1 ff ff call 1cd0 <mce_wrmsrl>
05a4 2b44: eb b8 jmp 2afe <do_machine_check+0x55e>
05a6 2b46: 42 8d 3c b5 01 04 00 00 lea 0x401(,%r14,4),%edi
05ae 2b4e: e9 a4 fd ff ff jmp 28f7 <do_machine_check+0x357>
05b3 2b53: 42 8d 3c bd 01 04 00 00 lea 0x401(,%r15,4),%edi
05bb 2b5b: e9 17 ff ff ff jmp 2a77 <do_machine_check+0x4d7>
05c0 2b60: 45 85 ff test %r15d,%r15d
05c3 2b63: 0f 84 f9 fd ff ff je 2962 <do_machine_check+0x3c2>
05c9 2b69: 4c 0f ab ac 24 b8 00 00 00 bts %r13,0xb8(%rsp)
05d2 2b72: 44 89 f6 mov %r14d,%esi
05d5 2b75: 48 89 df mov %rbx,%rdi
05d8 2b78: 89 44 24 10 mov %eax,0x10(%rsp)
05dc 2b7c: e8 8f f7 ff ff call 2310 <mce_read_aux>
05e1 2b81: 8b 44 24 10 mov 0x10(%rsp),%eax
05e5 2b85: 88 44 24 6a mov %al,0x6a(%rsp)
05e9 2b89: 90 nop
05ea 2b8a: 48 89 df mov %rbx,%rdi
05ed 2b8d: e8 00 00 00 00 call 2b92 <do_machine_check+0x5f2> 2b8e: R_X86_64_PLT32 mce_log-0x4
05f2 2b92: 90 nop
05f3 2b93: 8b 0c 24 mov (%rsp),%ecx
05f6 2b96: 8b 44 24 10 mov 0x10(%rsp),%eax
05fa 2b9a: 39 c8 cmp %ecx,%eax
05fc 2b9c: 0f 8e c0 fd ff ff jle 2962 <do_machine_check+0x3c2>
0602 2ba2: 48 8b 54 24 30 mov 0x30(%rsp),%rdx
0607 2ba7: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bae <do_machine_check+0x60e> 2baa: R_X86_64_PC32 .data+0xb285c
060e 2bae: 48 8b 54 24 38 mov 0x38(%rsp),%rdx
0613 2bb3: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bba <do_machine_check+0x61a> 2bb6: R_X86_64_PC32 .data+0xb2864
061a 2bba: 48 8b 54 24 40 mov 0x40(%rsp),%rdx
061f 2bbf: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bc6 <do_machine_check+0x626> 2bc2: R_X86_64_PC32 .data+0xb286c
0626 2bc6: 48 8b 54 24 48 mov 0x48(%rsp),%rdx
062b 2bcb: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bd2 <do_machine_check+0x632> 2bce: R_X86_64_PC32 .data+0xb2874
0632 2bd2: 48 8b 54 24 50 mov 0x50(%rsp),%rdx
0637 2bd7: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bde <do_machine_check+0x63e> 2bda: R_X86_64_PC32 .data+0xb287c
063e 2bde: 48 8b 54 24 58 mov 0x58(%rsp),%rdx
0643 2be3: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bea <do_machine_check+0x64a> 2be6: R_X86_64_PC32 .data+0xb2884
064a 2bea: 48 8b 54 24 60 mov 0x60(%rsp),%rdx
064f 2bef: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2bf6 <do_machine_check+0x656> 2bf2: R_X86_64_PC32 .data+0xb288c
0656 2bf6: 48 8b 54 24 68 mov 0x68(%rsp),%rdx
065b 2bfb: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c02 <do_machine_check+0x662> 2bfe: R_X86_64_PC32 .data+0xb2894
0662 2c02: 48 8b 54 24 70 mov 0x70(%rsp),%rdx
0667 2c07: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c0e <do_machine_check+0x66e> 2c0a: R_X86_64_PC32 .data+0xb289c
066e 2c0e: 48 8b 54 24 78 mov 0x78(%rsp),%rdx
0673 2c13: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c1a <do_machine_check+0x67a> 2c16: R_X86_64_PC32 .data+0xb28a4
067a 2c1a: 48 8b 94 24 80 00 00 00 mov 0x80(%rsp),%rdx
0682 2c22: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c29 <do_machine_check+0x689> 2c25: R_X86_64_PC32 .data+0xb28ac
0689 2c29: 48 8b 94 24 88 00 00 00 mov 0x88(%rsp),%rdx
0691 2c31: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c38 <do_machine_check+0x698> 2c34: R_X86_64_PC32 .data+0xb28b4
0698 2c38: 48 8b 94 24 90 00 00 00 mov 0x90(%rsp),%rdx
06a0 2c40: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c47 <do_machine_check+0x6a7> 2c43: R_X86_64_PC32 .data+0xb28bc
06a7 2c47: 48 8b 94 24 98 00 00 00 mov 0x98(%rsp),%rdx
06af 2c4f: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c56 <do_machine_check+0x6b6> 2c52: R_X86_64_PC32 .data+0xb28c4
06b6 2c56: 48 8b 94 24 a0 00 00 00 mov 0xa0(%rsp),%rdx
06be 2c5e: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c65 <do_machine_check+0x6c5> 2c61: R_X86_64_PC32 .data+0xb28cc
06c5 2c65: 48 8b 94 24 a8 00 00 00 mov 0xa8(%rsp),%rdx
06cd 2c6d: 48 89 15 00 00 00 00 mov %rdx,0x0(%rip) # 2c74 <do_machine_check+0x6d4> 2c70: R_X86_64_PC32 .data+0xb28d4
06d4 2c74: 89 04 24 mov %eax,(%rsp)
06d7 2c77: e9 e6 fc ff ff jmp 2962 <do_machine_check+0x3c2>
06dc 2c7c: 8b 44 24 08 mov 0x8(%rsp),%eax
06e0 2c80: 83 e0 08 and $0x8,%eax
06e3 2c83: 89 44 24 04 mov %eax,0x4(%rsp)
06e7 2c87: 0f 85 e1 fb ff ff jne 286e <do_machine_check+0x2ce>
06ed 2c8d: 48 8d 7c 24 1c lea 0x1c(%rsp),%rdi
06f2 2c92: e8 89 f3 ff ff call 2020 <mce_start>
06f7 2c97: 44 8b 7c 24 1c mov 0x1c(%rsp),%r15d
06fc 2c9c: 89 44 24 14 mov %eax,0x14(%rsp)
0700 2ca0: e9 df fb ff ff jmp 2884 <do_machine_check+0x2e4>
0705 2ca5: 44 89 e6 mov %r12d,%esi
0708 2ca8: 48 89 df mov %rbx,%rdi
070b 2cab: e8 60 f6 ff ff call 2310 <mce_read_aux>
0710 2cb0: 48 8b 44 24 28 mov 0x28(%rsp),%rax
0715 2cb5: 48 89 44 24 20 mov %rax,0x20(%rsp)
071a 2cba: b8 01 00 00 00 mov $0x1,%eax
071f 2cbf: e9 7f fb ff ff jmp 2843 <do_machine_check+0x2a3>
0724 2cc4: 48 8b 74 24 20 mov 0x20(%rsp),%rsi
0729 2cc9: 48 c7 c2 00 00 00 00 mov $0x0,%rdx 2ccc: R_X86_64_32S .text+0xc5300
0730 2cd0: 48 89 df mov %rbx,%rdi
0733 2cd3: e8 00 00 00 00 call 2cd8 <do_machine_check+0x738> 2cd4: R_X86_64_PC32 .text+0xc6bdc
0738 2cd8: e9 14 fe ff ff jmp 2af1 <do_machine_check+0x551>
073d 2cdd: 31 c9 xor %ecx,%ecx
073f 2cdf: 31 d2 xor %edx,%edx
0741 2ce1: be 12 00 00 00 mov $0x12,%esi
0746 2ce6: 48 89 ef mov %rbp,%rdi
0749 2ce9: e8 00 00 00 00 call 2cee <do_machine_check+0x74e> 2cea: R_X86_64_PLT32 fixup_exception-0x4
074e 2cee: 85 c0 test %eax,%eax
0750 2cf0: 0f 84 7a 01 00 00 je 2e70 <do_machine_check+0x8d0>
0756 2cf6: 48 8b 84 24 a8 00 00 00 mov 0xa8(%rsp),%rax
075e 2cfe: e9 e6 fd ff ff jmp 2ae9 <do_machine_check+0x549>
0763 2d03: 8b 7c 24 14 mov 0x14(%rsp),%edi
0767 2d07: e8 44 f4 ff ff call 2150 <mce_end>
076c 2d0c: 85 c0 test %eax,%eax
076e 2d0e: 0f 89 93 fd ff ff jns 2aa7 <do_machine_check+0x507>
0774 2d14: 8b 44 24 1c mov 0x1c(%rsp),%eax
0778 2d18: 85 c0 test %eax,%eax
077a 2d1a: 75 13 jne 2d2f <do_machine_check+0x78f>
077c 2d1c: 31 c0 xor %eax,%eax
077e 2d1e: 83 3c 24 06 cmpl $0x6,(%rsp)
0782 2d22: 0f 9f c0 setg %al
0785 2d25: 89 44 24 1c mov %eax,0x1c(%rsp)
0789 2d29: 0f 8e 78 fd ff ff jle 2aa7 <do_machine_check+0x507>
078f 2d2f: 48 8b 54 24 20 mov 0x20(%rsp),%rdx
0794 2d34: 48 89 de mov %rbx,%rsi
0797 2d37: 48 c7 c7 00 00 00 00 mov $0x0,%rdi 2d3a: R_X86_64_32S .rodata+0x3ac80
079e 2d3e: e8 6d f0 ff ff call 1db0 <mce_panic>
07a3 2d43: e9 5f fd ff ff jmp 2aa7 <do_machine_check+0x507>
07a8 2d48: 48 8b 54 24 20 mov 0x20(%rsp),%rdx
07ad 2d4d: 48 89 de mov %rbx,%rsi
07b0 2d50: 48 c7 c7 00 00 00 00 mov $0x0,%rdi 2d53: R_X86_64_32S .rodata+0x3ac40
07b7 2d57: e8 54 f0 ff ff call 1db0 <mce_panic>
07bc 2d5c: 44 8b 7c 24 1c mov 0x1c(%rsp),%r15d
07c1 2d61: e9 1e fb ff ff jmp 2884 <do_machine_check+0x2e4>
07c6 2d66: 48 8b 05 00 00 00 00 mov 0x0(%rip),%rax # 2d6d <do_machine_check+0x7cd> 2d69: R_X86_64_PC32 pcpu_hot+0x14
07cd 2d6d: 48 29 e0 sub %rsp,%rax
07d0 2d70: 48 3d ff 7f 00 00 cmp $0x7fff,%rax
07d6 2d76: 0f 87 0d 01 00 00 ja 2e89 <do_machine_check+0x8e9>
07dc 2d7c: f6 85 88 00 00 00 03 testb $0x3,0x88(%rbp)
07e3 2d83: 0f 84 00 01 00 00 je 2e89 <do_machine_check+0x8e9>
07e9 2d89: 48 89 df mov %rbx,%rdi
07ec 2d8c: e8 00 00 00 00 call 2d91 <do_machine_check+0x7f1> 2d8d: R_X86_64_PLT32 mce_usable_address-0x4
07f1 2d91: 84 c0 test %al,%al
07f3 2d93: 0f 85 be 00 00 00 jne 2e57 <do_machine_check+0x8b7>
07f9 2d99: 48 8b 74 24 20 mov 0x20(%rsp),%rsi
07fe 2d9e: 48 c7 c2 00 00 00 00 mov $0x0,%rdx 2da1: R_X86_64_32S .text+0xc5450
0805 2da5: 48 89 df mov %rbx,%rdi
0808 2da8: e8 00 00 00 00 call 2dad <do_machine_check+0x80d> 2da9: R_X86_64_PC32 .text+0xc6bdc
080d 2dad: e9 3f fd ff ff jmp 2af1 <do_machine_check+0x551>
0812 2db2: be 01 00 00 00 mov $0x1,%esi
0817 2db7: bf 04 00 00 00 mov $0x4,%edi
081c 2dbc: e8 00 00 00 00 call 2dc1 <do_machine_check+0x821> 2dbd: R_X86_64_PLT32 add_taint-0x4
0821 2dc1: e9 eb fc ff ff jmp 2ab1 <do_machine_check+0x511>
0826 2dc6: b9 01 00 00 00 mov $0x1,%ecx
082b 2dcb: 48 89 ee mov %rbp,%rsi
082e 2dce: 48 8d 54 24 20 lea 0x20(%rsp),%rdx
0833 2dd3: 48 89 df mov %rbx,%rdi
0836 2dd6: e8 00 00 00 00 call 2ddb <do_machine_check+0x83b> 2dd7: R_X86_64_PLT32 mce_severity-0x4
083b 2ddb: 48 8b 54 24 20 mov 0x20(%rsp),%rdx
0840 2de0: 48 89 de mov %rbx,%rsi
0843 2de3: 48 c7 c7 00 00 00 00 mov $0x0,%rdi 2de6: R_X86_64_32S .rodata+0x3ace0
084a 2dea: e8 c1 ef ff ff call 1db0 <mce_panic>
084f 2def: 90 nop
0850 2df0: 45 85 e4 test %r12d,%r12d
0853 2df3: 0f 84 be fc ff ff je 2ab7 <do_machine_check+0x517>
0859 2df9: be 01 00 00 00 mov $0x1,%esi
085e 2dfe: bf 04 00 00 00 mov $0x4,%edi
0863 2e03: e8 00 00 00 00 call 2e08 <do_machine_check+0x868> 2e04: R_X86_64_PLT32 add_taint-0x4
0868 2e08: e9 aa fc ff ff jmp 2ab7 <do_machine_check+0x517>
086d 2e0d: 48 89 df mov %rbx,%rdi
0870 2e10: e8 00 00 00 00 call 2e15 <do_machine_check+0x875> 2e11: R_X86_64_PLT32 mce_usable_address-0x4
0875 2e15: 84 c0 test %al,%al
0877 2e17: 0f 84 d4 fc ff ff je 2af1 <do_machine_check+0x551>
087d 2e1d: 48 8b 7c 24 40 mov 0x40(%rsp),%rdi
0882 2e22: 48 c1 ef 0c shr $0xc,%rdi
0886 2e26: e8 00 00 00 00 call 2e2b <do_machine_check+0x88b> 2e27: R_X86_64_PLT32 pfn_to_online_page-0x4
088b 2e2b: 48 89 c3 mov %rax,%rbx
088e 2e2e: 48 85 c0 test %rax,%rax
0891 2e31: 0f 84 ba fc ff ff je 2af1 <do_machine_check+0x551>
0897 2e37: be 08 00 00 00 mov $0x8,%esi
089c 2e3c: 48 89 c7 mov %rax,%rdi
089f 2e3f: e8 00 00 00 00 call 2e44 <do_machine_check+0x8a4> 2e40: R_X86_64_PLT32 __kasan_check_write-0x4
08a4 2e44: 80 4b 02 20 orb $0x20,0x2(%rbx)
08a8 2e48: e9 a4 fc ff ff jmp 2af1 <do_machine_check+0x551>
08ad 2e4d: e8 2e ef ff ff call 1d80 <unexpected_machine_check.constprop.0>
08b2 2e52: e9 a7 fc ff ff jmp 2afe <do_machine_check+0x55e>
08b7 2e57: 48 8b 74 24 20 mov 0x20(%rsp),%rsi
08bc 2e5c: 48 c7 c2 00 00 00 00 mov $0x0,%rdx 2e5f: R_X86_64_32S .text+0xc54b0
08c3 2e63: 48 89 df mov %rbx,%rdi
08c6 2e66: e8 00 00 00 00 call 2e6b <do_machine_check+0x8cb> 2e67: R_X86_64_PC32 .text+0xc6bdc
08cb 2e6b: e9 81 fc ff ff jmp 2af1 <do_machine_check+0x551>
08d0 2e70: 48 8b 54 24 20 mov 0x20(%rsp),%rdx
08d5 2e75: 48 89 de mov %rbx,%rsi
08d8 2e78: 48 c7 c7 00 00 00 00 mov $0x0,%rdi 2e7b: R_X86_64_32S .rodata+0x3ad20
08df 2e7f: e8 2c ef ff ff call 1db0 <mce_panic>
08e4 2e84: e9 6d fe ff ff jmp 2cf6 <do_machine_check+0x756>
08e9 2e89: 90 nop
08ea 2e8a: 0f 0b ud2
08ec 2e8c: e8 00 00 00 00 call 2e91 <do_machine_check+0x8f1> 2e8d: R_X86_64_PLT32 __stack_chk_fail-0x4
08f1 2e91: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 cs nopw 0x0(%rax,%rax,1)
08fc 2e9c: 0f 1f 40 00 nopl 0x0(%rax)
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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2024-07-30 18:54 [PATCH v3 0/4] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 1/4] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
2024-08-03 15:24 ` kernel test robot
2024-07-30 18:54 ` [PATCH v3 2/4] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 3/4] x86/mce/apei: Handle variable register array size Avadhut Naik
2024-07-30 18:54 ` [PATCH v3 4/4] EDAC/mce_amd: Add support for FRU Text in MCA Avadhut Naik
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