[PATCH v3 0/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[PATCH v3 0/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[Josua Mayer]

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v3:
- reused existing control register definition from sdhci-esdhc.h
  (Reported-by: Bough Chen <haibo.chen@nxp.com>)
- placed both control register mask definitions next to each other
- fixed timeout write register name
- Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com

Changes in v2:
- replaced udelay with usleep_range
  (Reported-by: Adrian Hunter <adrian.hunter@intel.com>)
- added comments for delay values
  (Reported-by: Peng Fan <peng.fan@nxp.com>)
- delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation,
  on page 159
  (Thanks to Bough Chen <haibo.chen@nxp.com>)
- added a second patch demonstrating a cosmetic issue revealed by first
  patch - it bothered me during development but is not important
- Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com

---
Josua Mayer (2):
      mmc: host: sdhci-esdhc-imx: implement emmc hardware reset
      mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask

 drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)
---
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
change-id: 20241027-imx-emmc-reset-7127d311174c

Best regards,
-- 
Josua Mayer <josua@solid-run.com>

[PATCH v3 1/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[Josua Mayer]

NXP ESDHC supports control of native emmc reset signal when pinmux is
set accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit.
Documentation is available in NXP i.MX6Q Reference Manual.

Implement the hw_reset function in sdhci_ops asserting reset for at
least 1us and waiting at least 200us after deassertion.
Lower bounds are based on:
JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159.
Upper bounds are chosen allowing flexibility to the scheduler.

Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is
still accessible after boot:
- eMMC extcsd has RST_N_FUNCTION=0x01
- sdhc node has cap-mmc-hw-reset
- pinmux set for EMMC0_RESET_B
- Linux v5.15

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8f0bc6dca2b0402fd2a0695903cf261a5b4e19dc..f106e291c276d0c8063e9ac59a126acf5e9e239e 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -31,6 +31,7 @@
 #include "cqhci.h"
 
 #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
+#define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
 #define	ESDHC_CTRL_D3CD			0x08
 #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
 /* VENDOR SPEC register */
@@ -1402,6 +1403,17 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
 	return 0;
 }
 
+static void esdhc_hw_reset(struct sdhci_host *host)
+{
+	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYSTEM_CONTROL);
+	/* eMMC spec requires minimum 1us, here delay between 1-10us */
+	usleep_range(1, 10);
+	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N,
+			ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL);
+	/* eMMC spec requires minimum 200us, here delay between 200-300us */
+	usleep_range(200, 300);
+}
+
 static struct sdhci_ops sdhci_esdhc_ops = {
 	.read_l = esdhc_readl_le,
 	.read_w = esdhc_readw_le,
@@ -1420,6 +1432,7 @@ static struct sdhci_ops sdhci_esdhc_ops = {
 	.reset = esdhc_reset,
 	.irq = esdhc_cqhci_irq,
 	.dump_vendor_regs = esdhc_dump_debug_regs,
+	.hw_reset = esdhc_hw_reset,
 };
 
 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {

-- 
2.43.0

[PATCH v3 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask

[Josua Mayer]

NXP ESDHC supports setting data timeout using uSDHCx_SYS_CTRL register
DTOCV bits (bits 16-19).
Currently the driver accesses those bits by 32-bit write using
SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h.
This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C).
The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which
is correct relative to SDHCI_TIMEOUT_CONTROL but not relative to
uSDHCx_SYS_CTRL. The definition carrying control register in its name is
therefore inconsistent.

Update the bitmask definition for bits 16-19 to be correct relative to
control register base.
Update the esdhc_set_timeout function to set timeout value at control
register base, not timeout offset.

This solves a purely cosmetic problem.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index f106e291c276d0c8063e9ac59a126acf5e9e239e..cda3cc4cc22cfa214369f40f097ca50937898604 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -30,7 +30,7 @@
 #include "sdhci-esdhc.h"
 #include "cqhci.h"
 
-#define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
+#define ESDHC_SYS_CTRL_DTOCV_MASK	GENMASK(19, 16)
 #define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
 #define	ESDHC_CTRL_D3CD			0x08
 #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
@@ -1386,8 +1386,8 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 
 	/* use maximum timeout counter */
 	esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
-			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
-			SDHCI_TIMEOUT_CONTROL);
+			esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000,
+			ESDHC_SYSTEM_CONTROL);
 }
 
 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)

-- 
2.43.0

RE: [PATCH v3 1/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[Bough Chen]

> -----Original Message-----
> From: Josua Mayer <josua@solid-run.com>
> Sent: 2024年11月1日 19:42
> To: Adrian Hunter <adrian.hunter@intel.com>; Bough Chen
> <haibo.chen@nxp.com>; Ulf Hansson <ulf.hansson@linaro.org>; Shawn Guo
> <shawnguo@kernel.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
> <festevam@gmail.com>
> Cc: Mikhail Anikin <mikhail.anikin@solid-run.com>; Jon Nettleton
> <jon@solid-run.com>; yazan.shhady <yazan.shhady@solid-run.com>; Rabeeh
> Khoury <rabeeh@solid-run.com>; imx@lists.linux.dev;
> linux-mmc@vger.kernel.org; dl-S32 <S32@nxp.com>;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Josua
> Mayer <josua@solid-run.com>
> Subject: [PATCH v3 1/2] mmc: host: sdhci-esdhc-imx: implement emmc
> hardware reset
> 
> NXP ESDHC supports control of native emmc reset signal when pinmux is set
> accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit.
> Documentation is available in NXP i.MX6Q Reference Manual.
> 
> Implement the hw_reset function in sdhci_ops asserting reset for at least 1us
> and waiting at least 200us after deassertion.
> Lower bounds are based on:
> JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159.
> Upper bounds are chosen allowing flexibility to the scheduler.
> 
> Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is
> still accessible after boot:
> - eMMC extcsd has RST_N_FUNCTION=0x01
> - sdhc node has cap-mmc-hw-reset
> - pinmux set for EMMC0_RESET_B
> - Linux v5.15

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

Best Regards
Haibo Chen
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index
> 8f0bc6dca2b0402fd2a0695903cf261a5b4e19dc..f106e291c276d0c8063e9ac59
> a126acf5e9e239e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -31,6 +31,7 @@
>  #include "cqhci.h"
> 
>  #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
> +#define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
>  #define	ESDHC_CTRL_D3CD			0x08
>  #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
>  /* VENDOR SPEC register */
> @@ -1402,6 +1403,17 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host,
> u32 intmask)
>  	return 0;
>  }
> 
> +static void esdhc_hw_reset(struct sdhci_host *host) {
> +	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0,
> ESDHC_SYSTEM_CONTROL);
> +	/* eMMC spec requires minimum 1us, here delay between 1-10us */
> +	usleep_range(1, 10);
> +	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N,
> +			ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL);
> +	/* eMMC spec requires minimum 200us, here delay between 200-300us */
> +	usleep_range(200, 300);
> +}
> +
>  static struct sdhci_ops sdhci_esdhc_ops = {
>  	.read_l = esdhc_readl_le,
>  	.read_w = esdhc_readw_le,
> @@ -1420,6 +1432,7 @@ static struct sdhci_ops sdhci_esdhc_ops = {
>  	.reset = esdhc_reset,
>  	.irq = esdhc_cqhci_irq,
>  	.dump_vendor_regs = esdhc_dump_debug_regs,
> +	.hw_reset = esdhc_hw_reset,
>  };
> 
>  static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
> 
> --
> 2.43.0

RE: [PATCH v3 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask

[Bough Chen]

> -----Original Message-----
> From: Josua Mayer <josua@solid-run.com>
> Sent: 2024年11月1日 19:42
> To: Adrian Hunter <adrian.hunter@intel.com>; Bough Chen
> <haibo.chen@nxp.com>; Ulf Hansson <ulf.hansson@linaro.org>; Shawn Guo
> <shawnguo@kernel.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
> <festevam@gmail.com>
> Cc: Mikhail Anikin <mikhail.anikin@solid-run.com>; Jon Nettleton
> <jon@solid-run.com>; yazan.shhady <yazan.shhady@solid-run.com>; Rabeeh
> Khoury <rabeeh@solid-run.com>; imx@lists.linux.dev;
> linux-mmc@vger.kernel.org; dl-S32 <S32@nxp.com>;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Josua
> Mayer <josua@solid-run.com>
> Subject: [PATCH v3 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv
> bitmask
> 
> NXP ESDHC supports setting data timeout using uSDHCx_SYS_CTRL register
> DTOCV bits (bits 16-19).
> Currently the driver accesses those bits by 32-bit write using
> SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h.
> This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C).
> The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which is
> correct relative to SDHCI_TIMEOUT_CONTROL but not relative to
> uSDHCx_SYS_CTRL. The definition carrying control register in its name is
> therefore inconsistent.
> 
> Update the bitmask definition for bits 16-19 to be correct relative to control
> register base.
> Update the esdhc_set_timeout function to set timeout value at control register
> base, not timeout offset.
> 
> This solves a purely cosmetic problem.

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

Best Regards
Haibo Chen
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index
> f106e291c276d0c8063e9ac59a126acf5e9e239e..cda3cc4cc22cfa214369f40f09
> 7ca50937898604 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -30,7 +30,7 @@
>  #include "sdhci-esdhc.h"
>  #include "cqhci.h"
> 
> -#define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
> +#define ESDHC_SYS_CTRL_DTOCV_MASK	GENMASK(19, 16)
>  #define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
>  #define	ESDHC_CTRL_D3CD			0x08
>  #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
> @@ -1386,8 +1386,8 @@ static void esdhc_set_timeout(struct sdhci_host
> *host, struct mmc_command *cmd)
> 
>  	/* use maximum timeout counter */
>  	esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
> -			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
> -			SDHCI_TIMEOUT_CONTROL);
> +			esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000,
> +			ESDHC_SYSTEM_CONTROL);
>  }
> 
>  static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
> 
> --
> 2.43.0

Re: [PATCH v3 0/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[Adrian Hunter]

On 1/11/24 13:42, Josua Mayer wrote:
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> Changes in v3:
> - reused existing control register definition from sdhci-esdhc.h
>   (Reported-by: Bough Chen <haibo.chen@nxp.com>)
> - placed both control register mask definitions next to each other
> - fixed timeout write register name
> - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com
> 
> Changes in v2:
> - replaced udelay with usleep_range
>   (Reported-by: Adrian Hunter <adrian.hunter@intel.com>)
> - added comments for delay values
>   (Reported-by: Peng Fan <peng.fan@nxp.com>)
> - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation,
>   on page 159
>   (Thanks to Bough Chen <haibo.chen@nxp.com>)
> - added a second patch demonstrating a cosmetic issue revealed by first
>   patch - it bothered me during development but is not important
> - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com
> 
> ---
> Josua Mayer (2):
>       mmc: host: sdhci-esdhc-imx: implement emmc hardware reset
>       mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask

For both:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

Re: [PATCH v3 0/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

[Ulf Hansson]

On Fri, 1 Nov 2024 at 12:42, Josua Mayer <josua@solid-run.com> wrote:
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> Changes in v3:
> - reused existing control register definition from sdhci-esdhc.h
>   (Reported-by: Bough Chen <haibo.chen@nxp.com>)
> - placed both control register mask definitions next to each other
> - fixed timeout write register name
> - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com
>
> Changes in v2:
> - replaced udelay with usleep_range
>   (Reported-by: Adrian Hunter <adrian.hunter@intel.com>)
> - added comments for delay values
>   (Reported-by: Peng Fan <peng.fan@nxp.com>)
> - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation,
>   on page 159
>   (Thanks to Bough Chen <haibo.chen@nxp.com>)
> - added a second patch demonstrating a cosmetic issue revealed by first
>   patch - it bothered me during development but is not important
> - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com
>
> ---
> Josua Mayer (2):
>       mmc: host: sdhci-esdhc-imx: implement emmc hardware reset
>       mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask
>
>  drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)


The series applied for next, thanks!

Kind regards
Uffe