[PATCH] pinctrl-tegra: Add config property GPIO mode

[PATCH] pinctrl-tegra: Add config property GPIO mode

[Prathamesh Shete]

The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing
system:
- When set to 1, the pin operates in SFIO mode, controlled by the
  pin's assigned special function.
- When set to 0, the pin operates as a general-purpose GPIO.

This SFIO/GPIO select bit that is set for a given pin is not displayed,
adding the support to retrieve this information from the
pinmux set for each pin.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 11 +++++++++++
 drivers/pinctrl/tegra/pinctrl-tegra.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 9523b93008d0..b3501c78b5b6 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -96,6 +96,7 @@ static const struct cfg_param {
 	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},
+	{"nvidia,gpio-mode",		TEGRA_PINCONF_PARAM_GPIO_MODE},
 };
 
 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
@@ -476,6 +477,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 		*bit = g->drvtype_bit;
 		*width = 2;
 		break;
+	case TEGRA_PINCONF_PARAM_GPIO_MODE:
+		if (pmx->soc->sfsel_in_mux) {
+			*bank = g->mux_bank;
+			*reg = g->mux_reg;
+			*bit = g->sfsel_bit;
+			*width = 1;
+		} else {
+			*reg = -ENODEV;
+		}
+		break;
 	default:
 		dev_err(pmx->dev, "Invalid config param %04x\n", param);
 		return -ENOTSUPP;
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index b97136685f7a..a47ac519f3ec 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -60,6 +60,8 @@ enum tegra_pinconf_param {
 	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
 	/* argument: Integer, range is HW-dependant */
 	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
+	/* argument: Boolean */
+	TEGRA_PINCONF_PARAM_GPIO_MODE,
 };
 
 enum tegra_pinconf_pull {
-- 
2.17.1

Re: [PATCH] pinctrl-tegra: Add config property GPIO mode

[Thierry Reding]

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On Mon, Dec 09, 2024 at 03:43:14PM +0530, Prathamesh Shete wrote:
> The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing
> system:
> - When set to 1, the pin operates in SFIO mode, controlled by the
>   pin's assigned special function.
> - When set to 0, the pin operates as a general-purpose GPIO.
> 
> This SFIO/GPIO select bit that is set for a given pin is not displayed,
> adding the support to retrieve this information from the
> pinmux set for each pin.
> 
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
>  drivers/pinctrl/tegra/pinctrl-tegra.c | 11 +++++++++++
>  drivers/pinctrl/tegra/pinctrl-tegra.h |  2 ++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 9523b93008d0..b3501c78b5b6 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -96,6 +96,7 @@ static const struct cfg_param {
>  	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
>  	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
>  	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},
> +	{"nvidia,gpio-mode",		TEGRA_PINCONF_PARAM_GPIO_MODE},
>  };
>  
>  static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> @@ -476,6 +477,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
>  		*bit = g->drvtype_bit;
>  		*width = 2;
>  		break;
> +	case TEGRA_PINCONF_PARAM_GPIO_MODE:
> +		if (pmx->soc->sfsel_in_mux) {
> +			*bank = g->mux_bank;
> +			*reg = g->mux_reg;
> +			*bit = g->sfsel_bit;
> +			*width = 1;
> +		} else {
> +			*reg = -ENODEV;

I think this should be either -EINVAL or -ENOTSUPP. If you look at
pinconf_generic_dump_one() where this function is ultimately called, it
will ignore those errors as "legal" but print out an error for all other
error codes. Since this code will potentially execute on chips that
don't support SFSEL in the mux register, leaving -ENODEV here might spam
the output with error messages.

Thierry

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