* [PATCH] riscv: Implement smp_cond_load8/16() with Zawrs
@ 2024-12-16 3:22 guoren
2024-12-16 15:42 ` Andrew Jones
0 siblings, 1 reply; 3+ messages in thread
From: guoren @ 2024-12-16 3:22 UTC (permalink / raw)
To: paul.walmsley, palmer, guoren, bjorn, conor, leobras, alexghiti,
christoph.muellner
Cc: linux-riscv, linux-kernel, parri.andrea, ajones, ericchancf,
Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 4cadc56220fe..2bd42a11ff8f 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
{
unsigned long tmp;
+ u32 *__ptr32b;
+ ulong __s, __val, __mask;
+
asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
0, RISCV_ISA_EXT_ZAWRS, 1)
: : : : no_zawrs);
switch (size) {
case 1:
- fallthrough;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xf << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 2:
- /* RISC-V doesn't have lr instructions on byte and half-word. */
- goto no_zawrs;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xff << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 4:
asm volatile(
" lr.w %0, %1\n"
--
2.40.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] riscv: Implement smp_cond_load8/16() with Zawrs
2024-12-16 3:22 [PATCH] riscv: Implement smp_cond_load8/16() with Zawrs guoren
@ 2024-12-16 15:42 ` Andrew Jones
2024-12-17 1:22 ` Guo Ren
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Jones @ 2024-12-16 15:42 UTC (permalink / raw)
To: guoren
Cc: paul.walmsley, palmer, bjorn, conor, leobras, alexghiti,
christoph.muellner, linux-riscv, linux-kernel, parri.andrea,
ericchancf, Guo Ren
On Sun, Dec 15, 2024 at 10:22:53PM -0500, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index 4cadc56220fe..2bd42a11ff8f 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
> {
> unsigned long tmp;
>
> + u32 *__ptr32b;
> + ulong __s, __val, __mask;
> +
> asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
> 0, RISCV_ISA_EXT_ZAWRS, 1)
> : : : : no_zawrs);
>
> switch (size) {
> case 1:
> - fallthrough;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xf << __s;
This mask should be 0xff and the mask below should be 0xffff.
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 2:
> - /* RISC-V doesn't have lr instructions on byte and half-word. */
> - goto no_zawrs;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xff << __s;
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 4:
> asm volatile(
> " lr.w %0, %1\n"
> --
> 2.40.1
>
Thanks,
drew
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] riscv: Implement smp_cond_load8/16() with Zawrs
2024-12-16 15:42 ` Andrew Jones
@ 2024-12-17 1:22 ` Guo Ren
0 siblings, 0 replies; 3+ messages in thread
From: Guo Ren @ 2024-12-17 1:22 UTC (permalink / raw)
To: Andrew Jones
Cc: paul.walmsley, palmer, bjorn, conor, leobras, alexghiti,
christoph.muellner, linux-riscv, linux-kernel, parri.andrea,
ericchancf, Guo Ren
On Mon, Dec 16, 2024 at 11:42 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Sun, Dec 15, 2024 at 10:22:53PM -0500, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > RISC-V code uses the queued spinlock implementation, which calls
> > the macros smp_cond_load_acquire for one byte. So, complement the
> > implementation of byte and halfword versions.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
> > 1 file changed, 35 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> > index 4cadc56220fe..2bd42a11ff8f 100644
> > --- a/arch/riscv/include/asm/cmpxchg.h
> > +++ b/arch/riscv/include/asm/cmpxchg.h
> > @@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
> > {
> > unsigned long tmp;
> >
> > + u32 *__ptr32b;
> > + ulong __s, __val, __mask;
> > +
> > asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
> > 0, RISCV_ISA_EXT_ZAWRS, 1)
> > : : : : no_zawrs);
> >
> > switch (size) {
> > case 1:
> > - fallthrough;
> > + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> > + __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
> > + __val = val << __s;
> > + __mask = 0xf << __s;
>
> This mask should be 0xff and the mask below should be 0xffff.
Thx for catching it; it's hard to test it out. I will correct it in
the next version.
>
> > +
> > + asm volatile(
> > + " lr.w %0, %1\n"
> > + " and %0, %0, %3\n"
> > + " xor %0, %0, %2\n"
> > + " bnez %0, 1f\n"
> > + ZAWRS_WRS_NTO "\n"
> > + "1:"
> > + : "=&r" (tmp), "+A" (*(__ptr32b))
> > + : "r" (__val), "r" (__mask)
> > + : "memory");
> > + break;
> > case 2:
> > - /* RISC-V doesn't have lr instructions on byte and half-word. */
> > - goto no_zawrs;
> > + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> > + __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
> > + __val = val << __s;
> > + __mask = 0xff << __s;
> > +
> > + asm volatile(
> > + " lr.w %0, %1\n"
> > + " and %0, %0, %3\n"
> > + " xor %0, %0, %2\n"
> > + " bnez %0, 1f\n"
> > + ZAWRS_WRS_NTO "\n"
> > + "1:"
> > + : "=&r" (tmp), "+A" (*(__ptr32b))
> > + : "r" (__val), "r" (__mask)
> > + : "memory");
> > + break;
> > case 4:
> > asm volatile(
> > " lr.w %0, %1\n"
> > --
> > 2.40.1
> >
>
> Thanks,
> drew
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-12-16 3:22 [PATCH] riscv: Implement smp_cond_load8/16() with Zawrs guoren
2024-12-16 15:42 ` Andrew Jones
2024-12-17 1:22 ` Guo Ren
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