* [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC
@ 2025-01-02 18:18 Prabhakar
2025-01-02 18:18 ` [PATCH v3 1/6] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling Prabhakar
` (5 more replies)
0 siblings, 6 replies; 25+ messages in thread
From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series fixes MSTOP handling in the RZ/V2H CPG family driver
and add support for clock and reset entries for GIC and SYS, along with
some cleanup.
v2->v3
- Included RB tag from Geert
- Dropped unnecessary parentheses
- Fixed review comments from Geert for patch 4/6
v1->v2
- Updated commit description in patch 1/6
- Updated fixes tag commit header in patch 1/6
- Introduced new patch to support mstop configuration per-bit
instead of group based
Cheers,
Prabhakar
Lad Prabhakar (6):
clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling
clk: renesas: rzv2h: Relocate MSTOP-related macros to the family
driver
clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction
clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r9a09g057: Add clock and reset entries for GIC
drivers/clk/renesas/r9a09g047-cpg.c | 2 +
drivers/clk/renesas/r9a09g057-cpg.c | 7 ++
drivers/clk/renesas/rzv2h-cpg.c | 185 +++++++++++++++-------------
drivers/clk/renesas/rzv2h-cpg.h | 13 +-
4 files changed, 116 insertions(+), 91 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v3 1/6] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-02 18:18 ` [PATCH v3 2/6] clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver Prabhakar ` (4 subsequent siblings) 5 siblings, 0 replies; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Avoid triggering a `refcount_t: addition on 0; use-after-free.` warning when registering a module clock with the same MSTOP configuration. The issue arises when a module clock is registered but not enabled, resulting in a `ref_cnt` of 0. Subsequent calls to `refcount_inc()` on such clocks cause the kernel to warn about use-after-free. [ 0.113529] ------------[ cut here ]------------ [ 0.113537] refcount_t: addition on 0; use-after-free. [ 0.113576] WARNING: CPU: 2 PID: 1 at lib/refcount.c:25 refcount_warn_saturate+0x120/0x144 [ 0.113602] Modules linked in: [ 0.113616] CPU: 2 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.13.0-rc3+ #446 [ 0.113629] Hardware name: Renesas RZ/V2H EVK Board based on r9a09g057h44 (DT) [ 0.113641] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.113652] pc : refcount_warn_saturate+0x120/0x144 [ 0.113664] lr : refcount_warn_saturate+0x120/0x144 [ 0.113675] sp : ffff8000818aba90 [ 0.113682] x29: ffff8000818aba90 x28: ffff0000c0d96450 x27: ffff0000c0d96440 [ 0.113699] x26: 0000000000000014 x25: 0000000000051000 x24: ffff0000c0ad6480 [ 0.113714] x23: ffff0000c0d96200 x22: ffff800080fae558 x21: 00000000000001e0 [ 0.113730] x20: ffff0000c0b11c10 x19: ffff8000815ae6f0 x18: 0000000000000006 [ 0.113745] x17: ffff800081765368 x16: 0000000000000000 x15: 0765076507720766 [ 0.113760] x14: ffff8000816a3ea0 x13: 0765076507720766 x12: 072d077207650774 [ 0.113776] x11: ffff8000816a3ea0 x10: 00000000000000ce x9 : ffff8000816fbea0 [ 0.113791] x8 : 0000000000017fe8 x7 : 00000000fffff000 x6 : ffff8000816fbea0 [ 0.113806] x5 : 80000000fffff000 x4 : 0000000000000000 x3 : 0000000000000000 [ 0.113821] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000c0158000 [ 0.113837] Call trace: [ 0.113845] refcount_warn_saturate+0x120/0x144 (P) [ 0.113859] rzv2h_cpg_probe+0x7f8/0xa38 [ 0.113874] platform_probe+0x68/0xdc [ 0.113890] really_probe+0xbc/0x2c0 [ 0.113901] __driver_probe_device+0x78/0x120 [ 0.113912] driver_probe_device+0x3c/0x154 [ 0.113923] __driver_attach+0x90/0x1a0 [ 0.113933] bus_for_each_dev+0x7c/0xe0 [ 0.113944] driver_attach+0x24/0x30 [ 0.113954] bus_add_driver+0xe4/0x208 [ 0.113965] driver_register+0x68/0x124 [ 0.113975] __platform_driver_probe+0x54/0xd4 [ 0.113987] rzv2h_cpg_init+0x24/0x30 [ 0.113998] do_one_initcall+0x60/0x1d4 [ 0.114013] kernel_init_freeable+0x214/0x278 [ 0.114028] kernel_init+0x20/0x140 [ 0.114041] ret_from_fork+0x10/0x20 [ 0.114052] ---[ end trace 0000000000000000 ]--- Resolve this by checking the `ref_cnt` value before calling `refcount_inc()`. If `ref_cnt` is 0, reset it to 1 using `refcount_set()`. Fixes: 7bd4cb3d6b7c ("clk: renesas: rzv2h: Add MSTOP support") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2->v3 - Included RB tag from Geert v1->v2 - Updated commit description - Updated fixes tag commit header --- drivers/clk/renesas/rzv2h-cpg.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 668a2880b2d3..23c89b0de38a 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -565,8 +565,12 @@ static struct rzv2h_mstop continue; if (BUS_MSTOP(clk->mstop->idx, clk->mstop->mask) == mstop_data) { - if (rzv2h_mod_clock_is_enabled(&clock->hw)) - refcount_inc(&clk->mstop->ref_cnt); + if (rzv2h_mod_clock_is_enabled(&clock->hw)) { + if (refcount_read(&clk->mstop->ref_cnt)) + refcount_inc(&clk->mstop->ref_cnt); + else + refcount_set(&clk->mstop->ref_cnt, 1); + } return clk->mstop; } } -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/6] clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar 2025-01-02 18:18 ` [PATCH v3 1/6] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar ` (3 subsequent siblings) 5 siblings, 0 replies; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> The `CPG_BUS_1_MSTOP` and `CPG_BUS_MSTOP` macros are exclusively used by the RZ/V2H(P) CPG family driver and are not required in the SoC-specific clock driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2->v3 - Included RB tag from Geert v1->v2 - None --- drivers/clk/renesas/rzv2h-cpg.c | 3 +++ drivers/clk/renesas/rzv2h-cpg.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 23c89b0de38a..38edddfc42d9 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -41,6 +41,9 @@ #define GET_RST_OFFSET(x) (0x900 + ((x) * 4)) #define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4)) +#define CPG_BUS_1_MSTOP (0xd00) +#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4) + #define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val))) #define MDIV(val) FIELD_GET(GENMASK(15, 6), (val)) #define PDIV(val) FIELD_GET(GENMASK(5, 0), (val)) diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 9be5a312fa96..810275eba473 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -35,7 +35,6 @@ struct ddiv { #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) -#define CPG_BUS_1_MSTOP (0xd00) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) @@ -47,8 +46,6 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) -#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4) - #define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask)) #define BUS_MSTOP_NONE GENMASK(31, 0) -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar 2025-01-02 18:18 ` [PATCH v3 1/6] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling Prabhakar 2025-01-02 18:18 ` [PATCH v3 2/6] clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-03 2:21 ` kernel test robot ` (2 more replies) 2025-01-02 18:18 ` [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis Prabhakar ` (2 subsequent siblings) 5 siblings, 3 replies; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and `FIELD_GET` macros for better clarity and maintainability. Introduce explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve readability. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2->v3 - Dropped unnecessary parentheses - Included RB tag from Geert v1->v2 - None --- drivers/clk/renesas/rzv2h-cpg.c | 4 ++-- drivers/clk/renesas/rzv2h-cpg.h | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 38edddfc42d9..23fb209d3232 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -582,8 +582,8 @@ static struct rzv2h_mstop if (!mstop) return NULL; - mstop->idx = (mstop_data >> 16) & 0xffff; - mstop->mask = mstop_data & 0xffff; + mstop->idx = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); + mstop->mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); if (rzv2h_mod_clock_is_enabled(&clock->hw)) refcount_set(&mstop->ref_cnt, 1); else diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 810275eba473..f918620c4650 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -46,7 +46,10 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) -#define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask)) +#define BUS_MSTOP_IDX_MASK GENMASK(31, 16) +#define BUS_MSTOP_BITS_MASK GENMASK(15, 0) +#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ + FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) #define BUS_MSTOP_NONE GENMASK(31, 0) /** -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar @ 2025-01-03 2:21 ` kernel test robot 2025-01-03 10:03 ` Lad, Prabhakar 2025-01-03 10:42 ` kernel test robot 2025-01-03 17:07 ` Geert Uytterhoeven 2 siblings, 1 reply; 25+ messages in thread From: kernel test robot @ 2025-01-03 2:21 UTC (permalink / raw) To: Prabhakar, Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: oe-kbuild-all, linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Prabhakar, kernel test robot noticed the following build errors: [auto build test ERROR on geert-renesas-drivers/renesas-clk] [also build test ERROR on next-20241220] [cannot apply to linus/master v6.13-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238 base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction config: sparc-randconfig-002-20250103 (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/config) compiler: sparc-linux-gcc (GCC) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202501030941.vDjx439p-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/clk/renesas/r9a09g057-cpg.c:15: >> drivers/clk/renesas/rzv2h-cpg.h:51:34: error: implicit declaration of function 'FIELD_PREP_CONST' [-Wimplicit-function-declaration] 51 | #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ | ^~~~~~~~~~~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:32: note: in definition of macro 'DEF_MOD_BASE' 137 | .mstop_data = (_mstop), \ | ^~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD' 120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, | ^~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:121:49: note: in expansion of macro 'BUS_MSTOP' 121 | BUS_MSTOP(5, BIT(10))), | ^~~~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD' 120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[1].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD' 120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:122:9: note: in expansion of macro 'DEF_MOD' 122 | DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[2].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:122:9: note: in expansion of macro 'DEF_MOD' 122 | DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:124:9: note: in expansion of macro 'DEF_MOD' 124 | DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[3].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:124:9: note: in expansion of macro 'DEF_MOD' 124 | DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:126:9: note: in expansion of macro 'DEF_MOD' 126 | DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[4].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:126:9: note: in expansion of macro 'DEF_MOD' 126 | DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:128:9: note: in expansion of macro 'DEF_MOD' 128 | DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[5].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:128:9: note: in expansion of macro 'DEF_MOD' 128 | DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:130:9: note: in expansion of macro 'DEF_MOD' 130 | DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[6].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:130:9: note: in expansion of macro 'DEF_MOD' 130 | DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:132:9: note: in expansion of macro 'DEF_MOD' 132 | DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[7].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:132:9: note: in expansion of macro 'DEF_MOD' 132 | DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:134:9: note: in expansion of macro 'DEF_MOD' 134 | DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[8].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:134:9: note: in expansion of macro 'DEF_MOD' 134 | DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:136:9: note: in expansion of macro 'DEF_MOD' 136 | DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[9].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:136:9: note: in expansion of macro 'DEF_MOD' 136 | DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:138:9: note: in expansion of macro 'DEF_MOD' 138 | DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[10].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:138:9: note: in expansion of macro 'DEF_MOD' 138 | DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:140:9: note: in expansion of macro 'DEF_MOD' 140 | DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[11].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:140:9: note: in expansion of macro 'DEF_MOD' 140 | DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:142:9: note: in expansion of macro 'DEF_MOD' 142 | DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[12].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:142:9: note: in expansion of macro 'DEF_MOD' 142 | DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:144:9: note: in expansion of macro 'DEF_MOD' 144 | DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[13].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:144:9: note: in expansion of macro 'DEF_MOD' 144 | DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:146:9: note: in expansion of macro 'DEF_MOD' 146 | DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[14].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:146:9: note: in expansion of macro 'DEF_MOD' 146 | DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:148:9: note: in expansion of macro 'DEF_MOD' 148 | DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[15].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:148:9: note: in expansion of macro 'DEF_MOD' 148 | DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:150:9: note: in expansion of macro 'DEF_MOD' 150 | DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[16].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:150:9: note: in expansion of macro 'DEF_MOD' 150 | DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:152:9: note: in expansion of macro 'DEF_MOD' 152 | DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[17].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:152:9: note: in expansion of macro 'DEF_MOD' 152 | DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:154:9: note: in expansion of macro 'DEF_MOD' 154 | DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[18].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:154:9: note: in expansion of macro 'DEF_MOD' 154 | DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, | ^~~~~~~ >> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:156:9: note: in expansion of macro 'DEF_MOD' 156 | DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[19].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:156:9: note: in expansion of macro 'DEF_MOD' 156 | DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:158:9: note: in expansion of macro 'DEF_MOD' 158 | DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[20].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:158:9: note: in expansion of macro 'DEF_MOD' 158 | DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:160:9: note: in expansion of macro 'DEF_MOD' 160 | DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[21].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:160:9: note: in expansion of macro 'DEF_MOD' 160 | DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:162:9: note: in expansion of macro 'DEF_MOD' 162 | DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[22].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:162:9: note: in expansion of macro 'DEF_MOD' 162 | DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:164:9: note: in expansion of macro 'DEF_MOD' 164 | DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[23].mstop_data') 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:164:9: note: in expansion of macro 'DEF_MOD' 164 | DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant 137 | .mstop_data = (_mstop), \ | ^ drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~ drivers/clk/renesas/r9a09g057-cpg.c:166:9: note: in expansion of macro 'DEF_MOD' 166 | DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, | ^~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[24].mstop_data') 137 | .mstop_data = (_mstop), \ vim +/FIELD_PREP_CONST +51 drivers/clk/renesas/rzv2h-cpg.h 48 49 #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) 50 #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) > 51 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ 52 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) 53 #define BUS_MSTOP_NONE GENMASK(31, 0) 54 55 /** 56 * Definitions of CPG Core Clocks 57 * 58 * These include: 59 * - Clock outputs exported to DT 60 * - External input clocks 61 * - Internal CPG clocks 62 */ 63 struct cpg_core_clk { 64 const char *name; 65 unsigned int id; 66 unsigned int parent; 67 unsigned int div; 68 unsigned int mult; 69 unsigned int type; 70 union { 71 unsigned int conf; 72 struct ddiv ddiv; 73 } cfg; 74 const struct clk_div_table *dtable; 75 u32 flag; 76 }; 77 78 enum clk_types { 79 /* Generic */ 80 CLK_TYPE_IN, /* External Clock Input */ 81 CLK_TYPE_FF, /* Fixed Factor Clock */ 82 CLK_TYPE_PLL, 83 CLK_TYPE_DDIV, /* Dynamic Switching Divider */ 84 }; 85 86 /* BIT(31) indicates if CLK1/2 are accessible or not */ 87 #define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16))) 88 #define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0) 89 #define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16)) 90 #define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4)) 91 92 #define DEF_TYPE(_name, _id, _type...) \ 93 { .name = _name, .id = _id, .type = _type } 94 #define DEF_BASE(_name, _id, _type, _parent...) \ 95 DEF_TYPE(_name, _id, _type, .parent = _parent) 96 #define DEF_PLL(_name, _id, _parent, _conf) \ 97 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf) 98 #define DEF_INPUT(_name, _id) \ 99 DEF_TYPE(_name, _id, CLK_TYPE_IN) 100 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 101 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 102 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 103 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \ 104 .cfg.ddiv = _ddiv_packed, \ 105 .parent = _parent, \ 106 .dtable = _dtable, \ 107 .flag = CLK_DIVIDER_HIWORD_MASK) 108 109 /** 110 * struct rzv2h_mod_clk - Module Clocks definitions 111 * 112 * @name: handle between common and hardware-specific interfaces 113 * @mstop_data: packed data mstop register offset and mask 114 * @parent: id of parent clock 115 * @critical: flag to indicate the clock is critical 116 * @no_pm: flag to indicate PM is not supported 117 * @on_index: control register index 118 * @on_bit: ON bit 119 * @mon_index: monitor register index 120 * @mon_bit: monitor bit 121 */ 122 struct rzv2h_mod_clk { 123 const char *name; 124 u32 mstop_data; 125 u16 parent; 126 bool critical; 127 bool no_pm; 128 u8 on_index; 129 u8 on_bit; 130 s8 mon_index; 131 u8 mon_bit; 132 }; 133 134 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ 135 { \ 136 .name = (_name), \ > 137 .mstop_data = (_mstop), \ 138 .parent = (_parent), \ 139 .critical = (_critical), \ 140 .no_pm = (_no_pm), \ 141 .on_index = (_onindex), \ 142 .on_bit = (_onbit), \ 143 .mon_index = (_monindex), \ 144 .mon_bit = (_monbit), \ 145 } 146 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-03 2:21 ` kernel test robot @ 2025-01-03 10:03 ` Lad, Prabhakar 0 siblings, 0 replies; 25+ messages in thread From: Lad, Prabhakar @ 2025-01-03 10:03 UTC (permalink / raw) To: kernel test robot Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, oe-kbuild-all, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar Hi, On Fri, Jan 3, 2025 at 2:21 AM kernel test robot <lkp@intel.com> wrote: > > Hi Prabhakar, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on geert-renesas-drivers/renesas-clk] > [also build test ERROR on next-20241220] > [cannot apply to linus/master v6.13-rc5] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238 > base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk > patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com > patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction > config: sparc-randconfig-002-20250103 (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/config) > compiler: sparc-linux-gcc (GCC) 14.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202501030941.vDjx439p-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > In file included from drivers/clk/renesas/r9a09g057-cpg.c:15: > >> drivers/clk/renesas/rzv2h-cpg.h:51:34: error: implicit declaration of function 'FIELD_PREP_CONST' [-Wimplicit-function-declaration] > Thank you for the report, I'll include the required header `#include <linux/bitfield.h>` to fix this issue and send a new version. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar 2025-01-03 2:21 ` kernel test robot @ 2025-01-03 10:42 ` kernel test robot 2025-01-03 17:07 ` Geert Uytterhoeven 2 siblings, 0 replies; 25+ messages in thread From: kernel test robot @ 2025-01-03 10:42 UTC (permalink / raw) To: Prabhakar, Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: llvm, oe-kbuild-all, linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Prabhakar, kernel test robot noticed the following build errors: [auto build test ERROR on geert-renesas-drivers/renesas-clk] [also build test ERROR on next-20241220] [cannot apply to linus/master v6.13-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238 base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction config: powerpc64-randconfig-001-20250103 (https://download.01.org/0day-ci/archive/20250103/202501031820.KwL9vVF2-lkp@intel.com/config) compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501031820.KwL9vVF2-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202501031820.KwL9vVF2-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/clk/renesas/r9a09g057-cpg.c:121:7: error: call to undeclared function 'FIELD_PREP_CONST'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 121 | BUS_MSTOP(5, BIT(10))), | ^ drivers/clk/renesas/rzv2h-cpg.h:51:31: note: expanded from macro 'BUS_MSTOP' 51 | #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ | ^ >> drivers/clk/renesas/r9a09g057-cpg.c:120:2: error: initializer element is not a compile-time constant 120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 121 | BUS_MSTOP(5, BIT(10))), | ~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:148:2: note: expanded from macro 'DEF_MOD' 148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/renesas/rzv2h-cpg.h:137:17: note: expanded from macro 'DEF_MOD_BASE' 137 | .mstop_data = (_mstop), \ | ^~~~~~~~ 2 errors generated. vim +/FIELD_PREP_CONST +121 drivers/clk/renesas/r9a09g057-cpg.c 36932cbc3e6cc9 Lad Prabhakar 2024-07-29 116 36932cbc3e6cc9 Lad Prabhakar 2024-07-29 117 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 7bd4cb3d6b7c43 Biju Das 2024-12-13 118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 7bd4cb3d6b7c43 Biju Das 2024-12-13 119 BUS_MSTOP_NONE), 7bd4cb3d6b7c43 Biju Das 2024-12-13 @120 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 7bd4cb3d6b7c43 Biju Das 2024-12-13 @121 BUS_MSTOP(5, BIT(10))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 122 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 7bd4cb3d6b7c43 Biju Das 2024-12-13 123 BUS_MSTOP(5, BIT(11))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 124 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 7bd4cb3d6b7c43 Biju Das 2024-12-13 125 BUS_MSTOP(2, BIT(13))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 126 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 7bd4cb3d6b7c43 Biju Das 2024-12-13 127 BUS_MSTOP(2, BIT(14))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 128 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 7bd4cb3d6b7c43 Biju Das 2024-12-13 129 BUS_MSTOP(11, BIT(13))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 130 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 7bd4cb3d6b7c43 Biju Das 2024-12-13 131 BUS_MSTOP(11, BIT(14))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 132 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 7bd4cb3d6b7c43 Biju Das 2024-12-13 133 BUS_MSTOP(11, BIT(15))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 134 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 7bd4cb3d6b7c43 Biju Das 2024-12-13 135 BUS_MSTOP(12, BIT(0))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 136 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 7bd4cb3d6b7c43 Biju Das 2024-12-13 137 BUS_MSTOP(3, BIT(10))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 138 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 7bd4cb3d6b7c43 Biju Das 2024-12-13 139 BUS_MSTOP(3, BIT(10))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 140 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 7bd4cb3d6b7c43 Biju Das 2024-12-13 141 BUS_MSTOP(1, BIT(0))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 142 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 7bd4cb3d6b7c43 Biju Das 2024-12-13 143 BUS_MSTOP(1, BIT(0))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 144 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 7bd4cb3d6b7c43 Biju Das 2024-12-13 145 BUS_MSTOP(5, BIT(12))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 146 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 7bd4cb3d6b7c43 Biju Das 2024-12-13 147 BUS_MSTOP(5, BIT(12))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 148 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 7bd4cb3d6b7c43 Biju Das 2024-12-13 149 BUS_MSTOP(5, BIT(13))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 150 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 7bd4cb3d6b7c43 Biju Das 2024-12-13 151 BUS_MSTOP(5, BIT(13))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 152 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 7bd4cb3d6b7c43 Biju Das 2024-12-13 153 BUS_MSTOP(3, BIT(14))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 154 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 7bd4cb3d6b7c43 Biju Das 2024-12-13 155 BUS_MSTOP(3, BIT(13))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 156 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 7bd4cb3d6b7c43 Biju Das 2024-12-13 157 BUS_MSTOP(1, BIT(1))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 158 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 7bd4cb3d6b7c43 Biju Das 2024-12-13 159 BUS_MSTOP(1, BIT(2))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 160 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 7bd4cb3d6b7c43 Biju Das 2024-12-13 161 BUS_MSTOP(1, BIT(3))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 162 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 7bd4cb3d6b7c43 Biju Das 2024-12-13 163 BUS_MSTOP(1, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 164 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 7bd4cb3d6b7c43 Biju Das 2024-12-13 165 BUS_MSTOP(1, BIT(5))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 166 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 7bd4cb3d6b7c43 Biju Das 2024-12-13 167 BUS_MSTOP(1, BIT(6))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 168 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 7bd4cb3d6b7c43 Biju Das 2024-12-13 169 BUS_MSTOP(1, BIT(7))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 170 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 7bd4cb3d6b7c43 Biju Das 2024-12-13 171 BUS_MSTOP(1, BIT(8))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 172 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 7bd4cb3d6b7c43 Biju Das 2024-12-13 173 BUS_MSTOP(8, BIT(2))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 174 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 7bd4cb3d6b7c43 Biju Das 2024-12-13 175 BUS_MSTOP(8, BIT(2))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 176 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 7bd4cb3d6b7c43 Biju Das 2024-12-13 177 BUS_MSTOP(8, BIT(2))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 178 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 7bd4cb3d6b7c43 Biju Das 2024-12-13 179 BUS_MSTOP(8, BIT(2))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 180 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 7bd4cb3d6b7c43 Biju Das 2024-12-13 181 BUS_MSTOP(8, BIT(3))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 182 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 7bd4cb3d6b7c43 Biju Das 2024-12-13 183 BUS_MSTOP(8, BIT(3))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 184 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 7bd4cb3d6b7c43 Biju Das 2024-12-13 185 BUS_MSTOP(8, BIT(3))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 186 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 7bd4cb3d6b7c43 Biju Das 2024-12-13 187 BUS_MSTOP(8, BIT(3))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 188 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 7bd4cb3d6b7c43 Biju Das 2024-12-13 189 BUS_MSTOP(8, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 190 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 7bd4cb3d6b7c43 Biju Das 2024-12-13 191 BUS_MSTOP(8, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 192 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 7bd4cb3d6b7c43 Biju Das 2024-12-13 193 BUS_MSTOP(8, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 194 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 7bd4cb3d6b7c43 Biju Das 2024-12-13 195 BUS_MSTOP(8, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 196 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 7bd4cb3d6b7c43 Biju Das 2024-12-13 197 BUS_MSTOP(9, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 198 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 7bd4cb3d6b7c43 Biju Das 2024-12-13 199 BUS_MSTOP(9, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 200 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 7bd4cb3d6b7c43 Biju Das 2024-12-13 201 BUS_MSTOP(9, BIT(4))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 202 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 7bd4cb3d6b7c43 Biju Das 2024-12-13 203 BUS_MSTOP(9, BIT(5))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 204 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 7bd4cb3d6b7c43 Biju Das 2024-12-13 205 BUS_MSTOP(9, BIT(5))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 206 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 7bd4cb3d6b7c43 Biju Das 2024-12-13 207 BUS_MSTOP(9, BIT(5))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 208 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, 7bd4cb3d6b7c43 Biju Das 2024-12-13 209 BUS_MSTOP(9, BIT(6))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 210 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, 7bd4cb3d6b7c43 Biju Das 2024-12-13 211 BUS_MSTOP(9, BIT(6))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 212 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, 7bd4cb3d6b7c43 Biju Das 2024-12-13 213 BUS_MSTOP(9, BIT(6))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 214 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, 7bd4cb3d6b7c43 Biju Das 2024-12-13 215 BUS_MSTOP(9, BIT(7))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 216 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, 7bd4cb3d6b7c43 Biju Das 2024-12-13 217 BUS_MSTOP(9, BIT(7))), 7bd4cb3d6b7c43 Biju Das 2024-12-13 218 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, 7bd4cb3d6b7c43 Biju Das 2024-12-13 219 BUS_MSTOP(9, BIT(7))), 36932cbc3e6cc9 Lad Prabhakar 2024-07-29 220 }; 36932cbc3e6cc9 Lad Prabhakar 2024-07-29 221 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar 2025-01-03 2:21 ` kernel test robot 2025-01-03 10:42 ` kernel test robot @ 2025-01-03 17:07 ` Geert Uytterhoeven 2025-01-04 8:16 ` Lad, Prabhakar 2 siblings, 1 reply; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-03 17:07 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and > `FIELD_GET` macros for better clarity and maintainability. Introduce > explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve > readability. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2->v3 > - Dropped unnecessary parentheses > - Included RB tag from Geert Thanks, will queue in renesas-clk for v6.14, with --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -8,6 +8,8 @@ #ifndef __RENESAS_RZV2H_CPG_H__ #define __RENESAS_RZV2H_CPG_H__ +#include <linux/bitfield.h> + /** * struct ddiv - Structure for dynamic switching divider * Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction 2025-01-03 17:07 ` Geert Uytterhoeven @ 2025-01-04 8:16 ` Lad, Prabhakar 0 siblings, 0 replies; 25+ messages in thread From: Lad, Prabhakar @ 2025-01-04 8:16 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Geert, On Fri, Jan 3, 2025 at 5:08 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and > > `FIELD_GET` macros for better clarity and maintainability. Introduce > > explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve > > readability. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > v2->v3 > > - Dropped unnecessary parentheses > > - Included RB tag from Geert > > Thanks, will queue in renesas-clk for v6.14, with > > --- a/drivers/clk/renesas/rzv2h-cpg.h > +++ b/drivers/clk/renesas/rzv2h-cpg.h > @@ -8,6 +8,8 @@ > #ifndef __RENESAS_RZV2H_CPG_H__ > #define __RENESAS_RZV2H_CPG_H__ > > +#include <linux/bitfield.h> > + > /** > * struct ddiv - Structure for dynamic switching divider > * > Thanks for taking care of this. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar ` (2 preceding siblings ...) 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-03 17:06 ` Geert Uytterhoeven 2025-01-07 11:24 ` Biju Das 2025-01-02 18:18 ` [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS Prabhakar 2025-01-02 18:18 ` [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC Prabhakar 5 siblings, 2 replies; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Switch MSTOP handling from group-based to per-bit configuration to address issues with shared dependencies between module clocks. In the current group-based configuration, multiple module clocks may rely on a single MSTOP bit. When both clocks are turned ON and one is subsequently turned OFF, the shared MSTOP bit will still be set, which is incorrect since the other dependent module clock remains ON. By switching to a per-bit configuration, we ensure precise control over individual MSTOP bits, preventing such conflicts. Replace the refcount API with atomic operations for managing MSTOP bit counters. The refcount API requires explicitly setting the counter to `1` before calling `refcount_inc()`, which introduces potential edge cases and unnecessary complexity. Using atomic operations simplifies the logic and avoids such issues, resulting in cleaner and more maintainable code. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v2->v3 - Dropped unnecessary parentheses - Switched using to devm_kcalloc() instead of devm_kmalloc_array() - Optimized check in rzv2h_mod_clock_endisable() if the states are same - Dropped GET_MSTOP_IDX() macro and handled indexing in the code - Made mstop_mask to unsigned long to avoid casting v1->v2 - None --- drivers/clk/renesas/r9a09g047-cpg.c | 2 + drivers/clk/renesas/r9a09g057-cpg.c | 2 + drivers/clk/renesas/rzv2h-cpg.c | 186 ++++++++++++++-------------- drivers/clk/renesas/rzv2h-cpg.h | 5 + 4 files changed, 104 insertions(+), 91 deletions(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 7945b9f95b95..536d922bed70 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -145,4 +145,6 @@ const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { /* Resets */ .resets = r9a09g047_resets, .num_resets = ARRAY_SIZE(r9a09g047_resets), + + .num_mstop_bits = 208, }; diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 59dadedb2217..a45b4020996b 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -275,4 +275,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { /* Resets */ .resets = r9a09g057_resets, .num_resets = ARRAY_SIZE(r9a09g057_resets), + + .num_mstop_bits = 192, }; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 23fb209d3232..a4c1e92e1fd7 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -68,6 +68,7 @@ * @resets: Array of resets * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @mstop_count: Array of mstop values * @rcdev: Reset controller entity */ struct rzv2h_cpg_priv { @@ -82,17 +83,13 @@ struct rzv2h_cpg_priv { unsigned int num_resets; unsigned int last_dt_core_clk; + atomic_t *mstop_count; + struct reset_controller_dev rcdev; }; #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) -struct rzv2h_mstop { - u16 idx; - u16 mask; - refcount_t ref_cnt; -}; - struct pll_clk { struct rzv2h_cpg_priv *priv; void __iomem *base; @@ -107,7 +104,7 @@ struct pll_clk { * struct mod_clock - Module clock * * @priv: CPG private data - * @mstop: handle to cpg bus mstop data + * @mstop_data: mstop data relating to module clock * @hw: handle between common and hardware-specific interfaces * @no_pm: flag to indicate PM is not supported * @on_index: register offset @@ -117,7 +114,7 @@ struct pll_clk { */ struct mod_clock { struct rzv2h_cpg_priv *priv; - struct rzv2h_mstop *mstop; + unsigned int mstop_data; struct clk_hw hw; bool no_pm; u8 on_index; @@ -446,38 +443,70 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, } static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, - struct mod_clock *clock) + u32 mstop_data) { + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); + unsigned int index = (mstop_index - 1) * 16; + atomic_t *mstop = &priv->mstop_count[index]; unsigned long flags; - u32 val; + unsigned int i; + u32 val = 0; spin_lock_irqsave(&priv->rmw_lock, flags); - if (!refcount_read(&clock->mstop->ref_cnt)) { - val = clock->mstop->mask << 16; - writel(val, priv->base + CPG_BUS_MSTOP(clock->mstop->idx)); - refcount_set(&clock->mstop->ref_cnt, 1); - } else { - refcount_inc(&clock->mstop->ref_cnt); + for_each_set_bit(i, &mstop_mask, 16) { + if (!atomic_read(&mstop[i])) + val |= BIT(i) << 16; + atomic_inc(&mstop[i]); } + if (val) + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); spin_unlock_irqrestore(&priv->rmw_lock, flags); } static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, - struct mod_clock *clock) + u32 mstop_data) { + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); + unsigned int index = (mstop_index - 1) * 16; + atomic_t *mstop = &priv->mstop_count[index]; unsigned long flags; - u32 val; + unsigned int i; + u32 val = 0; spin_lock_irqsave(&priv->rmw_lock, flags); - if (refcount_dec_and_test(&clock->mstop->ref_cnt)) { - val = clock->mstop->mask << 16 | clock->mstop->mask; - writel(val, priv->base + CPG_BUS_MSTOP(clock->mstop->idx)); + for_each_set_bit(i, &mstop_mask, 16) { + if (!atomic_read(&mstop[i]) || + atomic_dec_and_test(&mstop[i])) + val |= BIT(i) << 16 | BIT(i); } + if (val) + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); spin_unlock_irqrestore(&priv->rmw_lock, flags); } +static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) +{ + struct mod_clock *clock = to_mod_clock(hw); + struct rzv2h_cpg_priv *priv = clock->priv; + u32 bitmask; + u32 offset; + + if (clock->mon_index >= 0) { + offset = GET_CLK_MON_OFFSET(clock->mon_index); + bitmask = BIT(clock->mon_bit); + } else { + offset = GET_CLK_ON_OFFSET(clock->on_index); + bitmask = BIT(clock->on_bit); + } + + return readl(priv->base + offset) & bitmask; +} + static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) { + bool enabled = rzv2h_mod_clock_is_enabled(hw); struct mod_clock *clock = to_mod_clock(hw); unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index); struct rzv2h_cpg_priv *priv = clock->priv; @@ -489,15 +518,18 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk, enable ? "ON" : "OFF"); + if (enabled == enable) + return 0; + value = bitmask << 16; if (enable) { value |= bitmask; writel(value, priv->base + reg); - if (clock->mstop) - rzv2h_mod_clock_mstop_enable(priv, clock); + if (clock->mstop_data != BUS_MSTOP_NONE) + rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); } else { - if (clock->mstop) - rzv2h_mod_clock_mstop_disable(priv, clock); + if (clock->mstop_data != BUS_MSTOP_NONE) + rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data); writel(value, priv->base + reg); } @@ -525,73 +557,12 @@ static void rzv2h_mod_clock_disable(struct clk_hw *hw) rzv2h_mod_clock_endisable(hw, false); } -static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) -{ - struct mod_clock *clock = to_mod_clock(hw); - struct rzv2h_cpg_priv *priv = clock->priv; - u32 bitmask; - u32 offset; - - if (clock->mon_index >= 0) { - offset = GET_CLK_MON_OFFSET(clock->mon_index); - bitmask = BIT(clock->mon_bit); - } else { - offset = GET_CLK_ON_OFFSET(clock->on_index); - bitmask = BIT(clock->on_bit); - } - - return readl(priv->base + offset) & bitmask; -} - static const struct clk_ops rzv2h_mod_clock_ops = { .enable = rzv2h_mod_clock_enable, .disable = rzv2h_mod_clock_disable, .is_enabled = rzv2h_mod_clock_is_enabled, }; -static struct rzv2h_mstop -*rzv2h_cpg_get_mstop(struct rzv2h_cpg_priv *priv, struct mod_clock *clock, u32 mstop_data) -{ - struct rzv2h_mstop *mstop; - unsigned int i; - - for (i = 0; i < priv->num_mod_clks; i++) { - struct mod_clock *clk; - struct clk_hw *hw; - - if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT)) - continue; - - hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]); - clk = to_mod_clock(hw); - if (!clk->mstop) - continue; - - if (BUS_MSTOP(clk->mstop->idx, clk->mstop->mask) == mstop_data) { - if (rzv2h_mod_clock_is_enabled(&clock->hw)) { - if (refcount_read(&clk->mstop->ref_cnt)) - refcount_inc(&clk->mstop->ref_cnt); - else - refcount_set(&clk->mstop->ref_cnt, 1); - } - return clk->mstop; - } - } - - mstop = devm_kzalloc(priv->dev, sizeof(*mstop), GFP_KERNEL); - if (!mstop) - return NULL; - - mstop->idx = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); - mstop->mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); - if (rzv2h_mod_clock_is_enabled(&clock->hw)) - refcount_set(&mstop->ref_cnt, 1); - else - refcount_set(&mstop->ref_cnt, 0); - - return mstop; -} - static void __init rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, struct rzv2h_cpg_priv *priv) @@ -638,6 +609,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, clock->no_pm = mod->no_pm; clock->priv = priv; clock->hw.init = &init; + clock->mstop_data = mod->mstop_data; ret = devm_clk_hw_register(dev, &clock->hw); if (ret) { @@ -647,12 +619,39 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, priv->clks[id] = clock->hw.clk; - if (mod->mstop_data != BUS_MSTOP_NONE) { - clock->mstop = rzv2h_cpg_get_mstop(priv, clock, mod->mstop_data); - if (!clock->mstop) { - clk = ERR_PTR(-ENOMEM); - goto fail; + /* + * Ensure the module clocks and MSTOP bits are synchronized when they are + * turned ON by the bootloader. Enable MSTOP bits for module clocks that were + * turned ON in an earlier boot stage. + */ + if (clock->mstop_data != BUS_MSTOP_NONE && + !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) { + rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); + } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) { + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data); + unsigned int index = (mstop_index - 1) * 16; + atomic_t *mstop = &priv->mstop_count[index]; + unsigned long flags; + unsigned int i; + u32 val = 0; + + /* + * Critical clocks are turned ON immediately upon registration, and the + * MSTOP counter is updated through the rzv2h_mod_clock_enable() path. + * However, if the critical clocks were already turned ON by the initial + * bootloader, synchronize the atomic counter here and clear the MSTOP bit. + */ + spin_lock_irqsave(&priv->rmw_lock, flags); + for_each_set_bit(i, &mstop_mask, 16) { + if (atomic_read(&mstop[i])) + continue; + val |= BIT(i) << 16; + atomic_inc(&mstop[i]); } + if (val) + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); + spin_unlock_irqrestore(&priv->rmw_lock, flags); } return; @@ -922,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) if (!clks) return -ENOMEM; + priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits, + sizeof(*priv->mstop_count), GFP_KERNEL); + if (!priv->mstop_count) + return -ENOMEM; + priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) * info->num_resets, GFP_KERNEL); if (!priv->resets) diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index f918620c4650..a772304f9057 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -193,6 +193,9 @@ struct rzv2h_reset { * * @resets: Array of Module Reset definitions * @num_resets: Number of entries in resets[] + * + * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the + * number of CPG_BUS_m_MSTOP registers multiplied by 16. */ struct rzv2h_cpg_info { /* Core Clocks */ @@ -209,6 +212,8 @@ struct rzv2h_cpg_info { /* Resets */ const struct rzv2h_reset *resets; unsigned int num_resets; + + unsigned int num_mstop_bits; }; extern const struct rzv2h_cpg_info r9a09g047_cpg_info; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-02 18:18 ` [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis Prabhakar @ 2025-01-03 17:06 ` Geert Uytterhoeven 2025-01-07 11:24 ` Biju Das 1 sibling, 0 replies; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-03 17:06 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Prabhakar, On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Switch MSTOP handling from group-based to per-bit configuration to > address issues with shared dependencies between module clocks. In the > current group-based configuration, multiple module clocks may rely on > a single MSTOP bit. When both clocks are turned ON and one is > subsequently turned OFF, the shared MSTOP bit will still be set, which > is incorrect since the other dependent module clock remains ON. By > switching to a per-bit configuration, we ensure precise control over > individual MSTOP bits, preventing such conflicts. > > Replace the refcount API with atomic operations for managing MSTOP bit > counters. The refcount API requires explicitly setting the counter to > `1` before calling `refcount_inc()`, which introduces potential edge > cases and unnecessary complexity. Using atomic operations simplifies > the logic and avoids such issues, resulting in cleaner and more > maintainable code. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v2->v3 > - Dropped unnecessary parentheses > - Switched using to devm_kcalloc() instead of devm_kmalloc_array() > - Optimized check in rzv2h_mod_clock_endisable() if the states are same > - Dropped GET_MSTOP_IDX() macro and handled indexing in the code > - Made mstop_mask to unsigned long to avoid casting Thanks for the update! > --- a/drivers/clk/renesas/rzv2h-cpg.c > +++ b/drivers/clk/renesas/rzv2h-cpg.c > @@ -446,38 +443,70 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, > } > > static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, > - struct mod_clock *clock) > + u32 mstop_data) > { > + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); > + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); > + unsigned int index = (mstop_index - 1) * 16; Probably I didn't explain it well, but you could avoid the "- 1" here and in all functions accessing priv->mstop_count, by adjusting priv->mstop_count in rzv2h_cpg_probe()[1]. > + atomic_t *mstop = &priv->mstop_count[index]; > unsigned long flags; > - u32 val; > + unsigned int i; > + u32 val = 0; > > spin_lock_irqsave(&priv->rmw_lock, flags); > - if (!refcount_read(&clock->mstop->ref_cnt)) { > - val = clock->mstop->mask << 16; > - writel(val, priv->base + CPG_BUS_MSTOP(clock->mstop->idx)); > - refcount_set(&clock->mstop->ref_cnt, 1); > - } else { > - refcount_inc(&clock->mstop->ref_cnt); > + for_each_set_bit(i, &mstop_mask, 16) { > + if (!atomic_read(&mstop[i])) > + val |= BIT(i) << 16; > + atomic_inc(&mstop[i]); > } > + if (val) > + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); > spin_unlock_irqrestore(&priv->rmw_lock, flags); > } > @@ -647,12 +619,39 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, > > priv->clks[id] = clock->hw.clk; > > - if (mod->mstop_data != BUS_MSTOP_NONE) { > - clock->mstop = rzv2h_cpg_get_mstop(priv, clock, mod->mstop_data); > - if (!clock->mstop) { > - clk = ERR_PTR(-ENOMEM); > - goto fail; > + /* > + * Ensure the module clocks and MSTOP bits are synchronized when they are > + * turned ON by the bootloader. Enable MSTOP bits for module clocks that were > + * turned ON in an earlier boot stage. > + */ > + if (clock->mstop_data != BUS_MSTOP_NONE && > + !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) { > + rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); > + } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) { > + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); > + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data); > + unsigned int index = (mstop_index - 1) * 16; > + atomic_t *mstop = &priv->mstop_count[index]; > + unsigned long flags; > + unsigned int i; > + u32 val = 0; > + > + /* > + * Critical clocks are turned ON immediately upon registration, and the > + * MSTOP counter is updated through the rzv2h_mod_clock_enable() path. > + * However, if the critical clocks were already turned ON by the initial > + * bootloader, synchronize the atomic counter here and clear the MSTOP bit. > + */ > + spin_lock_irqsave(&priv->rmw_lock, flags); > + for_each_set_bit(i, &mstop_mask, 16) { > + if (atomic_read(&mstop[i])) > + continue; > + val |= BIT(i) << 16; > + atomic_inc(&mstop[i]); > } > + if (val) > + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); > + spin_unlock_irqrestore(&priv->rmw_lock, flags); > } This logic could be simplified to: if (clock->mstop_data == BUS_MSTOP_NONE) return; if (mod->critical) { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); ... } else if (rzv2h_mod_clock_is_enabled(&clock->hw)) { rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); } > > return; > @@ -922,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) > if (!clks) > return -ENOMEM; > > + priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits, > + sizeof(*priv->mstop_count), GFP_KERNEL); > + if (!priv->mstop_count) > + return -ENOMEM; [1] /* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */ priv->mstop_count -= 16; Anyway, it's getting late in the cycle, so I am queuing this tentatively in renesas-clk for v6.14, to allow the bots to give it a run in this Monday's linux-next. I will still have to squash the fixes (+ whatever minor updates?) into the original bad commit (adding Co-Developed-by-tags for you and Biju), but that can be done later, just before sending my final pull requests for the v6.14 merge window... Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-02 18:18 ` [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis Prabhakar 2025-01-03 17:06 ` Geert Uytterhoeven @ 2025-01-07 11:24 ` Biju Das 2025-01-07 11:45 ` Lad, Prabhakar 1 sibling, 1 reply; 25+ messages in thread From: Biju Das @ 2025-01-07 11:24 UTC (permalink / raw) To: Prabhakar, Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar <prabhakar.csengg@gmail.com> > Sent: 02 January 2025 18:19 > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Switch MSTOP handling from group-based to per-bit configuration to address issues with shared > dependencies between module clocks. In the current group-based configuration, multiple module clocks > may rely on a single MSTOP bit. When both clocks are turned ON and one is subsequently turned OFF, the > shared MSTOP bit will still be set, which is incorrect since the other dependent module clock remains > ON. I guess this statement is incorrect. Still in group-based, mstop bit is controlled by usage count(ref_cnt). The real advantage with per-bit configuration is, we can drop index manipulation. Cheers, Biju ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 11:24 ` Biju Das @ 2025-01-07 11:45 ` Lad, Prabhakar 2025-01-07 12:25 ` Biju Das 0 siblings, 1 reply; 25+ messages in thread From: Lad, Prabhakar @ 2025-01-07 11:45 UTC (permalink / raw) To: Biju Das Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Biju, On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -----Original Message----- > > From: Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 02 January 2025 18:19 > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Switch MSTOP handling from group-based to per-bit configuration to address issues with shared > > dependencies between module clocks. In the current group-based configuration, multiple module clocks > > may rely on a single MSTOP bit. When both clocks are turned ON and one is subsequently turned OFF, the > > shared MSTOP bit will still be set, which is incorrect since the other dependent module clock remains > > ON. > > I guess this statement is incorrect. Still in group-based, mstop bit is controlled by usage count(ref_cnt). > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 | 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same MSTOP register say MSTOP1). Now this will be seperate groups having separate count(ref_cnt). Say you turn ON IP-A module clock and correspondingly clear the MSTOP bits and similarly now lets turn ON module clocks for IP-B and clear the MSTOP bits. Now let's say you want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block. This case is handled by switching refcount on per mstop bit by this patch. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 11:45 ` Lad, Prabhakar @ 2025-01-07 12:25 ` Biju Das 2025-01-07 12:31 ` Lad, Prabhakar 0 siblings, 1 reply; 25+ messages in thread From: Biju Das @ 2025-01-07 12:25 UTC (permalink / raw) To: Lad, Prabhakar Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: 07 January 2025 11:46 > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > Hi Biju, > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > Thanks for the patch. > > > > > -----Original Message----- > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: 02 January 2025 18:19 > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > configuration to per-bit basis > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Switch MSTOP handling from group-based to per-bit configuration to > > > address issues with shared dependencies between module clocks. In > > > the current group-based configuration, multiple module clocks may > > > rely on a single MSTOP bit. When both clocks are turned ON and one > > > is subsequently turned OFF, the shared MSTOP bit will still be set, which is incorrect since the > other dependent module clock remains ON. > > > > I guess this statement is incorrect. Still in group-based, mstop bit is controlled by usage > count(ref_cnt). > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 | > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same MSTOP register say MSTOP1). Now > this will be seperate groups having separate count(ref_cnt). Say you turn ON IP-A module clock and > correspondingly clear the MSTOP bits and similarly now lets turn ON module clocks for IP-B and clear > the MSTOP bits. Now let's say you want to turn OFF IP-A so you turn OFF module clock and set the MSTOP > bits 8 | 9 | 10. In this case you will now see issues with IP-B as MSTOP BIT(10) has been set when we > turned OFF IP-A block. This case is handled by switching refcount on per mstop bit by this patch. I agree, Do we have such use case? Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, bit 0 | index1 10 is addressed in current patch series? Cheers, Biju ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:25 ` Biju Das @ 2025-01-07 12:31 ` Lad, Prabhakar 2025-01-07 12:38 ` Biju Das 0 siblings, 1 reply; 25+ messages in thread From: Lad, Prabhakar @ 2025-01-07 12:31 UTC (permalink / raw) To: Biju Das Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Biju, On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > > -----Original Message----- > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 07 January 2025 11:46 > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > > > Hi Biju, > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > Hi Prabhakar, > > > > > > Thanks for the patch. > > > > > > > -----Original Message----- > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > Sent: 02 January 2025 18:19 > > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > configuration to per-bit basis > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Switch MSTOP handling from group-based to per-bit configuration to > > > > address issues with shared dependencies between module clocks. In > > > > the current group-based configuration, multiple module clocks may > > > > rely on a single MSTOP bit. When both clocks are turned ON and one > > > > is subsequently turned OFF, the shared MSTOP bit will still be set, which is incorrect since the > > other dependent module clock remains ON. > > > > > > I guess this statement is incorrect. Still in group-based, mstop bit is controlled by usage > > count(ref_cnt). > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 | > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same MSTOP register say MSTOP1). Now > > this will be seperate groups having separate count(ref_cnt). Say you turn ON IP-A module clock and > > correspondingly clear the MSTOP bits and similarly now lets turn ON module clocks for IP-B and clear > > the MSTOP bits. Now let's say you want to turn OFF IP-A so you turn OFF module clock and set the MSTOP > > bits 8 | 9 | 10. In this case you will now see issues with IP-B as MSTOP BIT(10) has been set when we > > turned OFF IP-A block. This case is handled by switching refcount on per mstop bit by this patch. > > I agree, Do we have such use case? > Yes, for USB2.0 on RZ/V2H. > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, bit 0 | index1 10 is addressed in current patch series? > Can you please elaborate, the above isn't clear to me. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:31 ` Lad, Prabhakar @ 2025-01-07 12:38 ` Biju Das 2025-01-07 12:44 ` Lad, Prabhakar 2025-01-07 12:49 ` Geert Uytterhoeven 0 siblings, 2 replies; 25+ messages in thread From: Biju Das @ 2025-01-07 12:38 UTC (permalink / raw) To: Lad, Prabhakar Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: 07 January 2025 12:31 > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > Hi Biju, > > On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > > -----Original Message----- > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: 07 January 2025 11:46 > > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > configuration to per-bit basis > > > > > > Hi Biju, > > > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > Hi Prabhakar, > > > > > > > > Thanks for the patch. > > > > > > > > > -----Original Message----- > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > Sent: 02 January 2025 18:19 > > > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > > configuration to per-bit basis > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Switch MSTOP handling from group-based to per-bit configuration > > > > > to address issues with shared dependencies between module > > > > > clocks. In the current group-based configuration, multiple > > > > > module clocks may rely on a single MSTOP bit. When both clocks > > > > > are turned ON and one is subsequently turned OFF, the shared > > > > > MSTOP bit will still be set, which is incorrect since the > > > other dependent module clock remains ON. > > > > > > > > I guess this statement is incorrect. Still in group-based, mstop > > > > bit is controlled by usage > > > count(ref_cnt). > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 > > > | > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same > > > MSTOP register say MSTOP1). Now this will be seperate groups having > > > separate count(ref_cnt). Say you turn ON IP-A module clock and > > > correspondingly clear the MSTOP bits and similarly now lets turn ON > > > module clocks for IP-B and clear the MSTOP bits. Now let's say you > > > want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block. This > case is handled by switching refcount on per mstop bit by this patch. > > > > I agree, Do we have such use case? > > > Yes, for USB2.0 on RZ/V2H. OK, then it make sense for per-bit configuration. > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, > bit 0 | index1 10 is addressed in current patch series? > > > Can you please elaborate, the above isn't clear to me. I just provide a random example for a future IP, where IP_A requires mstop1 {8,9,10} And IP_B requires mstop1 {8} and mstop2 {9, 10} Note: I haven't seen this scenario in hardware manual. Cheers, Biju ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:38 ` Biju Das @ 2025-01-07 12:44 ` Lad, Prabhakar 2025-01-07 12:50 ` Biju Das 2025-01-07 12:51 ` Geert Uytterhoeven 2025-01-07 12:49 ` Geert Uytterhoeven 1 sibling, 2 replies; 25+ messages in thread From: Lad, Prabhakar @ 2025-01-07 12:44 UTC (permalink / raw) To: Biju Das Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Biju, On Tue, Jan 7, 2025 at 12:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > > -----Original Message----- > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 07 January 2025 12:31 > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > > > Hi Biju, > > > > On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > Hi Prabhakar, > > > > > > > -----Original Message----- > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > > Sent: 07 January 2025 11:46 > > > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > configuration to per-bit basis > > > > > > > > Hi Biju, > > > > > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > > Hi Prabhakar, > > > > > > > > > > Thanks for the patch. > > > > > > > > > > > -----Original Message----- > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > Sent: 02 January 2025 18:19 > > > > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > > > configuration to per-bit basis > > > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Switch MSTOP handling from group-based to per-bit configuration > > > > > > to address issues with shared dependencies between module > > > > > > clocks. In the current group-based configuration, multiple > > > > > > module clocks may rely on a single MSTOP bit. When both clocks > > > > > > are turned ON and one is subsequently turned OFF, the shared > > > > > > MSTOP bit will still be set, which is incorrect since the > > > > other dependent module clock remains ON. > > > > > > > > > > I guess this statement is incorrect. Still in group-based, mstop > > > > > bit is controlled by usage > > > > count(ref_cnt). > > > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 > > > > | > > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same > > > > MSTOP register say MSTOP1). Now this will be seperate groups having > > > > separate count(ref_cnt). Say you turn ON IP-A module clock and > > > > correspondingly clear the MSTOP bits and similarly now lets turn ON > > > > module clocks for IP-B and clear the MSTOP bits. Now let's say you > > > > want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > > you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block. This > > case is handled by switching refcount on per mstop bit by this patch. > > > > > > I agree, Do we have such use case? > > > > > Yes, for USB2.0 on RZ/V2H. > > OK, then it make sense for per-bit configuration. > > > > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, > > bit 0 | index1 10 is addressed in current patch series? > > > > > Can you please elaborate, the above isn't clear to me. > > > I just provide a random example for a future IP, where > > IP_A requires mstop1 {8,9,10} > And > IP_B requires mstop1 {8} and mstop2 {9, 10} > No, this case is not handled by the patch series. > Note: I haven't seen this scenario in hardware manual. > Yes, neither do I. For this case we will have to re-work the BUS_MSTOP() macro. Let me know if we want this case to be handled. I'll create a new patch on top of this series. Cheers. Prabhakar ^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:44 ` Lad, Prabhakar @ 2025-01-07 12:50 ` Biju Das 2025-01-07 12:51 ` Geert Uytterhoeven 1 sibling, 0 replies; 25+ messages in thread From: Biju Das @ 2025-01-07 12:50 UTC (permalink / raw) To: Lad, Prabhakar Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: 07 January 2025 12:44 > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > Hi Biju, > > On Tue, Jan 7, 2025 at 12:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > > -----Original Message----- > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: 07 January 2025 12:31 > > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > configuration to per-bit basis > > > > > > Hi Biju, > > > > > > On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > Hi Prabhakar, > > > > > > > > > -----Original Message----- > > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > > > Sent: 07 January 2025 11:46 > > > > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > > configuration to per-bit basis > > > > > > > > > > Hi Biju, > > > > > > > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > > > > Hi Prabhakar, > > > > > > > > > > > > Thanks for the patch. > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > Sent: 02 January 2025 18:19 > > > > > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP > > > > > > > configuration to per-bit basis > > > > > > > > > > > > > > From: Lad Prabhakar > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > Switch MSTOP handling from group-based to per-bit > > > > > > > configuration to address issues with shared dependencies > > > > > > > between module clocks. In the current group-based > > > > > > > configuration, multiple module clocks may rely on a single > > > > > > > MSTOP bit. When both clocks are turned ON and one is > > > > > > > subsequently turned OFF, the shared MSTOP bit will still be > > > > > > > set, which is incorrect since the > > > > > other dependent module clock remains ON. > > > > > > > > > > > > I guess this statement is incorrect. Still in group-based, > > > > > > mstop bit is controlled by usage > > > > > count(ref_cnt). > > > > > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 > > > > > | 9 > > > > > | > > > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the > > > > > same MSTOP register say MSTOP1). Now this will be seperate > > > > > groups having separate count(ref_cnt). Say you turn ON IP-A > > > > > module clock and correspondingly clear the MSTOP bits and > > > > > similarly now lets turn ON module clocks for IP-B and clear the > > > > > MSTOP bits. Now let's say you want to turn OFF IP-A so you turn > > > > > OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > > > you will now see issues with IP-B as MSTOP BIT(10) has been set when > > > we turned OFF IP-A block. This case is handled by switching refcount on per mstop bit by this > patch. > > > > > > > > I agree, Do we have such use case? > > > > > > > Yes, for USB2.0 on RZ/V2H. > > > > OK, then it make sense for per-bit configuration. > > > > > > > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, > > > > bit10 and index 0, bit8 | index1, > > > bit 0 | index1 10 is addressed in current patch series? > > > > > > > Can you please elaborate, the above isn't clear to me. > > > > > > I just provide a random example for a future IP, where > > > > IP_A requires mstop1 {8,9,10} > > And > > IP_B requires mstop1 {8} and mstop2 {9, 10} > > > No, this case is not handled by the patch series. > > > Note: I haven't seen this scenario in hardware manual. > > > Yes, neither do I. For this case we will have to re-work the > BUS_MSTOP() macro. Let me know if we want this case to be handled. > I'll create a new patch on top of this series. I guess we can address this later when a real use case like USB2.0 arises. Cheers, Biju ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:44 ` Lad, Prabhakar 2025-01-07 12:50 ` Biju Das @ 2025-01-07 12:51 ` Geert Uytterhoeven 1 sibling, 0 replies; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-07 12:51 UTC (permalink / raw) To: Lad, Prabhakar Cc: Biju Das, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Prabhakar, On Tue, Jan 7, 2025 at 1:44 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Jan 7, 2025 at 12:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > Switch MSTOP handling from group-based to per-bit configuration > > > > > > > to address issues with shared dependencies between module > > > > > > > clocks. In the current group-based configuration, multiple > > > > > > > module clocks may rely on a single MSTOP bit. When both clocks > > > > > > > are turned ON and one is subsequently turned OFF, the shared > > > > > > > MSTOP bit will still be set, which is incorrect since the > > > > > other dependent module clock remains ON. > > > > > > > > > > > > I guess this statement is incorrect. Still in group-based, mstop > > > > > > bit is controlled by usage > > > > > count(ref_cnt). > > > > > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 > > > > > | > > > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same > > > > > MSTOP register say MSTOP1). Now this will be seperate groups having > > > > > separate count(ref_cnt). Say you turn ON IP-A module clock and > > > > > correspondingly clear the MSTOP bits and similarly now lets turn ON > > > > > module clocks for IP-B and clear the MSTOP bits. Now let's say you > > > > > want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > > > you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block. This > > > case is handled by switching refcount on per mstop bit by this patch. > > > > > > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, > > > bit 0 | index1 10 is addressed in current patch series? > > > > > > > Can you please elaborate, the above isn't clear to me. > > > > I just provide a random example for a future IP, where > > > > IP_A requires mstop1 {8,9,10} > > And > > IP_B requires mstop1 {8} and mstop2 {9, 10} > > > No, this case is not handled by the patch series. > > > Note: I haven't seen this scenario in hardware manual. > > > Yes, neither do I. For this case we will have to re-work the > BUS_MSTOP() macro. Let me know if we want this case to be handled. > I'll create a new patch on top of this series. -EPROBE_DEFER. I.e. fix it when the need arises (if ever)... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:38 ` Biju Das 2025-01-07 12:44 ` Lad, Prabhakar @ 2025-01-07 12:49 ` Geert Uytterhoeven 2025-01-07 12:51 ` Biju Das 1 sibling, 1 reply; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-07 12:49 UTC (permalink / raw) To: Biju Das Cc: Lad, Prabhakar, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Biju, On Tue, Jan 7, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Switch MSTOP handling from group-based to per-bit configuration > > > > > > to address issues with shared dependencies between module > > > > > > clocks. In the current group-based configuration, multiple > > > > > > module clocks may rely on a single MSTOP bit. When both clocks > > > > > > are turned ON and one is subsequently turned OFF, the shared > > > > > > MSTOP bit will still be set, which is incorrect since the > > > > other dependent module clock remains ON. > > > > > > > > > > I guess this statement is incorrect. Still in group-based, mstop > > > > > bit is controlled by usage > > > > count(ref_cnt). > > > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9 > > > > | > > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same > > > > MSTOP register say MSTOP1). Now this will be seperate groups having > > > > separate count(ref_cnt). Say you turn ON IP-A module clock and > > > > correspondingly clear the MSTOP bits and similarly now lets turn ON > > > > module clocks for IP-B and clear the MSTOP bits. Now let's say you > > > > want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > > you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block. This > > case is handled by switching refcount on per mstop bit by this patch. > > > > > > I agree, Do we have such use case? > > > > > Yes, for USB2.0 on RZ/V2H. > > OK, then it make sense for per-bit configuration. > > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1, > > bit 0 | index1 10 is addressed in current patch series? > > > > > Can you please elaborate, the above isn't clear to me. > > I just provide a random example for a future IP, where > > IP_A requires mstop1 {8,9,10} > And > IP_B requires mstop1 {8} and mstop2 {9, 10} > > Note: I haven't seen this scenario in hardware manual. That case is indeed not handled, and I had already checked before it is not needed for the current SoCs (until we discover e.g. a dependency between different GTM channels ;-) If it is ever needed for future SoCs, the system has to be adapted... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis 2025-01-07 12:49 ` Geert Uytterhoeven @ 2025-01-07 12:51 ` Biju Das 0 siblings, 0 replies; 25+ messages in thread From: Biju Das @ 2025-01-07 12:51 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad, Prabhakar, Michael Turquette, Stephen Boyd, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro, Prabhakar Mahadev Lad Hi Geert, > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: 07 January 2025 12:50 > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis > > Hi Biju, > > On Tue, Jan 7, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> On Tue, Jan 7, > > > 2025 at 12:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> On Tue, Jan 7, > > > > > 2025 at 11:24 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > From: Lad Prabhakar > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > Switch MSTOP handling from group-based to per-bit > > > > > > > configuration to address issues with shared dependencies > > > > > > > between module clocks. In the current group-based > > > > > > > configuration, multiple module clocks may rely on a single > > > > > > > MSTOP bit. When both clocks are turned ON and one is > > > > > > > subsequently turned OFF, the shared MSTOP bit will still be > > > > > > > set, which is incorrect since the > > > > > other dependent module clock remains ON. > > > > > > > > > > > > I guess this statement is incorrect. Still in group-based, > > > > > > mstop bit is controlled by usage > > > > > count(ref_cnt). > > > > > > > > > > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 > > > > > | 9 > > > > > | > > > > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the > > > > > same MSTOP register say MSTOP1). Now this will be seperate > > > > > groups having separate count(ref_cnt). Say you turn ON IP-A > > > > > module clock and correspondingly clear the MSTOP bits and > > > > > similarly now lets turn ON module clocks for IP-B and clear the > > > > > MSTOP bits. Now let's say you want to turn OFF IP-A so you turn > > > > > OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case > > > you will now see issues with IP-B as MSTOP BIT(10) has been set when > > > we turned OFF IP-A block. This case is handled by switching refcount on per mstop bit by this > patch. > > > > > > > > I agree, Do we have such use case? > > > > > > > Yes, for USB2.0 on RZ/V2H. > > > > OK, then it make sense for per-bit configuration. > > > > > > Consider another use case, index 0, bit 8| index 0, bit9| index0, > > > > bit10 and index 0, bit8 | index1, > > > bit 0 | index1 10 is addressed in current patch series? > > > > > > > Can you please elaborate, the above isn't clear to me. > > > > I just provide a random example for a future IP, where > > > > IP_A requires mstop1 {8,9,10} > > And > > IP_B requires mstop1 {8} and mstop2 {9, 10} > > > > Note: I haven't seen this scenario in hardware manual. > > That case is indeed not handled, and I had already checked before it is not needed for the current > SoCs (until we discover e.g. a dependency between different GTM channels ;-) If it is ever needed for > future SoCs, the system has to be adapted... I agree. Cheers, Biju ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar ` (3 preceding siblings ...) 2025-01-02 18:18 ` [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-03 15:57 ` Geert Uytterhoeven 2025-01-02 18:18 ` [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC Prabhakar 5 siblings, 1 reply; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add the missing reset entry for the `SYS` module in the clock driver. The corresponding core clock entry for `SYS` is already present. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2->v3 - Included RB tag from Geert v1->v2 - None --- drivers/clk/renesas/r9a09g057-cpg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index a45b4020996b..7ef681dfcba5 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -220,6 +220,7 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS 2025-01-02 18:18 ` [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS Prabhakar @ 2025-01-03 15:57 ` Geert Uytterhoeven 0 siblings, 0 replies; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-03 15:57 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add the missing reset entry for the `SYS` module in the clock driver. The > corresponding core clock entry for `SYS` is already present. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2->v3 > - Included RB tag from Geert Thanks, will queue in renesas-clk for v6.14. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar ` (4 preceding siblings ...) 2025-01-02 18:18 ` [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS Prabhakar @ 2025-01-02 18:18 ` Prabhakar 2025-01-03 15:58 ` Geert Uytterhoeven 5 siblings, 1 reply; 25+ messages in thread From: Prabhakar @ 2025-01-02 18:18 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd Cc: linux-renesas-soc, linux-clk, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add clock and reset entries for GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2->v3 - Included RB tag from Geert v1->v2 - None --- drivers/clk/renesas/r9a09g057-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 7ef681dfcba5..3705e18f66ad 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -117,6 +117,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, BUS_MSTOP_NONE), + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, BUS_MSTOP(5, BIT(10))), DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, @@ -222,6 +224,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC 2025-01-02 18:18 ` [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC Prabhakar @ 2025-01-03 15:58 ` Geert Uytterhoeven 0 siblings, 0 replies; 25+ messages in thread From: Geert Uytterhoeven @ 2025-01-03 15:58 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk, linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add clock and reset entries for GIC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2->v3 > - Included RB tag from Geert Thanks, will queue in renesas-clk for v6.14. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-01-07 12:51 UTC | newest] Thread overview: 25+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-02 18:18 [PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC Prabhakar 2025-01-02 18:18 ` [PATCH v3 1/6] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling Prabhakar 2025-01-02 18:18 ` [PATCH v3 2/6] clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver Prabhakar 2025-01-02 18:18 ` [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Prabhakar 2025-01-03 2:21 ` kernel test robot 2025-01-03 10:03 ` Lad, Prabhakar 2025-01-03 10:42 ` kernel test robot 2025-01-03 17:07 ` Geert Uytterhoeven 2025-01-04 8:16 ` Lad, Prabhakar 2025-01-02 18:18 ` [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis Prabhakar 2025-01-03 17:06 ` Geert Uytterhoeven 2025-01-07 11:24 ` Biju Das 2025-01-07 11:45 ` Lad, Prabhakar 2025-01-07 12:25 ` Biju Das 2025-01-07 12:31 ` Lad, Prabhakar 2025-01-07 12:38 ` Biju Das 2025-01-07 12:44 ` Lad, Prabhakar 2025-01-07 12:50 ` Biju Das 2025-01-07 12:51 ` Geert Uytterhoeven 2025-01-07 12:49 ` Geert Uytterhoeven 2025-01-07 12:51 ` Biju Das 2025-01-02 18:18 ` [PATCH v3 5/6] clk: renesas: r9a09g057: Add reset entry for SYS Prabhakar 2025-01-03 15:57 ` Geert Uytterhoeven 2025-01-02 18:18 ` [PATCH v3 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GIC Prabhakar 2025-01-03 15:58 ` Geert Uytterhoeven
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