From: Bjorn Helgaas <helgaas@kernel.org>
To: Terry Bowman <terry.bowman@amd.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com,
oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com,
nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
lukas@wunner.de, ming.li@zohomail.com,
PradeepVineshReddy.Kodamati@amd.com
Subject: Re: [PATCH v7 01/17] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver'
Date: Tue, 11 Feb 2025 14:25:51 -0600 [thread overview]
Message-ID: <20250211202551.GA53774@bhelgaas> (raw)
In-Reply-To: <20250211192444.2292833-2-terry.bowman@amd.com>
On Tue, Feb 11, 2025 at 01:24:28PM -0600, Terry Bowman wrote:
> CXL.io is implemented on top of PCIe Protocol Errors. But, CXL.io and PCIe
> have different handling requirements for uncorrectable errors (UCE).
>
> The PCIe AER service driver may attempt recovering PCIe devices with
> UCE while recovery is not used for CXL.io. Recovery is not used in the
> CXL.io case because of potential corruption on what can be system memory.
>
> Create pci_driver::cxl_err_handlers structure similar to
> pci_driver::error_handler. Create handlers for correctable and
> uncorrectable CXL.io error handling.
>
> The CXL error handlers will be used in future patches adding CXL PCIe
> Port Protocol Error handling.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> include/linux/pci.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 47b31ad724fa..1d62e785ae1f 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -884,6 +884,14 @@ struct pci_error_handlers {
> void (*cor_error_detected)(struct pci_dev *dev);
> };
>
> +/* Compute Express Link (CXL) bus error event callbacks */
> +struct cxl_error_handlers {
> + /* CXL bus error detected on this device */
> + pci_ers_result_t (*error_detected)(struct pci_dev *dev);
> +
> + /* Allow device driver to record more details of a correctable error */
> + void (*cor_error_detected)(struct pci_dev *dev);
> +};
>
> struct module;
>
> @@ -929,6 +937,7 @@ struct module;
> * @sriov_get_vf_total_msix: PF driver callback to get the total number of
> * MSI-X vectors available for distribution to the VFs.
> * @err_handler: See Documentation/PCI/pci-error-recovery.rst
> + * @cxl_err_handler: Compute Express Link specific error handlers.
> * @groups: Sysfs attribute groups.
> * @dev_groups: Attributes attached to the device that will be
> * created once it is bound to the driver.
> @@ -954,6 +963,7 @@ struct pci_driver {
> int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
> u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
> const struct pci_error_handlers *err_handler;
> + const struct cxl_error_handlers *cxl_err_handler;
> const struct attribute_group **groups;
> const struct attribute_group **dev_groups;
> struct device_driver driver;
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-02-11 20:25 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 19:24 [PATCH v7 00/17] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-02-11 19:24 ` [PATCH v7 01/17] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-02-11 20:25 ` Bjorn Helgaas [this message]
2025-02-11 20:42 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 02/17] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-02-11 20:26 ` Bjorn Helgaas
2025-02-11 20:44 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 03/17] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 20:38 ` Bowman, Terry
2025-02-11 22:33 ` Dan Williams
2025-02-12 19:07 ` Bowman, Terry
2025-02-12 19:51 ` Dan Williams
2025-03-04 19:11 ` Ira Weiny
2025-02-11 19:24 ` [PATCH v7 04/17] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 23:47 ` Dan Williams
2025-02-12 19:15 ` Bowman, Terry
2025-02-12 19:57 ` Dan Williams
2025-02-12 21:08 ` Bowman, Terry
2025-02-12 21:17 ` Lukas Wunner
2025-02-11 19:24 ` [PATCH v7 05/17] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 23:58 ` Dan Williams
2025-02-12 21:52 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error recovery " Terry Bowman
2025-02-11 20:29 ` Bjorn Helgaas
2025-02-11 21:59 ` Dave Jiang
2025-02-12 0:02 ` Gregory Price
2025-02-12 0:24 ` Dan Williams
2025-02-14 19:36 ` Bowman, Terry
2025-02-14 15:11 ` Jonathan Cameron
2025-02-18 15:43 ` Bowman, Terry
2025-02-14 17:36 ` Fan Ni
2025-02-11 19:24 ` [PATCH v7 07/17] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-02-11 22:40 ` Dave Jiang
2025-02-12 1:23 ` Dan Williams
2025-02-13 15:43 ` Bowman, Terry
2025-02-14 21:24 ` Dan Williams
2025-02-14 22:23 ` Bowman, Terry
2025-02-14 22:42 ` Dan Williams
2025-02-12 22:28 ` Alison Schofield
2025-02-12 22:37 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-02-11 23:02 ` Dave Jiang
2025-02-12 2:00 ` Dan Williams
2025-02-14 19:46 ` Bowman, Terry
2025-02-14 21:29 ` Dan Williams
2025-02-14 15:15 ` Jonathan Cameron
2025-02-14 19:50 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 09/17] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-02-11 23:26 ` Dave Jiang
2025-02-14 15:19 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 10/17] cxl/pci: Add log message and add type check in existing RAS handlers Terry Bowman
2025-02-11 23:28 ` Dave Jiang
2025-02-12 22:59 ` Dan Williams
2025-02-13 0:08 ` Bowman, Terry
2025-02-14 15:28 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 11/17] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-02-11 23:42 ` Dave Jiang
2025-02-13 23:15 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 12/17] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-02-12 0:11 ` Dave Jiang
2025-02-12 16:34 ` Bowman, Terry
2025-02-14 2:18 ` Dan Williams
2025-02-14 21:43 ` Bowman, Terry
2025-02-15 0:20 ` Dan Williams
2025-02-18 15:33 ` Bowman, Terry
2025-02-18 17:15 ` Dan Williams
2025-03-05 0:22 ` Ira Weiny
2025-03-06 13:50 ` Bowman, Terry
2025-03-06 13:50 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 13/17] cxl/pci: Add trace logging " Terry Bowman
2025-02-12 0:11 ` Gregory Price
2025-02-12 0:17 ` Dave Jiang
2025-02-12 0:19 ` Dave Jiang
2025-02-12 16:23 ` Bowman, Terry
2025-02-14 2:21 ` Dan Williams
2025-02-14 15:34 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF Terry Bowman
2025-02-12 0:21 ` Dave Jiang
2025-02-12 16:20 ` Bowman, Terry
2025-02-12 23:30 ` Alison Schofield
2025-02-12 23:34 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 15/17] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-02-12 0:38 ` Dave Jiang
2025-02-14 2:29 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 16/17] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-02-11 20:25 ` Bjorn Helgaas
2025-02-11 20:40 ` Bowman, Terry
2025-02-12 0:40 ` Dave Jiang
2025-02-14 2:35 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 17/17] cxl/pci: Handle CXL Endpoint and RCH Protocol Errors separately from PCIe errors Terry Bowman
2025-02-14 2:43 ` Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250211202551.GA53774@bhelgaas \
--to=helgaas@kernel.org \
--cc=Benjamin.Cheatham@amd.com \
--cc=PradeepVineshReddy.Kodamati@amd.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=mahesh@linux.ibm.com \
--cc=ming.li@zohomail.com \
--cc=nathan.fontenot@amd.com \
--cc=nifan.cxl@gmail.com \
--cc=oohall@gmail.com \
--cc=rrichter@amd.com \
--cc=terry.bowman@amd.com \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox