Re: [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers

["Bowman, Terry" <terry.bowman@amd.com>]

On 2/11/2025 8:00 PM, Dan Williams wrote:
> Terry Bowman wrote:
>> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers.
>>
>> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a
>> pointer to the CXL Upstream Port's mapped RAS registers.
>>
>> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS
>> register mapping. This is similar to the existing
>> cxl_dport_init_ras_reporting() but for USP devices.
>>
>> The USP may have multiple downstream endpoints. Before mapping RAS
>> registers check if the registers are already mapped.
> Yes, now this sharing makes sense, but the ras_init_mutex +
> cxl_init_ep_ports_aer() approach to solving it is broken.
>
>> Introduce a mutex for synchronizing accesses to the cached RAS
>> mapping.
> In this case, especially for VH configs, you should just be able to map
> the RAS registers once from cxl_endpoint_port_probe(). That will
> naturally only be called once when the first endpoint arrives, and will
> never be torn down until the last cxl_detach_ep() event triggers
> delete_switch_port().
There is still RPs and USPs that will be called for mapping more than once,
right? This will require synchronization, right?

Terry