* [PATCH v3 2/3] drm/tidss: Update infrastructure to support K3 DSS cut-down versions
2025-03-06 13:29 [PATCH v3 0/3] Add support for AM62L DSS Devarsh Thakkar
2025-03-06 13:29 ` [PATCH v3 1/3] dt-bindings: display: ti,am65x-dss: " Devarsh Thakkar
@ 2025-03-06 13:29 ` Devarsh Thakkar
2025-03-06 13:29 ` [PATCH v3 3/3] drm/tidss: Add support for AM62L display subsystem Devarsh Thakkar
2 siblings, 0 replies; 5+ messages in thread
From: Devarsh Thakkar @ 2025-03-06 13:29 UTC (permalink / raw)
To: jyri.sarha, tomi.valkeinen, airlied, maarten.lankhorst, mripard,
tzimmermann, dri-devel, simona, linux-kernel, devicetree, robh,
krzk+dt, conor+dt
Cc: praneeth, vigneshr, aradhya.bhatia, s-jain1, r-donadkar,
j-choudhary, h-shenoy, devarsht
SoCs like AM62Lx support cut-down version of DSS7 where
although same register space is supported as in other
DSS7 supported SoCs such as AM65x, AM62x, AM62Ax but some of
the resources such as planes and corresponding register spaces
are truncated.
For e.g. AM62Lx has only single VIDL pipeline supported, so
corresponding register spaces for other video pipelines need
to be skipped.
To add a generic support for future SoCs whether one or more
video pipelines can get truncated from the parent register space,
move the plane related information to plane_info struct which will
also have a flag to indicate whether that plane is actually supported
or it is truncated. If the plane is truncated, then skip the access
to corresponding register space while doing plane related operations.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
---
V3: Patch is introduced
V2: Patch not present
drivers/gpu/drm/tidss/tidss_crtc.c | 7 +-
drivers/gpu/drm/tidss/tidss_dispc.c | 133 +++++++++++++++++++++++-----
drivers/gpu/drm/tidss/tidss_dispc.h | 9 +-
drivers/gpu/drm/tidss/tidss_irq.c | 6 ++
drivers/gpu/drm/tidss/tidss_kms.c | 10 ++-
5 files changed, 135 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c
index 94f8e3178df5..0e08d2242c90 100644
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss,
!to_tidss_crtc_state(cstate)->plane_pos_changed)
return;
- for (layer = 0; layer < tidss->feat->num_planes; layer++) {
+ for (layer = 0; layer < tidss->num_planes ; layer++) {
struct drm_plane_state *pstate;
struct drm_plane *plane;
bool layer_active = false;
@@ -271,9 +271,12 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,
* another videoport, the DSS will report sync lost issues. Disable all
* the layers here as a work-around.
*/
- for (u32 layer = 0; layer < tidss->feat->num_planes; layer++)
+ for (u32 layer = 0; layer < tidss->feat->num_planes; layer++) {
+ if (!tidss->feat->vid_info[layer].is_present)
+ continue;
dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
false);
+ }
dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport);
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index cacb5f3d8085..9b46403dbb0c 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -104,8 +104,15 @@ const struct dispc_features dispc_k2g_feats = {
},
.num_planes = 1,
- .vid_name = { "vid1" },
- .vid_lite = { false },
+
+ .vid_info = {
+ {
+ .vid_name = "vid1",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ },
+
.vid_order = { 0 },
};
@@ -180,9 +187,20 @@ const struct dispc_features dispc_am65x_feats = {
.num_planes = 2,
/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
- .vid_name = { "vid", "vidl1" },
- .vid_lite = { false, true, },
- .vid_order = { 1, 0 },
+ .vid_info = {
+ {
+ .vid_name = "vid",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vidl1",
+ .vid_lite = true,
+ .is_present = true,
+ },
+ },
+
+ .vid_order = {1, 0},
};
static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
@@ -267,9 +285,32 @@ const struct dispc_features dispc_j721e_feats = {
.gamma_type = TIDSS_GAMMA_10BIT,
},
},
+
.num_planes = 4,
- .vid_name = { "vid1", "vidl1", "vid2", "vidl2" },
- .vid_lite = { 0, 1, 0, 1, },
+
+ .vid_info = {
+ {
+ .vid_name = "vid1",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vidl1",
+ .vid_lite = true,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vid2",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vidl2",
+ .vid_lite = true,
+ .is_present = true,
+ },
+ },
+
.vid_order = { 1, 3, 0, 2 },
};
@@ -316,10 +357,22 @@ const struct dispc_features dispc_am625_feats = {
},
.num_planes = 2,
+
/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
- .vid_name = { "vid", "vidl1" },
- .vid_lite = { false, true, },
- .vid_order = { 1, 0 },
+ .vid_info = {
+ {
+ .vid_name = "vid",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vidl1",
+ .vid_lite = true,
+ .is_present = true,
+ }
+ },
+
+ .vid_order = {1, 0},
};
const struct dispc_features dispc_am62a7_feats = {
@@ -370,10 +423,21 @@ const struct dispc_features dispc_am62a7_feats = {
},
.num_planes = 2,
- /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
- .vid_name = { "vid", "vidl1" },
- .vid_lite = { false, true, },
- .vid_order = { 1, 0 },
+
+ .vid_info = {
+ {
+ .vid_name = "vid",
+ .vid_lite = false,
+ .is_present = true,
+ },
+ {
+ .vid_name = "vidl1",
+ .vid_lite = true,
+ .is_present = true,
+ }
+ },
+
+ .vid_order = {1, 0},
};
static const u16 *dispc_common_regmap;
@@ -788,7 +852,11 @@ void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
if (clearmask & DSS_IRQ_VP_MASK(i))
dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
}
+
for (i = 0; i < dispc->feat->num_planes; ++i) {
+ if (!dispc->feat->vid_info[i].is_present)
+ continue;
+
if (clearmask & DSS_IRQ_PLANE_MASK(i))
dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
}
@@ -809,8 +877,12 @@ dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
for (i = 0; i < dispc->feat->num_vps; ++i)
status |= dispc_k3_vp_read_irqstatus(dispc, i);
- for (i = 0; i < dispc->feat->num_planes; ++i)
+ for (i = 0; i < dispc->feat->num_planes; ++i) {
+ if (!dispc->feat->vid_info[i].is_present)
+ continue;
+
status |= dispc_k3_vid_read_irqstatus(dispc, i);
+ }
dispc_k3_clear_irqstatus(dispc, status);
@@ -825,8 +897,12 @@ static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
for (i = 0; i < dispc->feat->num_vps; ++i)
enable |= dispc_k3_vp_read_irqenable(dispc, i);
- for (i = 0; i < dispc->feat->num_planes; ++i)
+ for (i = 0; i < dispc->feat->num_planes; ++i) {
+ if (!dispc->feat->vid_info[i].is_present)
+ continue;
+
enable |= dispc_k3_vid_read_irqenable(dispc, i);
+ }
return enable;
}
@@ -849,9 +925,12 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc,
main_enable |= BIT(i); /* VP IRQ */
else
main_disable |= BIT(i); /* VP IRQ */
+
}
for (i = 0; i < dispc->feat->num_planes; ++i) {
+ if (!dispc->feat->vid_info[i].is_present)
+ continue;
dispc_k3_vid_set_irqenable(dispc, i, mask);
if (mask & DSS_IRQ_PLANE_MASK(i))
main_enable |= BIT(i + 4); /* VID IRQ */
@@ -861,7 +940,6 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc,
if (main_enable)
dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
-
if (main_disable)
dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
@@ -2025,7 +2103,7 @@ int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
const struct drm_plane_state *state,
u32 hw_videoport)
{
- bool lite = dispc->feat->vid_lite[hw_plane];
+ bool lite = dispc->feat->vid_info[hw_plane].vid_lite;
u32 fourcc = state->fb->format->format;
bool need_scaling = state->src_w >> 16 != state->crtc_w ||
state->src_h >> 16 != state->crtc_h;
@@ -2096,7 +2174,7 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
const struct drm_plane_state *state,
u32 hw_videoport)
{
- bool lite = dispc->feat->vid_lite[hw_plane];
+ bool lite = dispc->feat->vid_info[hw_plane].vid_lite;
u32 fourcc = state->fb->format->format;
u16 cpp = state->fb->format->cpp[0];
u32 fb_width = state->fb->pitches[0] / cpp;
@@ -2211,6 +2289,9 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
+ if (!dispc->feat->vid_info[hw_plane].is_present)
+ continue;
+
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
u32 thr_low, thr_high;
u32 mflag_low, mflag_high;
@@ -2226,7 +2307,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
dev_dbg(dispc->dev,
"%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
- dispc->feat->vid_name[hw_plane],
+ dispc->feat->vid_info[hw_plane].vid_name,
size,
thr_high, thr_low,
mflag_high, mflag_low,
@@ -2266,6 +2347,9 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
+ if (!dispc->feat->vid_info[hw_plane].is_present)
+ continue;
+
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
u32 thr_low, thr_high;
u32 mflag_low, mflag_high;
@@ -2281,7 +2365,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
dev_dbg(dispc->dev,
"%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
- dispc->feat->vid_name[hw_plane],
+ dispc->feat->vid_info[hw_plane].vid_name,
size,
thr_high, thr_low,
mflag_high, mflag_low,
@@ -2899,8 +2983,11 @@ int dispc_init(struct tidss_device *tidss)
return r;
for (i = 0; i < dispc->feat->num_planes; i++) {
- r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
- &dispc->base_vid[i]);
+ if (dispc->feat->vid_info[i].is_present) {
+ r = dispc_iomap_resource(pdev, dispc->feat->vid_info[i].vid_name,
+ &dispc->base_vid[i]);
+ }
+
if (r)
return r;
}
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index 086327d51a90..f1755e031348 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -46,6 +46,12 @@ struct dispc_features_scaling {
u32 xinc_max;
};
+struct plane_info {
+ const char *vid_name; /* Should match dt reg names */
+ bool vid_lite;
+ bool is_present;
+};
+
struct dispc_errata {
bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */
};
@@ -83,8 +89,7 @@ struct dispc_features {
const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
struct tidss_vp_feat vp_feat;
u32 num_planes;
- const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
- bool vid_lite[TIDSS_MAX_PLANES];
+ struct plane_info vid_info[TIDSS_MAX_PLANES];
u32 vid_order[TIDSS_MAX_PLANES];
};
diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c
index 5abc788781f4..dce03504d006 100644
--- a/drivers/gpu/drm/tidss/tidss_irq.c
+++ b/drivers/gpu/drm/tidss/tidss_irq.c
@@ -83,6 +83,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)
struct drm_plane *plane = tidss->planes[i];
struct tidss_plane *tplane = to_tidss_plane(plane);
+ if (!(tidss->feat->vid_info[i].is_present))
+ continue;
+
if (irqstatus & DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id))
tidss_plane_error_irq(plane, irqstatus);
}
@@ -122,6 +125,9 @@ int tidss_irq_install(struct drm_device *ddev, unsigned int irq)
}
for (unsigned int i = 0; i < tidss->num_planes; ++i) {
+ if (!tidss->feat->vid_info[i].is_present)
+ continue;
+
struct tidss_plane *tplane = to_tidss_plane(tidss->planes[i]);
tidss->irq_mask |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id);
diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c
index f371518f8697..c0184c5ea23e 100644
--- a/drivers/gpu/drm/tidss/tidss_kms.c
+++ b/drivers/gpu/drm/tidss/tidss_kms.c
@@ -191,6 +191,9 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)
u32 hw_plane_id = feat->vid_order[tidss->num_planes];
int ret;
+ if (!feat->vid_info[hw_plane_id].is_present)
+ continue;
+
tplane = tidss_plane_create(tidss, hw_plane_id,
DRM_PLANE_TYPE_PRIMARY, crtc_mask,
fourccs, fourccs_len);
@@ -220,15 +223,16 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)
}
/* create overlay planes of the leftover planes */
-
- while (tidss->num_planes < max_planes) {
+ for (i = tidss->num_planes; i < max_planes ; i++) {
struct tidss_plane *tplane;
u32 hw_plane_id = feat->vid_order[tidss->num_planes];
+ if (!feat->vid_info[hw_plane_id].is_present)
+ continue;
+
tplane = tidss_plane_create(tidss, hw_plane_id,
DRM_PLANE_TYPE_OVERLAY, crtc_mask,
fourccs, fourccs_len);
-
if (IS_ERR(tplane)) {
dev_err(tidss->dev, "plane create failed\n");
return PTR_ERR(tplane);
--
2.39.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 3/3] drm/tidss: Add support for AM62L display subsystem
2025-03-06 13:29 [PATCH v3 0/3] Add support for AM62L DSS Devarsh Thakkar
2025-03-06 13:29 ` [PATCH v3 1/3] dt-bindings: display: ti,am65x-dss: " Devarsh Thakkar
2025-03-06 13:29 ` [PATCH v3 2/3] drm/tidss: Update infrastructure to support K3 DSS cut-down versions Devarsh Thakkar
@ 2025-03-06 13:29 ` Devarsh Thakkar
2025-03-13 9:41 ` Tomi Valkeinen
2 siblings, 1 reply; 5+ messages in thread
From: Devarsh Thakkar @ 2025-03-06 13:29 UTC (permalink / raw)
To: jyri.sarha, tomi.valkeinen, airlied, maarten.lankhorst, mripard,
tzimmermann, dri-devel, simona, linux-kernel, devicetree, robh,
krzk+dt, conor+dt
Cc: praneeth, vigneshr, aradhya.bhatia, s-jain1, r-donadkar,
j-choudhary, h-shenoy, devarsht
Enable display for AM62L DSS [1] which supports only a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and
the DPI signals from the video port are also routed to DSI Tx controller
present within the SoC.
[1]: Section 11.7 (Display Subsystem and Peripherals)
Link : https://www.ti.com/lit/pdf/sprujb4
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
---
V3:
- Rebase on top of
0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch
- Use the generic "tidss_am65x_common_regs" as common reg space
instead of creating a new one.
V2:
- Add separate common reg space for AM62L
- Add separate irq enable/disable/read/clear helpers for AM62L
- Use separate helper function for setting overlay attributes
- Drop Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
due to additional changes made in V2.
drivers/gpu/drm/tidss/tidss_dispc.c | 46 +++++++++++++++++++++++++++++
drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++
drivers/gpu/drm/tidss/tidss_drv.c | 1 +
3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 9b46403dbb0c..0ca0c2106715 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -440,6 +440,47 @@ const struct dispc_features dispc_am62a7_feats = {
.vid_order = {1, 0},
};
+const struct dispc_features dispc_am62l_feats = {
+ .max_pclk_khz = {
+ [DISPC_VP_DPI] = 165000,
+ },
+
+ .subrev = DISPC_AM62L,
+
+ .common = "common",
+ .common_regs = tidss_am65x_common_regs,
+
+ .num_vps = 1,
+ .vp_name = { "vp1" },
+ .ovr_name = { "ovr1" },
+ .vpclk_name = { "vp1" },
+ .vp_bus_type = { DISPC_VP_DPI },
+
+ .vp_feat = { .color = {
+ .has_ctm = true,
+ .gamma_size = 256,
+ .gamma_type = TIDSS_GAMMA_8BIT,
+ },
+ },
+
+ .num_planes = 2,
+
+ .vid_info = {
+ {
+ .vid_name = "vid",
+ .vid_lite = false,
+ .is_present = false,
+ },
+ {
+ .vid_name = "vidl1",
+ .vid_lite = true,
+ .is_present = true,
+ }
+ },
+
+ .vid_order = {1, 0},
+};
+
static const u16 *dispc_common_regmap;
struct dss_vp_data {
@@ -957,6 +998,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
return dispc_k2g_read_and_clear_irqstatus(dispc);
case DISPC_AM625:
case DISPC_AM62A7:
+ case DISPC_AM62L:
case DISPC_AM65X:
case DISPC_J721E:
return dispc_k3_read_and_clear_irqstatus(dispc);
@@ -974,6 +1016,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
break;
case DISPC_AM625:
case DISPC_AM62A7:
+ case DISPC_AM62L:
case DISPC_AM65X:
case DISPC_J721E:
dispc_k3_set_irqenable(dispc, mask);
@@ -1466,6 +1509,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
break;
case DISPC_AM625:
case DISPC_AM62A7:
+ case DISPC_AM62L:
case DISPC_AM65X:
dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
x, y, layer);
@@ -2392,6 +2436,7 @@ static void dispc_plane_init(struct dispc_device *dispc)
break;
case DISPC_AM625:
case DISPC_AM62A7:
+ case DISPC_AM62L:
case DISPC_AM65X:
case DISPC_J721E:
dispc_k3_plane_init(dispc);
@@ -2500,6 +2545,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
break;
case DISPC_AM625:
case DISPC_AM62A7:
+ case DISPC_AM62L:
case DISPC_AM65X:
dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
break;
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index f1755e031348..61d1087c5cf0 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -67,6 +67,7 @@ enum dispc_vp_bus_type {
enum dispc_dss_subrevision {
DISPC_K2G,
DISPC_AM625,
+ DISPC_AM62L,
DISPC_AM62A7,
DISPC_AM65X,
DISPC_J721E,
@@ -96,6 +97,7 @@ struct dispc_features {
extern const struct dispc_features dispc_k2g_feats;
extern const struct dispc_features dispc_am625_feats;
extern const struct dispc_features dispc_am62a7_feats;
+extern const struct dispc_features dispc_am62l_feats;
extern const struct dispc_features dispc_am65x_feats;
extern const struct dispc_features dispc_j721e_feats;
diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c
index d4652e8cc28c..f2a4f659f574 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.c
+++ b/drivers/gpu/drm/tidss/tidss_drv.c
@@ -242,6 +242,7 @@ static const struct of_device_id tidss_of_table[] = {
{ .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, },
{ .compatible = "ti,am625-dss", .data = &dispc_am625_feats, },
{ .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, },
+ { .compatible = "ti,am62l-dss", .data = &dispc_am62l_feats, },
{ .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, },
{ .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, },
{ }
--
2.39.1
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