* [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-17 14:06 ` Mark Brown
2025-03-13 18:34 ` [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command Raju Rangoju
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch enables core eSPI controller initialization in AMD embedded
platforms, supporting communication with eSPI slave devices through the
device file entry. Currently, the eSPI controller in AMD embedded platforms
has only one chip select line enabled, which is connected to the Embedded
Controller (EC).
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
MAINTAINERS | 6 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 2 +
drivers/spi/espi-amd-core.c | 883 +++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd-dev.c | 128 +++++
drivers/spi/espi-amd-err.h | 50 ++
drivers/spi/espi-amd-slave.h | 109 +++++
drivers/spi/espi-amd.h | 291 ++++++++++++
8 files changed, 1479 insertions(+)
create mode 100644 drivers/spi/espi-amd-core.c
create mode 100644 drivers/spi/espi-amd-dev.c
create mode 100644 drivers/spi/espi-amd-err.h
create mode 100644 drivers/spi/espi-amd-slave.h
create mode 100644 drivers/spi/espi-amd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f052994b7d4..c102dcce5892 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1059,6 +1059,12 @@ S: Supported
F: drivers/gpu/drm/amd/display/dc/dml/
F: drivers/gpu/drm/amd/display/dc/dml2/
+AMD ESPI DRIVER
+M: Raju Rangoju<raju.rangoju@amd.com>
+L: linux-spi@vger.kernel.org
+S: Supported
+F: drivers/spi/espi-amd*
+
AMD FAM15H PROCESSOR POWER MONITORING DRIVER
M: Huang Rui <ray.huang@amd.com>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ea8a31032927..72b950f3eccb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -1238,6 +1238,16 @@ config SPI_AMD
help
Enables SPI controller driver for AMD SoC.
+config SPI_AMD_ESPI
+ tristate "AMD eSPI controller"
+ depends on X86_64 || SPI_MASTER || COMPILE_TEST
+ help
+ AMD SOCs contains multiple SPI controllers, including a dedicated
+ eSPI controller. This config enables eSPI controller driver for
+ AMD SoC. AMD eSPI driver aims to comprehensive support for the
+ eSPI protocol, including initialization of eSPI controller
+ and slave devices and eSPI channel specific commands.
+
#
# Add new SPI master controllers in alphabetical order above this line
#
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 9db7554c1864..0dec8ad30967 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -159,6 +159,8 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
obj-$(CONFIG_SPI_AMD) += spi-amd.o
+obj-$(CONFIG_SPI_AMD_ESPI) += espi-amd.o
+espi-amd-objs := espi-amd-core.o espi-amd-dev.o
# SPI slave protocol handlers
obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o
diff --git a/drivers/spi/espi-amd-core.c b/drivers/spi/espi-amd-core.c
new file mode 100644
index 000000000000..72a625b8b16d
--- /dev/null
+++ b/drivers/spi/espi-amd-core.c
@@ -0,0 +1,883 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD eSPI controller driver
+ *
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Authors: Krishnamoorthi M <krishnamoorthi.m@amd.com>
+ * Akshata MukundShetty<akshata.mukundshetty@amd.com>
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/acpi.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+
+#include "espi-amd.h"
+#include "espi-amd-slave.h"
+#include "espi-amd-err.h"
+
+#define ESPI_CH_READY_TIMEOUT_US 200
+
+/*
+ * In case of get configuration command, hdata0 contains bits[15:8] of the slave register address
+ * and hdata1 contains bits[7:0] of the slave register address.
+ */
+#define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & GENMASK(7, 0))
+#define ESPI_CONFIGURATION_HDATA1(a) ((a) & GENMASK(7, 0))
+#define ESPI_INTR_MASK GENMASK(31, 0)
+
+static int amd_espi_set_initial_config(struct amd_espi *amd_espi);
+
+static void amd_espi_clear_status(struct amd_espi *amd_espi)
+{
+ u32 status = readl(ESPI_BASE + AMD_ESPI_SLAVE0_INT_STS_REG);
+
+ if (status)
+ writel(status, (ESPI_BASE + AMD_ESPI_SLAVE0_INT_STS_REG));
+}
+
+void amd_espi_clr_all_intr(struct amd_espi *amd_espi)
+{
+ /* Set all bits to clear all the interrupt */
+ writel(ESPI_INTR_MASK, (ESPI_BASE + AMD_ESPI_SLAVE0_INT_STS_REG));
+}
+
+static int amd_espi_check_error_status(struct amd_espi *amd_espi, u32 status)
+{
+ int ret = CB_SUCCESS;
+
+ if (!(status & ESPI_DNCMD_INT)) {
+ ret = ESPI_DNCMD_INT;
+ dev_err(amd_espi->dev, "eSPI downstream command completion failure\n");
+ } else if (status & ESPI_BUS_ERR_INT) {
+ ret = ESPI_BUS_ERR_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_BUS_TIMING]);
+ } else if (status & ESPI_WAIT_TIMEOUT_INT) {
+ ret = ESPI_WAIT_TIMEOUT_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_BUS_WAIT_STATE]);
+ } else if (status & ESPI_CRC_ERR_INT) {
+ ret = ESPI_CRC_ERR_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_CRC]);
+ } else if (status & ESPI_NO_RESP_INT) {
+ ret = ESPI_NO_RESP_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_NO_RESP]);
+ } else if (status & ESPI_FATAL_ERR_INT) {
+ ret = ESPI_FATAL_ERR_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_FATAL_ERR]);
+ } else if (status & ESPI_NON_FATAL_ERR_INT) {
+ ret = ESPI_NON_FATAL_ERR_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_NON_FATAL_ERR]);
+ } else if (status & ESPI_INVALID_RESP_CODE_INT) {
+ ret = ESPI_INVALID_RESP_CODE_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_INVALID_RESP_CODE]);
+ } else if (status & ESPI_INVALID_CYCLE_TYPE_INT) {
+ ret = ESPI_INVALID_CYCLE_TYPE_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_INVALID_CYCLE_TYPE]);
+ } else if (status & ESPI_UNSUCCESS_CPL_RECV_INT) {
+ ret = ESPI_UNSUCCESS_CPL_RECV_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_UNSUCCESS_CPL_RECV]);
+ } else if (status & ESPI_ILLEGAL_RESP_TAG_INT) {
+ ret = ESPI_ILLEGAL_RESP_TAG_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_ILLEGAL_RESP_TAG]);
+ } else if (status & ESPI_ILLEGAL_RESP_LEN_INT) {
+ ret = ESPI_ILLEGAL_RESP_LEN_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_ILLEGAL_RESP_LEN]);
+ } else if (status & ESPI_RX_OOB_OVERFLOW_INT) {
+ ret = ESPI_RX_OOB_OVERFLOW_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_OOB_DATA_LEN]);
+ } else if (status & ESPI_RX_PC_MSG_OVERFLOW_INT) {
+ ret = ESPI_RX_PC_MSG_OVERFLOW_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_PC_MSG_DATA]);
+ } else if (status & ESPI_RX_FLASH_MSG_OVERFLOW_INT) {
+ ret = ESPI_RX_FLASH_MSG_OVERFLOW_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_FLASH_DATA_LEN]);
+ } else if (status & ESPI_PROTOCOL_ERR_INT) {
+ ret = ESPI_PROTOCOL_ERR_INT;
+ dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_PROTOCOL_ERR]);
+ }
+
+ return ret;
+}
+
+static int amd_espi_alloc_cmd_data(struct espi_txcmd *cmd)
+{
+ u32 size = 0;
+
+ switch (cmd->hdr0.cmd_type) {
+ case SET_CONFIGURATION:
+ case GET_CONFIGURATION:
+ case IN_BAND_RESET:
+ size = 1;
+ default:
+ break;
+ }
+
+ if (!size)
+ return -EOPNOTSUPP;
+
+ size = DATA_SIZE_ROUNDOFF_4(size);
+ cmd->data = kzalloc(size, GFP_KERNEL);
+
+ if (!cmd->data)
+ return -ENOMEM;
+
+ return CB_SUCCESS;
+}
+
+static void amd_espi_send_downstream_data(struct amd_espi *amd_espi, struct espi_txcmd *cmd)
+{
+ union espi_txdata *data = cmd->data;
+
+ /* Write first 4 bytes of data - common for all eSPI commands */
+ writel(data->val, (ESPI_BASE + AMD_ESPI_DS_DATA_REG0));
+}
+
+static void amd_espi_cmd_reg_dump(struct device *dev, struct espi_txcmd *cmd)
+{
+ dev_err(dev, "eSPI command packet:\n"
+ "Header-0: %08x\nHeader-1: %08x\n"
+ "Header-2: %08x\nData: %08x\n",
+ cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data->val);
+}
+
+static int amd_espi_send_cmd(struct amd_espi *amd_espi, struct espi_txcmd *cmd)
+{
+ u32 status;
+ int ret;
+
+ /* Wait until HW is ready to send the command */
+ ret = readx_poll_timeout(ioread32, ESPI_BASE + AMD_ESPI_DS_HEADER_REG0,
+ status, (status & BIT(3)) == 0, ESPI_MSG_DELAY_MIN_US,
+ ESPI_RESP_MAX_TIMEOUT_US);
+ if (ret) {
+ dev_err(amd_espi->dev, "eSPI controller is not ready to accept commands\n");
+ amd_espi_cmd_reg_dump(amd_espi->dev, cmd);
+ return ESPI_DNCMD_INT;
+ }
+ amd_espi_clear_status(amd_espi);
+
+ writel(cmd->hdr1.val, (ESPI_BASE + AMD_ESPI_DS_HEADER_REG1));
+ writel(cmd->hdr2.val, (ESPI_BASE + AMD_ESPI_DS_HEADER_REG2));
+
+ amd_espi_send_downstream_data(amd_espi, cmd);
+
+ writel(cmd->hdr0.val, (ESPI_BASE + AMD_ESPI_DS_HEADER_REG0));
+
+ /* Wait until HW successfully sent the packet */
+ ret = readx_poll_timeout(ioread32, ESPI_BASE + AMD_ESPI_DS_HEADER_REG0,
+ status, (status & BIT(3)) == 0, ESPI_MSG_DELAY_MIN_US,
+ ESPI_RESP_MAX_TIMEOUT_US);
+ if (ret) {
+ dev_err(amd_espi->dev, "eSPI timed out waiting for command to complete\n");
+ amd_espi_cmd_reg_dump(amd_espi->dev, cmd);
+ return ESPI_DNCMD_INT;
+ }
+
+ /* Wait for DS command completion interrupt */
+ ret = readx_poll_timeout(ioread32, ESPI_BASE + AMD_ESPI_SLAVE0_INT_STS_REG,
+ status, status != 0, ESPI_MSG_DELAY_MIN_US,
+ ESPI_RESP_MAX_TIMEOUT_US);
+ if (ret) {
+ dev_err(amd_espi->dev, "eSPI command completion interrupt error (status = 0x%x)\n",
+ status);
+ amd_espi_cmd_reg_dump(amd_espi->dev, cmd);
+ return -ETIMEDOUT;
+ }
+
+ ret = amd_espi_check_error_status(amd_espi, status);
+ if (ret != CB_SUCCESS) {
+ amd_espi_cmd_reg_dump(amd_espi->dev, cmd);
+ dev_err(amd_espi->dev, "eSPI status register: 0x%x\n", status);
+ }
+
+ if (ret == ESPI_NO_RESP_INT || ret == ESPI_CRC_ERR_INT) {
+ dev_info(amd_espi->dev, "Triggering Inband-reset after CRC/NO_RESP Error\n");
+ if (amd_espi_inband_reset(amd_espi) != CB_SUCCESS)
+ dev_err(amd_espi->dev, "In-band reset failed!\n");
+ }
+
+ /* Clear downstream command completion interrupt after command completion */
+ writel(ESPI_DNCMD_INT, ESPI_BASE + AMD_ESPI_SLAVE0_INT_STS_REG);
+
+ return ret;
+}
+
+int amd_espi_inband_reset(struct amd_espi *amd_espi)
+{
+ int ret;
+ struct espi_txcmd cmd = {
+ .hdr0 = {
+ .cmd_type = IN_BAND_RESET,
+ .cmd_status = 1,
+ },
+ };
+
+ ret = amd_espi_alloc_cmd_data(&cmd);
+ if (ret)
+ return ret;
+
+ ret = amd_espi_send_cmd(amd_espi, &cmd);
+ if (ret != CB_SUCCESS) {
+ kfree(cmd.data);
+ return ret;
+ }
+
+ ret = amd_espi_set_initial_config(amd_espi);
+
+ kfree(cmd.data);
+ return ret;
+}
+
+int amd_espi_set_iomode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
+ u8 io_mode)
+{
+ struct espi_master *master = amd_espi->master;
+
+ switch (io_mode) {
+ case IO_MODE_QUAD:
+ if (master->caps.io_mode_quad && espi_slave_supports_quad_io(*slave_config)) {
+ *ctrlr_config = ESPI_CNTRL_SET_IO_MODE(*ctrlr_config, IO_MODE_QUAD);
+ *slave_config = ESPI_SLAVE_SET_IO_MODE(*slave_config,
+ ESPI_SLAVE_IO_MODE_SEL_QUAD);
+ break;
+ }
+ dev_info(amd_espi->dev, "eSPI Quad IO not supported. Dropping to Dual mode.\n");
+ fallthrough;
+ case IO_MODE_DUAL:
+ if (master->caps.io_mode_dual && espi_slave_supports_dual_io(*slave_config)) {
+ *ctrlr_config = ESPI_CNTRL_SET_IO_MODE(*ctrlr_config, IO_MODE_DUAL);
+ *slave_config = ESPI_SLAVE_SET_IO_MODE(*slave_config,
+ ESPI_SLAVE_IO_MODE_SEL_DUAL);
+ break;
+ }
+ dev_info(amd_espi->dev, "eSPI Dual IO not supported. Dropping to Single mode.\n");
+ fallthrough;
+ case IO_MODE_SINGLE:
+ default:
+ if (master->caps.io_mode_single && espi_slave_supports_single_io(*slave_config)) {
+ *ctrlr_config = ESPI_CNTRL_SET_IO_MODE(*ctrlr_config, IO_MODE_SINGLE);
+ *slave_config = ESPI_SLAVE_SET_IO_MODE(*slave_config,
+ ESPI_SLAVE_IO_MODE_SEL_SINGLE);
+ } else {
+ dev_err(amd_espi->dev, "%s, eSPI IO mode not supported\n", __func__);
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_set_freqmode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
+ u8 op_freq)
+{
+ struct espi_master *master = amd_espi->master;
+
+ switch (op_freq) {
+ case SLAVE_OP_FREQ_66:
+ if (master->caps.op_freq_66 && espi_slave_supports_66_mhz(*slave_config)) {
+ *ctrlr_config = ESPI_CNTRL_SET_OP_FREQ(*ctrlr_config,
+ CNTRL_SLAVE0_OP_FREQ_66);
+ *slave_config = ESPI_SLAVE_SET_OP_FREQ(*slave_config,
+ ESPI_SLAVE_OP_FREQ_SEL_66_MHZ);
+ break;
+ }
+ dev_info(amd_espi->dev, "eSPI frequency 66 MHz not supported. Dropping to 33MHz.\n");
+ fallthrough;
+ case SLAVE_OP_FREQ_33:
+ if (master->caps.op_freq_33 && ((espi_slave_supports_66_mhz(*slave_config)) ||
+ (espi_slave_supports_33_mhz(*slave_config)))) {
+ *ctrlr_config = ESPI_CNTRL_SET_OP_FREQ(*ctrlr_config,
+ CNTRL_SLAVE0_OP_FREQ_33);
+ *slave_config = ESPI_SLAVE_SET_OP_FREQ(*slave_config,
+ ESPI_SLAVE_OP_FREQ_SEL_33_MHZ);
+ break;
+ }
+ dev_info(amd_espi->dev, "eSPI frequency 33 MHz not supported. Dropping to 16MHz.\n");
+ fallthrough;
+ case SLAVE_OP_FREQ_16:
+ default:
+ if (master->caps.op_freq_16 && ((espi_slave_supports_66_mhz(*slave_config)) ||
+ (espi_slave_supports_33_mhz(*slave_config)) ||
+ (espi_slave_supports_16_mhz(*slave_config)))) {
+ *ctrlr_config = ESPI_CNTRL_SET_OP_FREQ(*ctrlr_config,
+ CNTRL_SLAVE0_OP_FREQ_16);
+ *slave_config = ESPI_SLAVE_SET_OP_FREQ(*slave_config,
+ ESPI_SLAVE_OP_FREQ_SEL_16_MHZ);
+ } else {
+ dev_err(amd_espi->dev, "%s, eSPI frequency mode not supported\n", __func__);
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return CB_SUCCESS;
+}
+
+static int amd_espi_get_config(struct amd_espi *amd_espi, u16 slave_reg_address, u32 *config)
+{
+ int ret;
+ struct espi_txcmd cmd = {
+ .hdr0 = {
+ .cmd_type = GET_CONFIGURATION,
+ .cmd_status = 1,
+ .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_address),
+ .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_address),
+ },
+ };
+
+ ret = amd_espi_alloc_cmd_data(&cmd);
+ if (ret)
+ return ret;
+
+ ret = amd_espi_send_cmd(amd_espi, &cmd);
+ if (ret != CB_SUCCESS) {
+ kfree(cmd.data);
+ return ret;
+ }
+
+ *config = readl(ESPI_BASE + AMD_ESPI_DS_HEADER_REG1);
+
+ kfree(cmd.data);
+ return CB_SUCCESS;
+}
+
+int amd_espi_get_channel_config(struct amd_espi *amd_espi)
+{
+ u32 chnl_config;
+ u32 ret = 0;
+
+ if (amd_espi_get_config(amd_espi, ESPI_SLAVE_PERIPH_CFG, &chnl_config) == CB_SUCCESS) {
+ if (chnl_config & ESPI_SLAVE_CHANNEL_ENABLE)
+ ret |= CHANNEL_MODE_PC;
+ }
+
+ if (amd_espi_get_config(amd_espi, ESPI_SLAVE_VW_CFG, &chnl_config) == CB_SUCCESS) {
+ if (chnl_config & ESPI_SLAVE_CHANNEL_ENABLE)
+ ret |= CHANNEL_MODE_VW;
+ }
+
+ return (ret == 0) ? -EOPNOTSUPP : ret;
+}
+
+int amd_espi_get_general_config(struct amd_espi *amd_espi, u32 *config)
+{
+ return amd_espi_get_config(amd_espi, ESPI_SLAVE_GENERAL_CAPS_CFG, config);
+}
+
+int amd_espi_set_config(struct amd_espi *amd_espi, u32 config, u16 slave_reg_address)
+{
+ int ret;
+ struct espi_txcmd cmd = {
+ .hdr0 = {
+ .cmd_type = SET_CONFIGURATION,
+ .cmd_status = 1,
+ .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_address),
+ .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_address),
+ },
+ .hdr1 = {
+ .val = config,
+ },
+ };
+
+ ret = amd_espi_alloc_cmd_data(&cmd);
+ if (ret)
+ return ret;
+
+ ret = amd_espi_send_cmd(amd_espi, &cmd);
+ kfree(cmd.data);
+
+ return ret;
+}
+
+int amd_espi_set_general_conf(struct amd_espi *amd_espi, struct config *dev)
+{
+ u32 ctrlr_config = readl(ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG);
+ u32 slave_config;
+ int status;
+
+ status = amd_espi_get_general_config(amd_espi, &slave_config);
+ if (status != CB_SUCCESS)
+ return status;
+
+ if (amd_espi->master->caps.alert_mode == 1) {
+ slave_config |= ESPI_SLAVE_ALERT_MODE_PIN;
+ ctrlr_config |= ESPI_CNTRL_SLAVE0_ALERT_MODE;
+ }
+
+ if (amd_espi->master->caps.crc_check_support == 1) {
+ slave_config |= ESPI_SLAVE_CRC_ENABLE;
+ ctrlr_config |= ESPI_CNTRL_SLAVE0_CRC_CHECK_EN;
+ }
+
+ status = amd_espi_set_iomode(amd_espi, &slave_config, &ctrlr_config, dev->io_mode);
+ if (status != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "%s, IO mode not supported\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ status = amd_espi_set_freqmode(amd_espi, &slave_config, &ctrlr_config, dev->op_freq);
+ if (status != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "%s, Operating frequency not supported\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ status = amd_espi_set_config(amd_espi, slave_config, ESPI_SLAVE_GENERAL_CAPS_CFG);
+ if (status != CB_SUCCESS)
+ return status;
+
+ writel(ctrlr_config, (ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG));
+
+ return CB_SUCCESS;
+}
+
+static int amd_espi_wait_channel_ready(struct amd_espi *amd_espi, u32 slave_reg_addr)
+{
+ u32 config;
+ int ret;
+
+ udelay(ESPI_CH_READY_TIMEOUT_US);
+ ret = amd_espi_get_config(amd_espi, slave_reg_addr, &config);
+ if (ret != CB_SUCCESS)
+ return ret;
+
+ if (!!(config & ESPI_SLAVE_CHANNEL_READY)) {
+ ret = CB_SUCCESS;
+ } else {
+ ret = -ETIMEDOUT;
+ dev_err(amd_espi->dev, "Channel is not ready after %d usec (slave addr: 0x%x)\n",
+ ESPI_CH_READY_TIMEOUT_US, slave_reg_addr);
+ }
+
+ return ret;
+}
+
+static void amd_espi_enable_ctrlr_channel(struct amd_espi *amd_espi, u32 channel_en)
+{
+ u32 reg = readl(ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG);
+
+ writel(reg | channel_en, (ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG));
+}
+
+static int amd_espi_set_channel_config(struct amd_espi *amd_espi, u32 slave_config,
+ u32 slave_reg_addr, u32 ctrlr_enable)
+{
+ int ret = amd_espi_set_config(amd_espi, slave_config, slave_reg_addr);
+
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Channel configuration failed\n");
+ return ret;
+ }
+
+ /* Channel already enabled */
+ if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE))
+ return CB_SUCCESS;
+
+ ret = amd_espi_wait_channel_ready(amd_espi, slave_reg_addr);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Channel is not ready\n");
+ return ret;
+ }
+
+ amd_espi_enable_ctrlr_channel(amd_espi, ctrlr_enable);
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_setup_periph_channel(struct amd_espi *amd_espi, u32 slave_caps)
+{
+ /* Peripheral channel requires BME bit to be set when enabling */
+ const u32 slave_en_mask = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE;
+ struct espi_master *master = amd_espi->master;
+ u32 slave_config;
+ int ret;
+
+ ret = amd_espi_get_config(amd_espi, ESPI_SLAVE_PERIPH_CFG, &slave_config);
+ if (ret != CB_SUCCESS)
+ return ret;
+
+ /* Check if PC is already enabled */
+ if (slave_config & ESPI_SLAVE_CHANNEL_ENABLE)
+ return CB_SUCCESS;
+
+ /*
+ * Peripheral channel is the only one which is enabled on reset. So, if the mainboard
+ * wants to disable it, set configuration to disable peripheral channel. It also
+ * requires that BME bit be cleared.
+ */
+ if (master->caps.periph_ch_en) {
+ if (!(slave_caps & ESPI_SLAVE_PERIPH_CH_SUPP)) {
+ dev_err(amd_espi->dev, "eSPI slave doesn't support periph channel!\n");
+ return -EOPNOTSUPP;
+ }
+ slave_config |= slave_en_mask;
+ } else {
+ slave_config &= ~slave_en_mask; /* If master does not support make it to 0 */
+ }
+
+ return amd_espi_set_channel_config(amd_espi, slave_config, ESPI_SLAVE_PERIPH_CFG,
+ CHANNEL_MODE_PC);
+}
+
+int amd_espi_setup_vw_channel(struct amd_espi *amd_espi, u32 slave_caps)
+{
+ struct espi_master *master = amd_espi->master;
+ u32 slave_vw_caps, slave_config;
+ int ret;
+
+ if (!master->caps.vw_ch_en) {
+ dev_err(amd_espi->dev, "Master doesn't support VW channel\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (!(slave_caps & ESPI_SLAVE_VW_CH_SUPP)) {
+ dev_err(amd_espi->dev, "eSPI slave doesn't support VW channel\n");
+ return -EOPNOTSUPP;
+ }
+
+ ret = amd_espi_get_config(amd_espi, ESPI_SLAVE_VW_CFG, &slave_vw_caps);
+ if (ret != CB_SUCCESS)
+ return ret;
+
+ slave_config = slave_vw_caps | ESPI_SLAVE_CHANNEL_ENABLE;
+
+ /* Check if VW channel is already enabled */
+ if (slave_config & ESPI_SLAVE_CHANNEL_ENABLE)
+ return CB_SUCCESS;
+
+ return amd_espi_set_channel_config(amd_espi, slave_config, ESPI_SLAVE_VW_CFG,
+ CHANNEL_MODE_VW);
+}
+
+static int amd_espi_get_master_cap(struct amd_espi *amd_espi, struct espi_master *master)
+{
+ u32 master_cap_reg, info;
+
+ master_cap_reg = readl(ESPI_BASE + AMD_ESPI_MASTER_CAP_REG);
+
+ /* Supported channels by master */
+ if (master_cap_reg & BIT(0))
+ master->caps.flash_ch_en = 1;
+
+ if (master_cap_reg & BIT(1))
+ master->caps.oob_ch_en = 1;
+
+ if (master_cap_reg & BIT(2))
+ master->caps.vw_ch_en = 1;
+
+ if (master_cap_reg & BIT(3))
+ master->caps.periph_ch_en = 1;
+
+ /* eSPI version */
+ master->caps.espi_version = ESPI_GET_ESPI_VERSION(master_cap_reg);
+
+ /* Operating frequency supported by master */
+ info = ESPI_GET_FREQ(master_cap_reg);
+ switch (info) {
+ case CNTRL_OP_FREQ_66:
+ master->caps.op_freq_66 = 1;
+ fallthrough;
+ case CNTRL_OP_FREQ_33:
+ master->caps.op_freq_33 = 1;
+ fallthrough;
+ case CNTRL_OP_FREQ_16:
+ master->caps.op_freq_16 = 1;
+ break;
+ default:
+ dev_err(amd_espi->dev, "%s, operating frequency Error\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ /* IO mode supported by master */
+ info = ESPI_GET_IO_MODE(master_cap_reg);
+ switch (info) {
+ case IO_MODE_QUAD:
+ master->caps.io_mode_quad = 1;
+ fallthrough;
+ case IO_MODE_DUAL:
+ master->caps.io_mode_dual = 1;
+ fallthrough;
+ case IO_MODE_SINGLE:
+ master->caps.io_mode_single = 1;
+ break;
+ default:
+ dev_err(amd_espi->dev, "%s, IO Mode Error\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ /* Number of slaves */
+ master->caps.no_of_slaves = ESPI_GET_NO_OF_SLAVES(master_cap_reg);
+
+ /* PC channel max payload size */
+ master->caps.pc_ch_max_payload_size = ESPI_GET_MAX_PAYLOAD_PC(master_cap_reg);
+
+ /* Flash access channel max payload size */
+ master->caps.flash_ch_max_payload = ESPI_GET_MAX_PAYLOAD_FLASH(master_cap_reg);
+
+ /* OOB message channel maximum payload size */
+ master->caps.oob_ch_max_payload = ESPI_GET_MAX_PAYLOAD_OOB(master_cap_reg);
+
+ /* Maximum virtual wire count */
+ master->caps.vw_ch_max_count = ESPI_GET_MAX_PAYLOAD_VW(master_cap_reg);
+
+ /* Alert mode support by master */
+ master->caps.alert_mode = ESPI_GET_ALERT_MODE(master_cap_reg);
+
+ /* CRC support by master */
+ master->caps.crc_check_support = ESPI_GET_CRC_SUPPORT(master_cap_reg);
+
+ return CB_SUCCESS;
+}
+
+static void amd_espi_set_def_initial_config(struct espi_master *master, struct config *dev_conf)
+{
+ dev_conf->channel_mode = CHANNEL_MODE_PC;
+ dev_conf->io_mode = IO_MODE_SINGLE;
+ dev_conf->op_freq = SLAVE_OP_FREQ_16;
+}
+
+static void amd_espi_control_reg_init(struct amd_espi *amd_espi)
+{
+ u32 espi_version, reg_val;
+
+ /* Clear any existing active bits */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_RX_VW_REG);
+ writel((reg_val | ESPI_RXVW_CLR_MASK), (ESPI_BASE + AMD_ESPI_SLAVE0_RX_VW_REG));
+
+ /* Check eSPI version */
+ espi_version = readl(ESPI_BASE + AMD_ESPI_MASTER_CAP_REG);
+ espi_version = ESPI_GET_ESPI_VERSION(espi_version);
+
+ /*
+ * Watchdog enable and wait state control enable.
+ * Set wait state counter to 0x3F.
+ */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG0);
+ reg_val = reg_val | BIT(0) | BIT(1) |
+ (ESPI_WAIT_STATE_COUNTER << ESPI_WAIT_STATE_COUNTER_SHIFT);
+ writel(reg_val, (ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG0));
+
+ /*
+ * Set slave0 error interrupt enable[19:0]
+ * Register command interrupt enable[31:24]
+ */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_INT_EN_REG);
+ writel(reg_val | ESPI_ALL_ERR_INT | ESPI_ALL_REG_CMD_INT,
+ (ESPI_BASE + AMD_ESPI_SLAVE0_INT_EN_REG));
+
+ /* Set eSPI controller error interrupt mapping, default is SMI (1Fh) */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1);
+ reg_val = ESPI_RGCMD_INT(amd_espi->irq, reg_val) |
+ ESPI_ERR_INT(ESPI_INT_SMI, reg_val);
+ writel(reg_val, (ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1));
+
+ /*
+ * Set the IRQ mask bit and polarity. Unmask IRQ 0~23.
+ * Enable to configure the VW index/data register
+ */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_VW_MISC_CNTRL_REG);
+ reg_val &= ~(GENMASK(31, 8));
+ writel((reg_val | GENMASK(3, 0)), (ESPI_BASE + AMD_ESPI_SLAVE0_VW_MISC_CNTRL_REG));
+
+ /* eSPI bus master enable */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1);
+ if (!(reg_val & ESPI_BUS_MASTER_EN)) {
+ reg_val |= ESPI_BUS_MASTER_EN | BIT(21);
+ writel(reg_val, (ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1));
+ }
+}
+
+static int amd_espi_set_initial_config(struct amd_espi *amd_espi)
+{
+ struct espi_master *master = amd_espi->master;
+ u32 espi_initial_mode, reg_val;
+ struct config espi_dev_conf;
+ int ret;
+
+ /* Clearing all the interrupts */
+ amd_espi_clr_all_intr(amd_espi);
+
+ espi_initial_mode = readl(ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG);
+ espi_initial_mode |= ((CNTRL_SLAVE0_OP_FREQ_16 << ESPI_CNTRL_SLAVE0_FREQ_SHIFT) |
+ (IO_MODE_SINGLE << ESPI_CNTRL_SLAVE0_IO_SHIFT));
+
+ if (amd_espi->master->caps.alert_mode == 1)
+ espi_initial_mode |= ESPI_CNTRL_SLAVE0_ALERT_MODE;
+
+ if (amd_espi->master->caps.crc_check_support == 1)
+ espi_initial_mode |= ESPI_CNTRL_SLAVE0_CRC_CHECK_EN;
+
+ writel(espi_initial_mode, (ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG));
+
+ /* Unmask IRQ 0~23 */
+ reg_val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_VW_MISC_CNTRL_REG);
+ reg_val &= ~(GENMASK(31, 8));
+ writel((reg_val | GENMASK(3, 0)), (ESPI_BASE + AMD_ESPI_SLAVE0_VW_MISC_CNTRL_REG));
+
+ amd_espi_set_def_initial_config(master, &espi_dev_conf);
+
+ ret = amd_espi_set_general_conf(amd_espi, &espi_dev_conf);
+ if (ret != CB_SUCCESS)
+ return ret;
+
+ amd_espi_clr_all_intr(amd_espi);
+
+ return CB_SUCCESS;
+}
+
+static int amd_espi_init_slave(struct amd_espi *amd_espi)
+{
+ struct espi_master *master = amd_espi->master;
+ u32 slave_caps, reg_val;
+ int ret;
+
+ ret = amd_espi_get_master_cap(amd_espi, master);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Get master capability failed\n");
+ return -EOPNOTSUPP;
+ }
+
+ ret = amd_espi_set_initial_config(amd_espi);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "eSPI set initial config failed\n");
+ return ret;
+ }
+
+ ret = amd_espi_inband_reset(amd_espi);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "In-band reset failed!\n");
+ return ret;
+ }
+
+ ret = amd_espi_get_general_config(amd_espi, &slave_caps);
+ if (ret != CB_SUCCESS)
+ return ret;
+
+ reg_val = readl(ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1);
+ writel(reg_val | BIT(20), (ESPI_BASE + AMD_ESPI_GLOBAL_CNTRL_REG1));
+
+ if (amd_espi_setup_periph_channel(amd_espi, slave_caps) != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Peripheral channel setup failed\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (amd_espi_setup_vw_channel(amd_espi, slave_caps) != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Virtual wire channel setup failed\n");
+ return -EOPNOTSUPP;
+ }
+
+ return CB_SUCCESS;
+}
+
+static int amd_espi_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int amd_espi_resume(struct device *dev)
+{
+ struct amd_espi *amd_espi = dev_get_drvdata(dev);
+ int ret;
+
+ ret = amd_espi_set_initial_config(amd_espi);
+ if (ret != CB_SUCCESS)
+ dev_err(amd_espi->dev, "espi_set_initial_config in %s failed!\n", __func__);
+
+ return ret;
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(amd_espi_pm_ops, amd_espi_suspend, amd_espi_resume);
+
+static int amd_espi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct config *espi_dev_conf;
+ struct amd_espi *amd_espi;
+ struct resource *res;
+ int ret;
+
+ amd_espi = devm_kzalloc(dev, sizeof(struct amd_espi), GFP_KERNEL);
+ if (!amd_espi)
+ return -ENOMEM;
+
+ amd_espi->master = devm_kzalloc(dev, sizeof(struct espi_master), GFP_KERNEL);
+ if (!amd_espi->master)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EOPNOTSUPP;
+
+ amd_espi->io_remap_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(amd_espi->io_remap_addr)) {
+ ret = PTR_ERR(amd_espi->io_remap_addr);
+ return dev_err_probe(dev, ret, "ioremap of eSPI registers failed\n");
+ }
+
+ ret = amd_espi_device_create(amd_espi, dev);
+ if (ret != 0)
+ return dev_err_probe(amd_espi->dev, ret, "device creation failed\n");
+
+ platform_set_drvdata(pdev, amd_espi);
+
+ /* Allocate mem for espi_device */
+ espi_dev_conf = devm_kzalloc(dev, sizeof(struct config), GFP_KERNEL);
+ if (!espi_dev_conf) {
+ ret = -ENOMEM;
+ goto espidev_free;
+ }
+
+ amd_espi->irq = platform_get_irq(pdev, 0);
+ if (amd_espi->irq < 0) {
+ ret = amd_espi->irq;
+ goto espidev_free;
+ }
+
+ amd_espi_control_reg_init(amd_espi);
+ ret = amd_espi_init_slave(amd_espi);
+ if (ret != CB_SUCCESS)
+ goto espidev_free;
+
+ dev_info(dev, "AMD ESPI device initialization completed\n");
+
+ return 0;
+
+espidev_free:
+ amd_espi_device_remove(amd_espi);
+ return ret;
+}
+
+static void amd_espi_remove(struct platform_device *pdev)
+{
+ struct amd_espi *amd_espi = platform_get_drvdata(pdev);
+
+ amd_espi_device_remove(amd_espi);
+}
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id espi_acpi_match[] = {
+ { "AMDI0070", AMD_ESPI_V1 },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, espi_acpi_match);
+#endif
+
+static struct platform_driver amd_espi_driver = {
+ .driver = {
+ .name = "amd_espi",
+ .owner = THIS_MODULE,
+ .acpi_match_table = ACPI_PTR(espi_acpi_match),
+ .pm = pm_sleep_ptr(&amd_espi_pm_ops),
+ },
+ .probe = amd_espi_probe,
+ .remove = amd_espi_remove,
+};
+
+module_platform_driver(amd_espi_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("AMD eSPI Controller Driver");
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
new file mode 100644
index 000000000000..4e46c30d3405
--- /dev/null
+++ b/drivers/spi/espi-amd-dev.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD eSPI controller driver - device file operations
+ *
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Authors: Krishnamoorthi M <krishnamoorthi.m@amd.com>
+ * Akshata MukundShetty<akshata.mukundshetty@amd.com>
+ */
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#include "espi-amd.h"
+#include "espi-amd-slave.h"
+
+#define ESPI_DEV_MINORS 0
+#define N_ESPI_MINORS 1
+
+static LIST_HEAD(device_list);
+static DEFINE_MUTEX(device_list_lock);
+
+static struct class *amd_espi_dev_class;
+static struct cdev cdev;
+
+static int amd_espi_open(struct inode *inode, struct file *filp)
+{
+ struct amd_espi *espi;
+ int status = -ENXIO;
+
+ guard(mutex)(&device_list_lock);
+
+ list_for_each_entry(espi, &device_list, device_entry) {
+ if (espi->dev_minor == inode->i_rdev) {
+ status = 0;
+ break;
+ }
+ }
+ if (status)
+ goto err_dev_find;
+
+ espi->users++;
+ filp->private_data = espi;
+ nonseekable_open(inode, filp);
+
+err_dev_find:
+ return status;
+}
+
+static int amd_espi_release(struct inode *inode, struct file *filp)
+{
+ struct amd_espi *espi;
+
+ guard(mutex)(&device_list_lock);
+ espi = filp->private_data;
+ filp->private_data = NULL;
+ espi->users--;
+ if (!espi->users && !espi->dev)
+ kfree(espi);
+
+ return 0;
+}
+
+static const struct file_operations amd_espi_fops = {
+ .owner = THIS_MODULE,
+ .open = amd_espi_open,
+ .release = amd_espi_release,
+};
+
+int amd_espi_device_create(struct amd_espi *amd_espi, struct device *dev)
+{
+ int ret;
+
+ INIT_LIST_HEAD(&amd_espi->device_entry);
+ ret = alloc_chrdev_region(&amd_espi->dev_minor, 0, ESPI_DEV_MINORS, "amd_espi");
+ if (ret < 0) {
+ dev_err(amd_espi->dev, "Device numbers allocation failed: %d\n", ret);
+ return ret;
+ }
+
+ amd_espi_dev_class = class_create("amd_espi");
+ if (IS_ERR(amd_espi_dev_class)) {
+ dev_err(amd_espi->dev, "Class creation failed\n");
+ ret = PTR_ERR(amd_espi_dev_class);
+ goto espi_unregister_chrdev;
+ }
+
+ cdev_init(&cdev, &amd_espi_fops);
+ ret = cdev_add(&cdev, amd_espi->dev_minor, N_ESPI_MINORS);
+ if (ret)
+ goto espi_class_cleanup;
+
+ amd_espi->dev = dev;
+ dev = device_create(amd_espi_dev_class, NULL, amd_espi->dev_minor, &amd_espi, "amd_espi");
+ if (IS_ERR(dev)) {
+ dev_err(amd_espi->dev, "Device creation failed\n");
+ ret = PTR_ERR(dev);
+ goto espi_del_dev;
+ }
+
+ list_add(&amd_espi->device_entry, &device_list);
+
+ return 0;
+
+espi_del_dev:
+ cdev_del(&cdev);
+
+espi_class_cleanup:
+ class_destroy(amd_espi_dev_class);
+
+espi_unregister_chrdev:
+ unregister_chrdev_region(amd_espi->dev_minor, ESPI_DEV_MINORS);
+ return ret;
+}
+
+void amd_espi_device_remove(struct amd_espi *amd_espi)
+{
+ list_del(&amd_espi->device_entry);
+ device_destroy(amd_espi_dev_class, amd_espi->dev_minor);
+ cdev_del(&cdev);
+ class_destroy(amd_espi_dev_class);
+ unregister_chrdev_region(amd_espi->dev_minor, ESPI_DEV_MINORS);
+}
diff --git a/drivers/spi/espi-amd-err.h b/drivers/spi/espi-amd-err.h
new file mode 100644
index 000000000000..d2d3967a3c6d
--- /dev/null
+++ b/drivers/spi/espi-amd-err.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AMD eSPI controller driver error codes
+ *
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Authors: Krishnamoorthi M <krishnamoorthi.m@amd.com>
+ * Akshata MukundShetty<akshata.mukundshetty@amd.com>
+ */
+#ifndef AMD_ESPI_ERROR_H
+#define AMD_ESPI_ERROR_H
+
+/* Error code bit positions */
+#define POS_BUS_TIMING 0
+#define POS_BUS_WAIT_STATE 1
+#define POS_CRC 2
+#define POS_NO_RESP 4
+#define POS_FATAL_ERR 5
+#define POS_NON_FATAL_ERR 6
+#define POS_INVALID_RESP_CODE 7
+#define POS_INVALID_CYCLE_TYPE 8
+#define POS_UNSUCCESS_CPL_RECV 9
+#define POS_ILLEGAL_RESP_TAG 10
+#define POS_ILLEGAL_RESP_LEN 11
+#define POS_OOB_DATA_LEN 12
+#define POS_PC_MSG_DATA 13
+#define POS_FLASH_DATA_LEN 14
+#define POS_PROTOCOL_ERR 15
+
+/* Human-readable error strings */
+static char *espi_error_codes[] = {
+ "ERR 00: eSPI BUS TIMING ERROR",
+ "ERR 01: eSPI WAIT STATE TIMER TIMEOUT",
+ "ERR 02: eSPI CRC ERROR",
+ "",
+ "ERR 04: NO RESPONSE FROM SLAVE",
+ "ERR 05: FATAL_ERROR RESPONSE FROM SLAVE",
+ "ERR 06: NON_FATAL_ERROR RESPONSE FROM SLAVE",
+ "ERR 07: INVALID RESPONSE CODE RECEIVED",
+ "ERR 08: INVALID CYCLE TYPE RECEIVED",
+ "ERR 09: UNSUCCESSFUL COMPLETION PACKET",
+ "ERR 10: ILLEGAL RESPONSE TAG",
+ "ERR 11: ILLEGAL RESPONSE LENGTH",
+ "ERR 12: OOB PACKET DATA LENGTH ERROR",
+ "ERR 13: PC MESSAGE DATA LENGTH ERROR",
+ "ERR 14: FLASH PACKET DATA LENGTH ERROR",
+ "ERR 15: PROTOCOL ERROR",
+};
+#endif
diff --git a/drivers/spi/espi-amd-slave.h b/drivers/spi/espi-amd-slave.h
new file mode 100644
index 000000000000..07aaad4f28aa
--- /dev/null
+++ b/drivers/spi/espi-amd-slave.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AMD eSPI slave device specific macros
+ *
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Authors: Krishnamoorthi M <krishnamoorthi.m@amd.com>
+ * Akshata MukundShetty<akshata.mukundshetty@amd.com>
+ */
+#ifndef AMD_ESPI_SLAVE_H
+#define AMD_ESPI_SLAVE_H
+
+#define ESPI_SLAVE_GENERAL_CAPS_CFG 0x08
+
+/* eSPI slave channel support */
+#define ESPI_SLAVE_PERIPH_CH_SUPP BIT(0)
+#define ESPI_SLAVE_VW_CH_SUPP BIT(1)
+#define ESPI_SLAVE_OOB_CH_SUPP BIT(2)
+#define ESPI_SLAVE_FLASH_CH_SUPP BIT(3)
+
+/* eSPI slave frequency support */
+#define ESPI_SLAVE_OP_FREQ_SUPP_SHIFT 16
+#define ESPI_SLAVE_OP_FREQ_SUPP_MASK GENMASK(18, 16)
+#define ESPI_SLAVE_OP_FREQ_SUPP_VAL(x) ((x) << ESPI_SLAVE_OP_FREQ_SUPP_SHIFT)
+#define ESPI_SLAVE_OP_FREQ_SUPP_16_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(0)
+#define ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(2)
+#define ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(4)
+
+/* eSPI slave frequency selection */
+#define ESPI_SLAVE_OP_FREQ_SEL_SHIFT 20
+#define ESPI_SLAVE_OP_FREQ_SEL_MASK ~GENMASK(22, 20)
+#define ESPI_SLAVE_OP_FREQ_SEL_VAL(x) ((x) << ESPI_SLAVE_OP_FREQ_SEL_SHIFT)
+#define ESPI_SLAVE_OP_FREQ_SEL_16_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(0)
+#define ESPI_SLAVE_OP_FREQ_SEL_33_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(2)
+#define ESPI_SLAVE_OP_FREQ_SEL_66_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(4)
+#define ESPI_SLAVE_SET_OP_FREQ(conf, freq) (((conf) & ESPI_SLAVE_OP_FREQ_SEL_MASK) | (freq))
+
+/* eSPI slave IO mode support */
+#define ESPI_SLAVE_IO_MODE_SUPP_SHIFT 24
+#define ESPI_SLAVE_IO_MODE_SUPP_MASK GENMASK(25, 24)
+#define ESPI_SLAVE_IO_MODE_SUPP_VAL(x) ((x) << ESPI_SLAVE_IO_MODE_SUPP_SHIFT)
+#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_ONLY ESPI_SLAVE_IO_MODE_SUPP_VAL(0)
+#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL ESPI_SLAVE_IO_MODE_SUPP_VAL(1)
+#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD ESPI_SLAVE_IO_MODE_SUPP_VAL(2)
+#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD ESPI_SLAVE_IO_MODE_SUPP_VAL(3)
+
+/* eSPI slave IO mode selection */
+#define ESPI_SLAVE_IO_MODE_SEL_SHIFT 26
+#define ESPI_SLAVE_IO_MODE_SEL_MASK ~GENMASK(27, 26)
+#define ESPI_SLAVE_IO_MODE_SEL_VAL(x) ((x) << ESPI_SLAVE_IO_MODE_SEL_SHIFT)
+#define ESPI_SLAVE_IO_MODE_SEL_SINGLE ESPI_SLAVE_IO_MODE_SEL_VAL(0)
+#define ESPI_SLAVE_IO_MODE_SEL_DUAL ESPI_SLAVE_IO_MODE_SEL_VAL(1)
+#define ESPI_SLAVE_IO_MODE_SEL_QUAD ESPI_SLAVE_IO_MODE_SEL_VAL(2)
+#define ESPI_SLAVE_SET_IO_MODE(conf, mode) (((conf) & ESPI_SLAVE_IO_MODE_SEL_MASK) | (mode))
+
+#define ESPI_SLAVE_ALERT_MODE_PIN BIT(28)
+#define ESPI_SLAVE_CRC_ENABLE BIT(31)
+
+/* eSPI slave channel capabilities and configuration registers */
+#define ESPI_SLAVE_PERIPH_CFG 0x10
+#define ESPI_SLAVE_VW_CFG 0x20
+#define ESPI_SLAVE_OOB_CFG 0x30
+#define ESPI_SLAVE_FLASH_CFG 0x40
+
+#define ESPI_SLAVE_CHANNEL_ENABLE BIT(0)
+#define ESPI_SLAVE_CHANNEL_READY BIT(1)
+#define ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE BIT(2)
+
+static inline bool espi_slave_supports_quad_io(u32 caps)
+{
+ u32 mode = caps & ESPI_SLAVE_IO_MODE_SUPP_MASK;
+
+ return (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD) ||
+ (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD);
+}
+
+static inline bool espi_slave_supports_dual_io(u32 caps)
+{
+ u32 mode = caps & ESPI_SLAVE_IO_MODE_SUPP_MASK;
+
+ return (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL) ||
+ (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD);
+}
+
+static inline bool espi_slave_supports_single_io(u32 caps)
+{
+ /* Single IO mode is supported by default */
+ return true;
+}
+
+static inline bool espi_slave_supports_66_mhz(u32 caps)
+{
+ u32 freq = caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK;
+ return freq == ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ;
+}
+
+static inline bool espi_slave_supports_33_mhz(u32 caps)
+{
+ u32 freq = caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK;
+ return freq == ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ;
+}
+
+static inline bool espi_slave_supports_16_mhz(u32 caps)
+{
+ u32 freq = caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK;
+ return freq == ESPI_SLAVE_OP_FREQ_SUPP_16_MHZ;
+}
+#endif
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
new file mode 100644
index 000000000000..57b156fb0a05
--- /dev/null
+++ b/drivers/spi/espi-amd.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AMD eSPI general macros and structures
+ *
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Authors: Krishnamoorthi M <krishnamoorthi.m@amd.com>
+ * Akshata MukundShetty<akshata.mukundshetty@amd.com>
+ */
+#ifndef AMD_ESPI_H
+#define AMD_ESPI_H
+
+#include <linux/ioctl.h>
+
+#define CB_SUCCESS 0
+#define DATA_SIZE_ROUNDOFF_4(NUM) (((NUM) + 3) & (~0x03u))
+
+/* Timeouts and delay */
+#define ESPI_MSG_DELAY_MIN_US 50
+#define ESPI_RESP_MAX_TIMEOUT_US 200000 /* 200 ms */
+
+/* Downstream transmit registers */
+#define AMD_ESPI_DS_HEADER_REG0 0x00
+#define AMD_ESPI_DS_HEADER_REG1 0x04
+#define AMD_ESPI_DS_HEADER_REG2 0x08
+#define AMD_ESPI_DS_DATA_REG0 0x0C
+
+/* Master capability and control registers */
+#define AMD_ESPI_MASTER_CAP_REG 0x2C
+#define AMD_ESPI_GLOBAL_CNTRL_REG0 0x30
+#define AMD_ESPI_GLOBAL_CNTRL_REG1 0x34
+#define AMD_ESPI_MISC_CNTRL_REG0 0x38
+#define AMD_ESPI_MISC_CNTRL_REG1 0x3c
+
+/* Slave-0 configuration and interrupt registers */
+#define AMD_ESPI_SLAVE0_CONFIG_REG 0x68
+#define AMD_ESPI_SLAVE0_INT_EN_REG 0x6C
+#define AMD_ESPI_SLAVE0_INT_STS_REG 0x70
+#define ESPI_CNTRL_SLAVE0_ALERT_MODE BIT(30)
+#define ESPI_CNTRL_SLAVE0_CRC_CHECK_EN BIT(31)
+
+/* Slave-0 Virtual wire registers */
+#define AMD_ESPI_SLAVE0_RX_VW_REG 0x9C
+#define AMD_ESPI_SLAVE0_VW_MISC_CNTRL_REG 0xA8
+
+/* Slave-0 interrupt enable and status bits */
+#define ESPI_BUS_ERR_INT BIT(0)
+#define ESPI_WAIT_TIMEOUT_INT BIT(1)
+#define ESPI_CRC_ERR_INT BIT(2)
+#define ESPI_NO_RESP_INT BIT(4)
+#define ESPI_FATAL_ERR_INT BIT(5)
+#define ESPI_NON_FATAL_ERR_INT BIT(6)
+#define ESPI_INVALID_RESP_CODE_INT BIT(7)
+#define ESPI_INVALID_CYCLE_TYPE_INT BIT(8)
+#define ESPI_UNSUCCESS_CPL_RECV_INT BIT(9)
+#define ESPI_ILLEGAL_RESP_TAG_INT BIT(10)
+#define ESPI_ILLEGAL_RESP_LEN_INT BIT(11)
+#define ESPI_RX_OOB_OVERFLOW_INT BIT(12)
+#define ESPI_RX_PC_MSG_OVERFLOW_INT BIT(13)
+#define ESPI_RX_FLASH_MSG_OVERFLOW_INT BIT(14)
+#define ESPI_PROTOCOL_ERR_INT BIT(15)
+#define ESPI_DNCMD_INT BIT(28)
+#define ESPI_RXMSG_INT BIT(29)
+#define ESPI_ALL_ERR_INT GENMASK(19, 0)
+#define ESPI_ALL_REG_CMD_INT GENMASK(31, 24)
+
+/* eSPI global control register configurations */
+#define ESPI_BUS_MASTER_EN BIT(1)
+#define ESPI_WAIT_STATE_COUNTER 0x3F
+#define ESPI_WAIT_STATE_COUNTER_SHIFT 23
+#define ESPI_ERR_INT_MAP_SHIFT 8
+#define ESPI_ERR_INT(irq, val) ((u32)(((val) & ~(GENMASK(12, 8))) | \
+ ((irq) << ESPI_ERR_INT_MAP_SHIFT)))
+#define ESPI_INT_SMI 0x1f
+#define ESPI_RGCMD_INT_MAP_SHIFT 13
+#define ESPI_RGCMD_INT(irq, val) ((u32)(((val) & ~(GENMASK(17, 13))) | \
+ ((irq) << ESPI_RGCMD_INT_MAP_SHIFT)))
+#define ESPI_RXVW_CLR_MASK 0xFFFF6F00
+
+/* eSPI master capability register values */
+#define ESPI_GET_ESPI_VERSION(val) (((val) & GENMASK(6, 4)) >> 4)
+#define ESPI_GET_MAX_PAYLOAD_FLASH(val) (((val) & GENMASK(9, 7)) >> 7)
+#define ESPI_GET_MAX_PAYLOAD_OOB(val) (((val) & GENMASK(12, 10)) >> 10)
+#define ESPI_GET_MAX_PAYLOAD_VW(val) (((val) & GENMASK(18, 13)) >> 13)
+#define ESPI_GET_MAX_PAYLOAD_PC(val) (((val) & GENMASK(21, 19)) >> 19)
+#define ESPI_GET_NO_OF_SLAVES(val) (((val) & GENMASK(24, 22)) >> 22)
+#define ESPI_GET_FREQ(val) (((val) & GENMASK(27, 25)) >> 25)
+#define ESPI_GET_IO_MODE(val) (((val) & GENMASK(29, 28)) >> 28)
+#define ESPI_GET_ALERT_MODE(val) (((val) & BIT(30)) >> 30)
+#define ESPI_GET_CRC_SUPPORT(val) (((val) & BIT(31)) >> 31)
+
+/* Channel modes */
+#define CHANNEL_MODE_FLASH BIT(0)
+#define CHANNEL_MODE_OOB BIT(1)
+#define CHANNEL_MODE_VW BIT(2)
+#define CHANNEL_MODE_PC BIT(3)
+#define CHAN_NOT_ENABLED BIT(4)
+
+/*
+ * Controller IO MODE encoding values
+ * 00 - Single I/O
+ * 01 - Dual I/O, Single I/O
+ * 10 - Quad I/O, Dual I/O, Single I/O
+ */
+#define IO_MODE_SINGLE 0x0
+#define IO_MODE_DUAL 0x1
+#define IO_MODE_QUAD 0x2
+#define ESPI_CNTRL_SLAVE0_IO_SHIFT 28
+#define ESPI_CNTRL_IO_MODE_MASK ~GENMASK(29, 28)
+#define ESPI_CNTRL_SET_IO_MODE(conf, mode) (((conf) & ESPI_CNTRL_IO_MODE_MASK) |\
+ ((mode) << ESPI_CNTRL_SLAVE0_IO_SHIFT))
+
+/*
+ * Controller operating support frequency values
+ * 000 - 16.7 MHz
+ * 001 - 16.7 MHz, 33 MHz
+ * 011 - 16.7 MHz, 33 MHz, 66 MHz
+ */
+#define CNTRL_OP_FREQ_16 0x0
+#define CNTRL_OP_FREQ_33 0x1
+#define CNTRL_OP_FREQ_66 0x3
+
+/* Slave0 operating frequency values */
+#define SLAVE_OP_FREQ_16 0x0
+#define SLAVE_OP_FREQ_33 0x2
+#define SLAVE_OP_FREQ_66 0x4
+
+/* Slave0 operating frequency values in controller side */
+#define CNTRL_SLAVE0_OP_FREQ_16 0x0
+#define CNTRL_SLAVE0_OP_FREQ_33 0x1
+#define CNTRL_SLAVE0_OP_FREQ_66 0x2
+
+#define ESPI_CNTRL_SLAVE0_FREQ_SHIFT 25
+#define ESPI_CNTRL_OP_MODE_MASK ~GENMASK(27, 25)
+#define ESPI_CNTRL_SET_OP_FREQ(conf, freq) (((conf) & ESPI_CNTRL_OP_MODE_MASK) |\
+ ((freq) << ESPI_CNTRL_SLAVE0_FREQ_SHIFT))
+
+#define ESPI_BASE ((u8 __iomem *)amd_espi->io_remap_addr)
+
+/*
+ * enum amd_espi_versions - eSPI controller versions
+ * @AMD_ESPI_V1: AMDI0070 hardware version
+ */
+enum amd_espi_versions {
+ AMD_ESPI_V1 = 1,
+};
+
+/* eSPI commands */
+enum espi_cmd_type {
+ SET_CONFIGURATION,
+ GET_CONFIGURATION,
+ IN_BAND_RESET,
+ PERIPHERAL_CHNL = 4,
+ VW_CHNL,
+ OOB_CHNL,
+ FLASH_CHNL,
+};
+
+struct amd_espi {
+ void __iomem *io_remap_addr;
+ struct device *dev;
+ struct espi_master *master;
+ struct list_head device_entry;
+ dev_t dev_minor;
+ enum amd_espi_versions version;
+ unsigned int users;
+ int irq;
+ void (*suspend)(struct amd_espi *amd_espi);
+ void (*resume)(struct amd_espi *amd_espi);
+};
+
+struct master_caps {
+ /* Channel support by master, bits [3:0] */
+ u32 periph_ch_en:1;
+ u32 vw_ch_en:1;
+ u32 oob_ch_en:1;
+ u32 flash_ch_en:1;
+
+ /* eSPI version, bits [6:4] */
+ u32 espi_version:3;
+
+ /* Flash access channel max supported payload, bits[9:7] */
+ u32 flash_ch_max_payload:3;
+
+ /* OOB message channel max supported payload, bits[10:12] */
+ u32 oob_ch_max_payload:3;
+
+ /* Operating maximum virtual wire count, bits[18:13] */
+ u32 vw_ch_max_count:6;
+
+ /* Peripheral channel max supported payload, bits[21:19] */
+ u32 pc_ch_max_payload_size:3;
+
+ /* Number of slaves supported by master bits, [24:22] */
+ u32 no_of_slaves:3;
+
+ /* Operating frequencies, bits [27:25] */
+ u32 op_freq_66:1;
+ u32 op_freq_33:1;
+ u32 op_freq_16:1;
+
+ /* IO modes bits [29:28] */
+ u32 io_mode_single:1;
+ u32 io_mode_dual:1;
+ u32 io_mode_quad:1;
+
+ /* Alert mode support by master, bit[30] */
+ u32 alert_mode:1;
+
+ /* CRC checking support by master, bit[31] */
+ u32 crc_check_support:1;
+} __packed;
+
+struct espi_master {
+ struct device *dev;
+ struct master_caps caps;
+};
+
+struct config {
+ u8 io_mode;
+ u8 channel_mode;
+ u8 op_freq;
+};
+
+/* TX Header and data packet */
+union espi_txhdr0 {
+ u32 val;
+ struct {
+ u32 cmd_type:3;
+ u32 cmd_status:1;
+ u32 slave_sel:2;
+ u32 rsvd:2;
+ u32 hdata0:8;
+ u32 hdata1:8;
+ u32 hdata2:8;
+ };
+};
+
+union espi_txhdr1 {
+ u32 val;
+ struct {
+ u32 hdata3:8;
+ u32 hdata4:8;
+ u32 hdata5:8;
+ u32 hdata6:8;
+ };
+};
+
+union espi_txhdr2 {
+ u32 val;
+ struct {
+ u32 hdata7:8;
+ u32 rsvd:24;
+ };
+};
+
+union espi_txdata {
+ u32 val;
+ struct {
+ u32 dbyte0:8;
+ u32 dbyte1:8;
+ u32 dbyte2:8;
+ u32 dbyte3:8;
+ };
+};
+
+struct espi_txcmd {
+ union espi_txhdr0 hdr0;
+ union espi_txhdr1 hdr1;
+ union espi_txhdr2 hdr2;
+ union espi_txdata *data;
+ u32 expected_status_codes;
+};
+
+/* Function prototypes */
+int amd_espi_device_create(struct amd_espi *amd_espi, struct device *dev);
+void amd_espi_device_remove(struct amd_espi *amd_espi);
+int amd_espi_inband_reset(struct amd_espi *amd_espi);
+int amd_espi_get_general_config(struct amd_espi *amd_espi, u32 *config);
+int amd_espi_set_general_conf(struct amd_espi *amd_espi, struct config *dev);
+int amd_espi_set_config(struct amd_espi *amd_espi, u32 config, u16 slave_reg_address);
+int amd_espi_set_iomode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
+ u8 io_mode);
+int amd_espi_set_freqmode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
+ u8 op_freq);
+int amd_espi_get_channel_config(struct amd_espi *amd_espi);
+int amd_espi_setup_periph_channel(struct amd_espi *amd_espi, u32 slave_caps);
+int amd_espi_setup_vw_channel(struct amd_espi *amd_espi, u32 slave_caps);
+void amd_espi_clr_all_intr(struct amd_espi *amd_espi);
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support
2025-03-13 18:34 ` [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support Raju Rangoju
@ 2025-03-17 14:06 ` Mark Brown
2025-03-26 10:00 ` Rangoju, Raju
0 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2025-03-17 14:06 UTC (permalink / raw)
To: Raju Rangoju
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
[-- Attachment #1: Type: text/plain, Size: 3655 bytes --]
On Fri, Mar 14, 2025 at 12:04:31AM +0530, Raju Rangoju wrote:
> @@ -159,6 +159,8 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
> obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
> obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
> obj-$(CONFIG_SPI_AMD) += spi-amd.o
> +obj-$(CONFIG_SPI_AMD_ESPI) += espi-amd.o
> +espi-amd-objs := espi-amd-core.o espi-amd-dev.o
>
Please keep these files sorted.
> @@ -0,0 +1,883 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * AMD eSPI controller driver
Please make the entire comment block a C++ one to make things look more
consistent.
> + *
> + * Copyright (c) 2025, Advanced Micro Devices, Inc.
> + * All Rights Reserved.
Are you sure?
> +static int amd_espi_check_error_status(struct amd_espi *amd_espi, u32 status)
> +{
> + int ret = CB_SUCCESS;
> +
> + if (!(status & ESPI_DNCMD_INT)) {
> + ret = ESPI_DNCMD_INT;
> + dev_err(amd_espi->dev, "eSPI downstream command completion failure\n");
> + } else if (status & ESPI_BUS_ERR_INT) {
> + ret = ESPI_BUS_ERR_INT;
> + dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_BUS_TIMING]);
Can we really only have one error flagged at once? The whole
espi_error_codes thing also seems like unneeded complexity and fagility,
this function is the only place they're used and there's nothing
ensuring that the defines for indexing into the array have anything to
do with the strings in there.
> +int amd_espi_set_iomode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
> + u8 io_mode)
> +{
> + struct espi_master *master = amd_espi->master;
There's a lot of outdated terminology like this in the driver - while
sometimes it's unavoidable due to the register map it's better to use
more modern terms like controller and device when it's just pure
software things.
> + ret = amd_espi_get_config(amd_espi, ESPI_SLAVE_PERIPH_CFG, &slave_config);
> + if (ret != CB_SUCCESS)
> + return ret;
> +
> + /* Check if PC is already enabled */
> + if (slave_config & ESPI_SLAVE_CHANNEL_ENABLE)
> + return CB_SUCCESS;
Is there any great reason to use these non-standard CB_ return codes?
> +static int amd_espi_suspend(struct device *dev)
> +{
> + return 0;
> +}
Remove empty functions, if they can safely be empty the functions will
be optional.
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EOPNOTSUPP;
> +
> + amd_espi->io_remap_addr = devm_ioremap_resource(dev, res);
dev_platform_get_and_ioremap_resource().
> + amd_espi_control_reg_init(amd_espi);
> + ret = amd_espi_init_slave(amd_espi);
> + if (ret != CB_SUCCESS)
> + goto espidev_free;
> +
> + dev_info(dev, "AMD ESPI device initialization completed\n");
This is just noise, remove it.
> +
> + return 0;
> +
> +espidev_free:
> + amd_espi_device_remove(amd_espi);
> + return ret;
This will return your non-standard error codes to generic code.
> +static void amd_espi_remove(struct platform_device *pdev)
> +{
> + struct amd_espi *amd_espi = platform_get_drvdata(pdev);
> +
> + amd_espi_device_remove(amd_espi);
> +}
There's no need for this wrapper function, there's exactly one place we
can call remove from.
> +static int amd_espi_open(struct inode *inode, struct file *filp)
> +{
> + struct amd_espi *espi;
> + int status = -ENXIO;
> +
> + guard(mutex)(&device_list_lock);
Whatever this userspace ABI is for it should be added in a separate
patch, most likely it shouldn't be here at all and standard interfaces
should be used. Currently it doesn't seem to actually do anything.
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support
2025-03-17 14:06 ` Mark Brown
@ 2025-03-26 10:00 ` Rangoju, Raju
0 siblings, 0 replies; 21+ messages in thread
From: Rangoju, Raju @ 2025-03-26 10:00 UTC (permalink / raw)
To: Mark Brown
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
On 3/17/2025 7:36 PM, Mark Brown wrote:
> On Fri, Mar 14, 2025 at 12:04:31AM +0530, Raju Rangoju wrote:
>
>> @@ -159,6 +159,8 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
>> obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
>> obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
>> obj-$(CONFIG_SPI_AMD) += spi-amd.o
>> +obj-$(CONFIG_SPI_AMD_ESPI) += espi-amd.o
>> +espi-amd-objs := espi-amd-core.o espi-amd-dev.o
>>
>
> Please keep these files sorted.
Sure Mark, we will address this in V2.
>
>> @@ -0,0 +1,883 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * AMD eSPI controller driver
>
> Please make the entire comment block a C++ one to make things look more
> consistent.
Will address in V2.
>
>> + *
>> + * Copyright (c) 2025, Advanced Micro Devices, Inc.
>> + * All Rights Reserved.
>
> Are you sure?
>
Yes, we've used the same copyright text in other AMD drivers/files.
>> +static int amd_espi_check_error_status(struct amd_espi *amd_espi, u32 status)
>> +{
>> + int ret = CB_SUCCESS;
>> +
>> + if (!(status & ESPI_DNCMD_INT)) {
>> + ret = ESPI_DNCMD_INT;
>> + dev_err(amd_espi->dev, "eSPI downstream command completion failure\n");
>> + } else if (status & ESPI_BUS_ERR_INT) {
>> + ret = ESPI_BUS_ERR_INT;
>> + dev_err(amd_espi->dev, "%s\n", espi_error_codes[POS_BUS_TIMING]);
>
> Can we really only have one error flagged at once? The whole
> espi_error_codes thing also seems like unneeded complexity and fagility,
> this function is the only place they're used and there's nothing
> ensuring that the defines for indexing into the array have anything to
> do with the strings in there.
The purpose of maintaining error codes is to inform the user space
application about the reason for the command failure. The user space
application can then use these error codes to determine the cause of the
command failure.
>
>> +int amd_espi_set_iomode(struct amd_espi *amd_espi, u32 *slave_config, u32 *ctrlr_config,
>> + u8 io_mode)
>> +{
>> + struct espi_master *master = amd_espi->master;
>
> There's a lot of outdated terminology like this in the driver - while
> sometimes it's unavoidable due to the register map it's better to use
> more modern terms like controller and device when it's just pure
> software things.
Will address in V2.
>
>> + ret = amd_espi_get_config(amd_espi, ESPI_SLAVE_PERIPH_CFG, &slave_config);
>> + if (ret != CB_SUCCESS)
>> + return ret;
>> +
>> + /* Check if PC is already enabled */
>> + if (slave_config & ESPI_SLAVE_CHANNEL_ENABLE)
>> + return CB_SUCCESS;
>
> Is there any great reason to use these non-standard CB_ return codes?
Sure, will address in V2.
>
>> +static int amd_espi_suspend(struct device *dev)
>> +{
>> + return 0;
>> +}
>
> Remove empty functions, if they can safely be empty the functions will
> be optional.
>
Will address in V2.
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res)
>> + return -EOPNOTSUPP;
>> +
>> + amd_espi->io_remap_addr = devm_ioremap_resource(dev, res);
>
> dev_platform_get_and_ioremap_resource().
Will address in V2.
>
>> + amd_espi_control_reg_init(amd_espi);
>> + ret = amd_espi_init_slave(amd_espi);
>> + if (ret != CB_SUCCESS)
>> + goto espidev_free;
>> +
>> + dev_info(dev, "AMD ESPI device initialization completed\n");
>
> This is just noise, remove it.
Sure
>
>> +
>> + return 0;
>> +
>> +espidev_free:
>> + amd_espi_device_remove(amd_espi);
>> + return ret;
>
> This will return your non-standard error codes to generic code.
Will address in V2
>
>> +static void amd_espi_remove(struct platform_device *pdev)
>> +{
>> + struct amd_espi *amd_espi = platform_get_drvdata(pdev);
>> +
>> + amd_espi_device_remove(amd_espi);
>> +}
>
> There's no need for this wrapper function, there's exactly one place we
> can call remove from.
>
We have moved all device-related operations to a common file espi-amd-dev.c.
Therefore, the device remove callback is invoked from the driver remove
function during un-initialization.
>> +static int amd_espi_open(struct inode *inode, struct file *filp)
>> +{
>> + struct amd_espi *espi;
>> + int status = -ENXIO;
>> +
>> + guard(mutex)(&device_list_lock);
>
> Whatever this userspace ABI is for it should be added in a separate
> patch, most likely it shouldn't be here at all and standard interfaces
> should be used. Currently it doesn't seem to actually do anything.
Since we are not registering the driver with spi framework and going
with char dev file for user interface, all the dependent functions
required including open, close and ioctls for char dev are placed in
this file.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
2025-03-13 18:34 ` [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-17 14:07 ` Mark Brown
2025-03-13 18:34 ` [PATCH 03/10] spi: espi_amd: Add eSPI get " Raju Rangoju
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch introduces an IOCTL command to set the configuration of the
eSPI controller and eSPI slave0. The configuration options include
parameters like frequency, channel, and IO mode. The new IOCTL command
allow users to dynamically configure the eSPI controller and slave.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 94 ++++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd.h | 4 ++
2 files changed, 98 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 4e46c30d3405..5f25ad2b1eef 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -28,6 +28,99 @@ static DEFINE_MUTEX(device_list_lock);
static struct class *amd_espi_dev_class;
static struct cdev cdev;
+static int amd_espi_ioctl_set_conf(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct config *dev_conf, *config;
+ u32 slave_config;
+ int ret;
+
+ dev_conf = kzalloc(sizeof(*dev_conf), GFP_KERNEL);
+ if (!dev_conf)
+ return -ENOMEM;
+
+ config = kzalloc(sizeof(*config), GFP_KERNEL);
+ if (!config) {
+ kfree(dev_conf);
+ return -ENOMEM;
+ }
+
+ if (copy_from_user(config, (void __user *)arg, sizeof(struct config))) {
+ ret = -EFAULT;
+ goto set_config_free;
+ }
+
+ /* IO mode configuration */
+ if (config->io_mode != IO_MODE_SINGLE && config->io_mode != IO_MODE_DUAL &&
+ config->io_mode != IO_MODE_QUAD) {
+ dev_err(amd_espi->dev, "Invalid IO mode\n");
+ ret = -EOPNOTSUPP;
+ goto set_config_free;
+ } else {
+ dev_conf->io_mode = config->io_mode;
+ }
+
+ /* Set operating frequency configuration */
+ if (config->op_freq != SLAVE_OP_FREQ_16 && config->op_freq != SLAVE_OP_FREQ_33 &&
+ config->op_freq != SLAVE_OP_FREQ_66) {
+ dev_err(amd_espi->dev, "Invalid operating frequency\n");
+ ret = -EOPNOTSUPP;
+ goto set_config_free;
+ } else {
+ dev_conf->op_freq = config->op_freq;
+ }
+
+ ret = amd_espi_set_general_conf(amd_espi, dev_conf);
+ if (ret != CB_SUCCESS)
+ goto set_config_free;
+
+ /* Set channel configuration */
+ ret = amd_espi_get_general_config(amd_espi, &slave_config);
+ if (ret != CB_SUCCESS)
+ goto set_config_free;
+
+ if (config->channel_mode == CHANNEL_MODE_PC) {
+ ret = amd_espi_setup_periph_channel(amd_espi, slave_config);
+ if (ret) {
+ dev_err(amd_espi->dev, "Peripheral channel setup failed\n");
+ goto set_config_free;
+ }
+ } else if (config->channel_mode == CHANNEL_MODE_VW) {
+ ret = amd_espi_setup_vw_channel(amd_espi, slave_config);
+ if (ret) {
+ dev_err(amd_espi->dev, "Virtual wire channel setup failed\n");
+ goto set_config_free;
+ }
+ } else {
+ ret = -EOPNOTSUPP;
+ }
+
+set_config_free:
+ kfree(dev_conf);
+ kfree(config);
+ return ret;
+}
+
+static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct amd_espi *amd_espi = filp->private_data;
+ int ret = 0;
+
+ /* Check type and command number */
+ if (_IOC_TYPE(cmd) != ESPI_MAGIC_NUMBER)
+ return -EINVAL;
+
+ switch (cmd) {
+ case ESPI_SET_CONFIG:
+ ret = amd_espi_ioctl_set_conf(amd_espi, arg);
+ break;
+ default:
+ dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
static int amd_espi_open(struct inode *inode, struct file *filp)
{
struct amd_espi *espi;
@@ -68,6 +161,7 @@ static int amd_espi_release(struct inode *inode, struct file *filp)
static const struct file_operations amd_espi_fops = {
.owner = THIS_MODULE,
+ .unlocked_ioctl = amd_espi_ioctl,
.open = amd_espi_open,
.release = amd_espi_release,
};
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index 57b156fb0a05..1de53426059b 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -138,6 +138,10 @@
#define ESPI_BASE ((u8 __iomem *)amd_espi->io_remap_addr)
+/* IOCTL calls */
+#define ESPI_MAGIC_NUMBER 'i'
+#define ESPI_SET_CONFIG _IOW(ESPI_MAGIC_NUMBER, 0x1, struct config)
+
/*
* enum amd_espi_versions - eSPI controller versions
* @AMD_ESPI_V1: AMDI0070 hardware version
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command
2025-03-13 18:34 ` [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command Raju Rangoju
@ 2025-03-17 14:07 ` Mark Brown
2025-03-26 10:03 ` Rangoju, Raju
0 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2025-03-17 14:07 UTC (permalink / raw)
To: Raju Rangoju
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
[-- Attachment #1: Type: text/plain, Size: 373 bytes --]
On Fri, Mar 14, 2025 at 12:04:32AM +0530, Raju Rangoju wrote:
> This patch introduces an IOCTL command to set the configuration of the
> eSPI controller and eSPI slave0. The configuration options include
> parameters like frequency, channel, and IO mode. The new IOCTL command
> allow users to dynamically configure the eSPI controller and slave.
Why? We have spidev...
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command
2025-03-17 14:07 ` Mark Brown
@ 2025-03-26 10:03 ` Rangoju, Raju
0 siblings, 0 replies; 21+ messages in thread
From: Rangoju, Raju @ 2025-03-26 10:03 UTC (permalink / raw)
To: Mark Brown
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
On 3/17/2025 7:37 PM, Mark Brown wrote:
> On Fri, Mar 14, 2025 at 12:04:32AM +0530, Raju Rangoju wrote:
>
>> This patch introduces an IOCTL command to set the configuration of the
>> eSPI controller and eSPI slave0. The configuration options include
>> parameters like frequency, channel, and IO mode. The new IOCTL command
>> allow users to dynamically configure the eSPI controller and slave.
>
> Why? We have spidev...
There is no support from the slave device side to register as an SPI
slave device with the SPI framework and provide SPI communication.
For this reason, the AMD eSPI driver can only handle device
initialization itself and provide a character device file as an
interface to user space.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 03/10] spi: espi_amd: Add eSPI get config IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
2025-03-13 18:34 ` [PATCH 01/10] spi: espi_amd: Add AMD eSPI controller driver support Raju Rangoju
2025-03-13 18:34 ` [PATCH 02/10] spi: espi_amd: Add eSPI set config IOCTL command Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 04/10] spi: espi_amd: Add eSPI inband-reset " Raju Rangoju
` (7 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch introduces an IOCTL command to retrieve the configuration of
the eSPI controller and eSPI slave0. The configuration parameters include
the frequency, channel, and IO mode.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 69 ++++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd.h | 1 +
2 files changed, 70 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 5f25ad2b1eef..79224f4f86fa 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -100,6 +100,72 @@ static int amd_espi_ioctl_set_conf(struct amd_espi *amd_espi, unsigned long arg)
return ret;
}
+static int amd_espi_ioctl_get_conf(struct amd_espi *amd_espi, unsigned long arg)
+{
+ u32 op_freq, io_mode, slave_conf;
+ struct config *config;
+ int ret;
+
+ config = kzalloc(sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ ret = amd_espi_get_general_config(amd_espi, &slave_conf);
+ if (ret != CB_SUCCESS)
+ goto get_config_free;
+
+ /* Get IO mode configuration */
+ io_mode = (slave_conf & GENMASK(27, 26)) >> ESPI_SLAVE_IO_MODE_SEL_SHIFT;
+ switch (io_mode) {
+ case IO_MODE_SINGLE:
+ case IO_MODE_DUAL:
+ case IO_MODE_QUAD:
+ config->io_mode = io_mode;
+ break;
+ default:
+ dev_err(amd_espi->dev, "Invalid IO mode\n");
+ ret = -EOPNOTSUPP;
+ goto get_config_free;
+ }
+
+ /* Get operating frequency configuration */
+ op_freq = (slave_conf & GENMASK(22, 20)) >> ESPI_SLAVE_OP_FREQ_SEL_SHIFT;
+ switch (op_freq) {
+ case SLAVE_OP_FREQ_16:
+ case SLAVE_OP_FREQ_33:
+ case SLAVE_OP_FREQ_66:
+ config->op_freq = op_freq;
+ break;
+ default:
+ dev_err(amd_espi->dev, "Invalid operating frequency\n");
+ ret = -EOPNOTSUPP;
+ goto get_config_free;
+ }
+
+ /* Get channel configuration */
+ ret = amd_espi_get_channel_config(amd_espi);
+ config->channel_mode = 0;
+
+ if (ret == -EOPNOTSUPP) {
+ config->channel_mode = CHAN_NOT_ENABLED;
+ } else {
+ if (ret & CHANNEL_MODE_PC)
+ config->channel_mode |= CHANNEL_MODE_PC;
+ if (ret & CHANNEL_MODE_VW)
+ config->channel_mode |= CHANNEL_MODE_VW;
+ }
+
+ if (copy_to_user((void __user *)arg, config, sizeof(struct config))) {
+ ret = -EFAULT;
+ goto get_config_free;
+ }
+ ret = 0;
+
+get_config_free:
+ kfree(config);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -113,6 +179,9 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_SET_CONFIG:
ret = amd_espi_ioctl_set_conf(amd_espi, arg);
break;
+ case ESPI_GET_CONFIG:
+ ret = amd_espi_ioctl_get_conf(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index 1de53426059b..bc15f7417c37 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -141,6 +141,7 @@
/* IOCTL calls */
#define ESPI_MAGIC_NUMBER 'i'
#define ESPI_SET_CONFIG _IOW(ESPI_MAGIC_NUMBER, 0x1, struct config)
+#define ESPI_GET_CONFIG _IOR(ESPI_MAGIC_NUMBER, 0x2, struct config)
/*
* enum amd_espi_versions - eSPI controller versions
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 04/10] spi: espi_amd: Add eSPI inband-reset IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (2 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 03/10] spi: espi_amd: Add eSPI get " Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 05/10] spi: espi_amd: Add eSPI set IO mode " Raju Rangoju
` (6 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch adds support for a channel-independent IOCTL command to
dynamically reset the configuration settings of the eSPI controller.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 5 +++++
drivers/spi/espi-amd.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 79224f4f86fa..ba2becdec8e6 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -182,6 +182,11 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_GET_CONFIG:
ret = amd_espi_ioctl_get_conf(amd_espi, arg);
break;
+ case ESPI_INBAND_RESET:
+ ret = amd_espi_inband_reset(amd_espi);
+ if (ret != CB_SUCCESS)
+ dev_err(amd_espi->dev, "In-band reset failed!\n");
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index bc15f7417c37..3c6e9b92c08d 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -142,6 +142,7 @@
#define ESPI_MAGIC_NUMBER 'i'
#define ESPI_SET_CONFIG _IOW(ESPI_MAGIC_NUMBER, 0x1, struct config)
#define ESPI_GET_CONFIG _IOR(ESPI_MAGIC_NUMBER, 0x2, struct config)
+#define ESPI_INBAND_RESET _IO(ESPI_MAGIC_NUMBER, 0x3)
/*
* enum amd_espi_versions - eSPI controller versions
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 05/10] spi: espi_amd: Add eSPI set IO mode IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (3 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 04/10] spi: espi_amd: Add eSPI inband-reset " Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 06/10] spi: espi_amd: Add eSPI set channel " Raju Rangoju
` (5 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch introduces an IOCTL command to allow users to dynamically
configure the supported IO modes such as single, dual and quad modes.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 40 ++++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index ba2becdec8e6..821cc0486657 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -166,6 +166,43 @@ static int amd_espi_ioctl_get_conf(struct amd_espi *amd_espi, unsigned long arg)
return ret;
}
+static int amd_espi_ioctl_set_io_mode(struct amd_espi *amd_espi, unsigned long arg)
+{
+ u32 ctrlr_config, slave_config;
+ struct config *config;
+ int ret;
+
+ config = kzalloc(sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ if (copy_from_user(config, (void __user *)arg, sizeof(struct config))) {
+ ret = -EFAULT;
+ goto set_io_mode_free;
+ }
+
+ ctrlr_config = readl(ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG);
+
+ ret = amd_espi_get_general_config(amd_espi, &slave_config);
+ if (ret != CB_SUCCESS)
+ goto set_io_mode_free;
+
+ ret = amd_espi_set_iomode(amd_espi, &slave_config, &ctrlr_config, config->io_mode);
+ if (ret != CB_SUCCESS)
+ goto set_io_mode_free;
+
+ ret = amd_espi_set_config(amd_espi, slave_config, ESPI_SLAVE_GENERAL_CAPS_CFG);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Set IO mode failed\n");
+ goto set_io_mode_free;
+ }
+ writel(ctrlr_config, (ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG));
+
+set_io_mode_free:
+ kfree(config);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -187,6 +224,9 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
if (ret != CB_SUCCESS)
dev_err(amd_espi->dev, "In-band reset failed!\n");
break;
+ case ESPI_SET_IO_MODE:
+ ret = amd_espi_ioctl_set_io_mode(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index 3c6e9b92c08d..f1185f877a05 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -143,6 +143,7 @@
#define ESPI_SET_CONFIG _IOW(ESPI_MAGIC_NUMBER, 0x1, struct config)
#define ESPI_GET_CONFIG _IOR(ESPI_MAGIC_NUMBER, 0x2, struct config)
#define ESPI_INBAND_RESET _IO(ESPI_MAGIC_NUMBER, 0x3)
+#define ESPI_SET_IO_MODE _IOW(ESPI_MAGIC_NUMBER, 0x4, struct config)
/*
* enum amd_espi_versions - eSPI controller versions
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 06/10] spi: espi_amd: Add eSPI set channel IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (4 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 05/10] spi: espi_amd: Add eSPI set IO mode " Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 07/10] spi: espi_amd: Add eSPI set frequency " Raju Rangoju
` (4 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch introduces support for a new IOCTL command to set the channel
of eSPI controller. Currently espi_amd driver supports to enable
peripheral and virtual wire channels.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 49 ++++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd.h | 1 +
2 files changed, 50 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 821cc0486657..c78a9b2b059b 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -203,6 +203,52 @@ static int amd_espi_ioctl_set_io_mode(struct amd_espi *amd_espi, unsigned long a
return ret;
}
+static int amd_espi_ioctl_set_channel_mode(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct config *config;
+ u32 slave_config;
+ int ret;
+
+ config = kzalloc(sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ if (copy_from_user(config, (void __user *)arg, sizeof(struct config))) {
+ ret = -EFAULT;
+ goto set_chan_mode_free;
+ }
+
+ ret = amd_espi_get_general_config(amd_espi, &slave_config);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Get configuration failed\n");
+ goto set_chan_mode_free;
+ }
+
+ switch (config->channel_mode) {
+ case CHANNEL_MODE_PC:
+ ret = amd_espi_setup_periph_channel(amd_espi, slave_config);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Setup peripheral channel failed\n");
+ goto set_chan_mode_free;
+ }
+ break;
+ case CHANNEL_MODE_VW:
+ ret = amd_espi_setup_vw_channel(amd_espi, slave_config);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Setup virtual wire channel failed\n");
+ goto set_chan_mode_free;
+ }
+ break;
+ default:
+ dev_err(amd_espi->dev, "Channel: not supported\n");
+ ret = -EOPNOTSUPP;
+ }
+
+set_chan_mode_free:
+ kfree(config);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -227,6 +273,9 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_SET_IO_MODE:
ret = amd_espi_ioctl_set_io_mode(amd_espi, arg);
break;
+ case ESPI_SET_CHAN_MODE:
+ ret = amd_espi_ioctl_set_channel_mode(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index f1185f877a05..3774918d994f 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -144,6 +144,7 @@
#define ESPI_GET_CONFIG _IOR(ESPI_MAGIC_NUMBER, 0x2, struct config)
#define ESPI_INBAND_RESET _IO(ESPI_MAGIC_NUMBER, 0x3)
#define ESPI_SET_IO_MODE _IOW(ESPI_MAGIC_NUMBER, 0x4, struct config)
+#define ESPI_SET_CHAN_MODE _IOW(ESPI_MAGIC_NUMBER, 0x5, struct config)
/*
* enum amd_espi_versions - eSPI controller versions
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 07/10] spi: espi_amd: Add eSPI set frequency IOCTL command
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (5 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 06/10] spi: espi_amd: Add eSPI set channel " Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration Raju Rangoju
` (3 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
This patch adds support for a new IOCTL command in the espi_amd driver to
set the operating frequency of the eSPI controller. The frequency value
can be one of the following supported options: 16MHz, 33MHz or 66MHz.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-dev.c | 40 ++++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index c78a9b2b059b..9f1968566980 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -249,6 +249,43 @@ static int amd_espi_ioctl_set_channel_mode(struct amd_espi *amd_espi, unsigned l
return ret;
}
+static int amd_espi_ioctl_set_freq(struct amd_espi *amd_espi, unsigned long arg)
+{
+ u32 ctrlr_config, slave_config;
+ struct config *config;
+ int ret;
+
+ config = kzalloc(sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ if (copy_from_user(config, (void __user *)arg, sizeof(struct config))) {
+ ret = -EFAULT;
+ goto set_freq_free;
+ }
+
+ ctrlr_config = readl(ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG);
+
+ ret = amd_espi_get_general_config(amd_espi, &slave_config);
+ if (ret != CB_SUCCESS)
+ goto set_freq_free;
+
+ ret = amd_espi_set_freqmode(amd_espi, &slave_config, &ctrlr_config, config->op_freq);
+ if (ret != CB_SUCCESS)
+ goto set_freq_free;
+
+ ret = amd_espi_set_config(amd_espi, slave_config, ESPI_SLAVE_GENERAL_CAPS_CFG);
+ if (ret != CB_SUCCESS) {
+ dev_err(amd_espi->dev, "Set operating frequency failed\n");
+ goto set_freq_free;
+ }
+ writel(ctrlr_config, (ESPI_BASE + AMD_ESPI_SLAVE0_CONFIG_REG));
+
+set_freq_free:
+ kfree(config);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -276,6 +313,9 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_SET_CHAN_MODE:
ret = amd_espi_ioctl_set_channel_mode(amd_espi, arg);
break;
+ case ESPI_SET_FREQ:
+ ret = amd_espi_ioctl_set_freq(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index 3774918d994f..e5760db7c1d3 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -145,6 +145,7 @@
#define ESPI_INBAND_RESET _IO(ESPI_MAGIC_NUMBER, 0x3)
#define ESPI_SET_IO_MODE _IOW(ESPI_MAGIC_NUMBER, 0x4, struct config)
#define ESPI_SET_CHAN_MODE _IOW(ESPI_MAGIC_NUMBER, 0x5, struct config)
+#define ESPI_SET_FREQ _IOW(ESPI_MAGIC_NUMBER, 0x6, struct config)
/*
* enum amd_espi_versions - eSPI controller versions
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (6 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 07/10] spi: espi_amd: Add eSPI set frequency " Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-17 14:10 ` Mark Brown
2025-03-13 18:34 ` [PATCH 09/10] spi: espi_amd: Add eSPI PC channel IO read/write IOCTL commands Raju Rangoju
` (2 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
Add support to configure the eSPI slave0 IO/MMIO address before
initiating the peripheral channel IO/MMIO read and write operations.
This patch introduces new IOCTLs to enable, disable and read IO/MMIO
configurations.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-core.c | 157 ++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd-dev.c | 53 ++++++++++++
drivers/spi/espi-amd.h | 91 +++++++++++++++++++++
3 files changed, 301 insertions(+)
diff --git a/drivers/spi/espi-amd-core.c b/drivers/spi/espi-amd-core.c
index 72a625b8b16d..3704cbd816ae 100644
--- a/drivers/spi/espi-amd-core.c
+++ b/drivers/spi/espi-amd-core.c
@@ -553,6 +553,163 @@ int amd_espi_setup_vw_channel(struct amd_espi *amd_espi, u32 slave_caps)
CHANNEL_MODE_VW);
}
+void amd_espi_get_io_mmio_decode_info(struct amd_espi *amd_espi,
+ struct io_mmio_decode_config *config)
+{
+ config->io_mmio_dc_enable = readl(ESPI_BASE + AMD_ESPI_SLAVE0_DECODE_EN_REG);
+ config->range0.val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG0_REG);
+ config->range1.val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG1_REG);
+ config->range2.val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_IO_SIZE_REG);
+ config->mmio_target_range0 = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG0);
+ config->mmio_target_range1 = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG1);
+ config->mmio_target_range2 = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG2);
+ config->mmio_target_range3 = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG3);
+ config->mmio_range4.val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG0);
+ config->mmio_range5.val = readl(ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG1);
+}
+
+void amd_espi_set_io_mmio_decode_config(struct amd_espi *amd_espi,
+ struct io_mmio_decode_config *config)
+{
+ struct io_mmio_decode_config io_dc_conf;
+
+ amd_espi_get_io_mmio_decode_info(amd_espi, &io_dc_conf);
+ writel(((~(config->io_mmio_dc_enable) & io_dc_conf.io_mmio_dc_enable) |
+ config->io_mmio_dc_enable), (ESPI_BASE + AMD_ESPI_SLAVE0_DECODE_EN_REG));
+
+ /* IO RANGE-0 configuration */
+ if (config->io_mmio_dc_enable & IO_DECODE_RANGE0) {
+ if (config->range0.base_addr_range0 != io_dc_conf.range0.base_addr_range0) {
+ writel(((io_dc_conf.range0.val & CNTRL_IO_DECODE_ADDR_MASK(0)) |
+ config->range0.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG0_REG));
+ writel(((io_dc_conf.range2.val & CNTRL_IO_DECODE_SIZE_MASK(0)) |
+ config->range2.val), (ESPI_BASE + AMD_ESPI_SLAVE0_IO_SIZE_REG));
+ }
+ }
+
+ /* IO RANGE-1 configuration */
+ if (config->io_mmio_dc_enable & IO_DECODE_RANGE1) {
+ if (config->range0.base_addr_range1 != io_dc_conf.range0.base_addr_range1) {
+ writel(((io_dc_conf.range0.val & CNTRL_IO_DECODE_ADDR_MASK(16)) |
+ config->range0.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG0_REG));
+ writel(((io_dc_conf.range2.val & CNTRL_IO_DECODE_SIZE_MASK(8)) |
+ config->range2.val), (ESPI_BASE + AMD_ESPI_SLAVE0_IO_SIZE_REG));
+ }
+ }
+
+ /* IO RANGE-2 configuration */
+ if (config->io_mmio_dc_enable & IO_DECODE_RANGE2) {
+ if (config->range1.base_addr_range2 != io_dc_conf.range1.base_addr_range2) {
+ writel(((io_dc_conf.range1.val & CNTRL_IO_DECODE_ADDR_MASK(0)) |
+ config->range1.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG1_REG));
+ writel(((io_dc_conf.range2.val & CNTRL_IO_DECODE_SIZE_MASK(16)) |
+ config->range2.val), (ESPI_BASE + AMD_ESPI_SLAVE0_IO_SIZE_REG));
+ }
+ }
+
+ /* IO RANGE-3 configuration */
+ if (config->io_mmio_dc_enable & IO_DECODE_RANGE3) {
+ if (config->range1.base_addr_range3 != io_dc_conf.range1.base_addr_range3) {
+ writel(((io_dc_conf.range1.val & CNTRL_IO_DECODE_ADDR_MASK(16)) |
+ config->range1.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_IO_BASE_REG1_REG));
+ writel(((io_dc_conf.range2.val & CNTRL_IO_DECODE_SIZE_MASK(24)) |
+ config->range2.val), (ESPI_BASE + AMD_ESPI_SLAVE0_IO_SIZE_REG));
+ }
+ }
+
+ /* MMIO RANGE-0 configure */
+ if (config->io_mmio_dc_enable & MMIO_DECODE_RANGE0) {
+ if (config->mmio_target_range0 != io_dc_conf.mmio_target_range0) {
+ writel(config->mmio_target_range0,
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG0));
+ writel(((io_dc_conf.mmio_range4.val & CNTRL_MMIO_DECODE_SIZE_MASK(0)) |
+ config->mmio_range4.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG0));
+ }
+ }
+
+ /* MMIO RANGE-1 configure */
+ if (config->io_mmio_dc_enable & MMIO_DECODE_RANGE1) {
+ if (config->mmio_target_range1 != io_dc_conf.mmio_target_range1) {
+ writel(config->mmio_target_range1,
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG1));
+ writel(((io_dc_conf.mmio_range4.val & CNTRL_MMIO_DECODE_SIZE_MASK(16)) |
+ config->mmio_range4.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG0));
+ }
+ }
+
+ /* MMIO RANGE-2 configure */
+ if (config->io_mmio_dc_enable & MMIO_DECODE_RANGE2) {
+ if (config->mmio_target_range2 != io_dc_conf.mmio_target_range2) {
+ writel(config->mmio_target_range2,
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG2));
+ writel(((io_dc_conf.mmio_range5.val & CNTRL_MMIO_DECODE_SIZE_MASK(0)) |
+ config->mmio_range5.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG1));
+ }
+ }
+
+ /* MMIO RANGE-3 configure */
+ if (config->io_mmio_dc_enable & MMIO_DECODE_RANGE3) {
+ if (config->mmio_target_range3 != io_dc_conf.mmio_target_range3) {
+ writel(config->mmio_target_range3,
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_BASE_REG3));
+ writel(((io_dc_conf.mmio_range5.val & CNTRL_MMIO_DECODE_SIZE_MASK(16)) |
+ config->mmio_range5.val),
+ (ESPI_BASE + AMD_ESPI_SLAVE0_MMIO_SIZE_REG1));
+ }
+ }
+}
+
+void amd_espi_disable_io_decode_range(struct amd_espi *amd_espi, u32 io_range)
+{
+ u32 io_mmio_dc_enable = readl(ESPI_BASE + AMD_ESPI_SLAVE0_DECODE_EN_REG);
+
+ switch (io_range) {
+ case 1:
+ if (io_mmio_dc_enable & IO_DECODE_RANGE0)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ IO_DECODE_RANGE0;
+ break;
+ case 2:
+ if (io_mmio_dc_enable & IO_DECODE_RANGE1)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ IO_DECODE_RANGE1;
+ break;
+ case 3:
+ if (io_mmio_dc_enable & IO_DECODE_RANGE2)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ IO_DECODE_RANGE2;
+ break;
+ case 4:
+ if (io_mmio_dc_enable & IO_DECODE_RANGE3)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ IO_DECODE_RANGE3;
+ break;
+ case 5:
+ if (io_mmio_dc_enable & MMIO_DECODE_RANGE0)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ MMIO_DECODE_RANGE0;
+ break;
+ case 6:
+ if (io_mmio_dc_enable & MMIO_DECODE_RANGE1)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ MMIO_DECODE_RANGE1;
+ break;
+ case 7:
+ if (io_mmio_dc_enable & MMIO_DECODE_RANGE2)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ MMIO_DECODE_RANGE2;
+ break;
+ case 8:
+ if (io_mmio_dc_enable & MMIO_DECODE_RANGE3)
+ io_mmio_dc_enable = io_mmio_dc_enable ^ MMIO_DECODE_RANGE3;
+ break;
+ default:
+ break;
+ }
+
+ writel(io_mmio_dc_enable, (ESPI_BASE + AMD_ESPI_SLAVE0_DECODE_EN_REG));
+}
+
static int amd_espi_get_master_cap(struct amd_espi *amd_espi, struct espi_master *master)
{
u32 master_cap_reg, info;
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 9f1968566980..31fb06f4a3ff 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -286,9 +286,49 @@ static int amd_espi_ioctl_set_freq(struct amd_espi *amd_espi, unsigned long arg)
return ret;
}
+static int amd_espi_ioctl_get_io_decode_conf(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct io_mmio_decode_config *io_dc_config;
+ int ret = 0;
+
+ io_dc_config = kzalloc(sizeof(*io_dc_config), GFP_KERNEL);
+ if (!io_dc_config)
+ return -ENOMEM;
+
+ amd_espi_get_io_mmio_decode_info(amd_espi, io_dc_config);
+
+ if (copy_to_user((void __user *)arg, io_dc_config, sizeof(struct io_mmio_decode_config)))
+ ret = -EFAULT;
+
+ kfree(io_dc_config);
+ return ret;
+}
+
+static int amd_espi_ioctl_enable_io_decode_conf(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct io_mmio_decode_config *io_dc_config;
+ int ret = 0;
+
+ io_dc_config = kzalloc(sizeof(*io_dc_config), GFP_KERNEL);
+ if (!io_dc_config)
+ return -ENOMEM;
+
+ if (copy_from_user(io_dc_config, (void __user *)arg,
+ sizeof(struct io_mmio_decode_config))) {
+ ret = -EFAULT;
+ goto decode_config_free;
+ }
+ amd_espi_set_io_mmio_decode_config(amd_espi, io_dc_config);
+
+decode_config_free:
+ kfree(io_dc_config);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
+ u32 io_range = 0;
int ret = 0;
/* Check type and command number */
@@ -316,6 +356,19 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_SET_FREQ:
ret = amd_espi_ioctl_set_freq(amd_espi, arg);
break;
+ case ESPI_GET_IODECODE_CONFIG:
+ ret = amd_espi_ioctl_get_io_decode_conf(amd_espi, arg);
+ break;
+ case ESPI_EN_IODECODE_CONFIG:
+ ret = amd_espi_ioctl_enable_io_decode_conf(amd_espi, arg);
+ break;
+ case ESPI_DS_IODECODE_CONFIG:
+ if (copy_from_user(&io_range, (void __user *)arg, sizeof(unsigned int))) {
+ ret = -EFAULT;
+ break;
+ }
+ amd_espi_disable_io_decode_range(amd_espi, io_range);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index e5760db7c1d3..ae76243786f0 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -33,6 +33,19 @@
#define AMD_ESPI_MISC_CNTRL_REG0 0x38
#define AMD_ESPI_MISC_CNTRL_REG1 0x3c
+/* Slave-0 registers IO and MMIO config registers */
+#define AMD_ESPI_SLAVE0_DECODE_EN_REG 0x40
+#define AMD_ESPI_SLAVE0_IO_BASE_REG0_REG 0x44
+#define AMD_ESPI_SLAVE0_IO_BASE_REG1_REG 0x48
+#define AMD_ESPI_SLAVE0_IO_SIZE_REG 0x4C
+#define AMD_ESPI_SLAVE0_MMIO_BASE_REG0 0x50
+#define AMD_ESPI_SLAVE0_MMIO_BASE_REG1 0x54
+#define AMD_ESPI_SLAVE0_MMIO_BASE_REG2 0x58
+#define AMD_ESPI_SLAVE0_MMIO_BASE_REG3 0x5C
+#define AMD_ESPI_SLAVE0_MMIO_SIZE_REG0 0x60
+#define AMD_ESPI_SLAVE0_MMIO_SIZE_REG1 0x64
+#define AMD_ESPI_MMIO_ADDR_LEN 4
+
/* Slave-0 configuration and interrupt registers */
#define AMD_ESPI_SLAVE0_CONFIG_REG 0x68
#define AMD_ESPI_SLAVE0_INT_EN_REG 0x6C
@@ -136,6 +149,20 @@
#define ESPI_CNTRL_SET_OP_FREQ(conf, freq) (((conf) & ESPI_CNTRL_OP_MODE_MASK) |\
((freq) << ESPI_CNTRL_SLAVE0_FREQ_SHIFT))
+/* Slave-0 IO and MMIO decode enable configurations */
+#define IO_DECODE_RANGE0 BIT(8)
+#define IO_DECODE_RANGE1 BIT(9)
+#define IO_DECODE_RANGE2 BIT(10)
+#define IO_DECODE_RANGE3 BIT(11)
+#define MMIO_DECODE_RANGE0 BIT(12)
+#define MMIO_DECODE_RANGE1 BIT(13)
+#define MMIO_DECODE_RANGE2 BIT(14)
+#define MMIO_DECODE_RANGE3 BIT(15)
+
+#define CNTRL_IO_DECODE_ADDR_MASK(val) (~(GENMASK(15, 0) << (val)))
+#define CNTRL_IO_DECODE_SIZE_MASK(val) (~(GENMASK(3, 0) << (val)))
+#define CNTRL_MMIO_DECODE_SIZE_MASK(val) (~(GENMASK(15, 0) << (val)))
+
#define ESPI_BASE ((u8 __iomem *)amd_espi->io_remap_addr)
/* IOCTL calls */
@@ -146,6 +173,9 @@
#define ESPI_SET_IO_MODE _IOW(ESPI_MAGIC_NUMBER, 0x4, struct config)
#define ESPI_SET_CHAN_MODE _IOW(ESPI_MAGIC_NUMBER, 0x5, struct config)
#define ESPI_SET_FREQ _IOW(ESPI_MAGIC_NUMBER, 0x6, struct config)
+#define ESPI_GET_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x7, struct io_mmio_decode_config)
+#define ESPI_EN_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x8, struct io_mmio_decode_config)
+#define ESPI_DS_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x9, u32)
/*
* enum amd_espi_versions - eSPI controller versions
@@ -282,6 +312,62 @@ struct espi_txcmd {
u32 expected_status_codes;
};
+/* IO/MMIO decode configuartions */
+union io_target_range0 {
+ u32 val;
+ struct {
+ u16 base_addr_range0;
+ u16 base_addr_range1;
+ };
+};
+
+union io_target_range1 {
+ u32 val;
+ struct {
+ u16 base_addr_range2;
+ u16 base_addr_range3;
+ };
+};
+
+union io_target_range2 {
+ u32 val;
+ struct {
+ u32 io_range0_size:8;
+ u32 io_range1_size:8;
+ u32 io_range2_size:8;
+ u32 io_range3_size:8;
+ };
+};
+
+union mmio_target_range4 {
+ u32 val;
+ struct {
+ u32 mmio_range0_size : 16;
+ u32 mmio_range1_size : 16;
+ };
+};
+
+union mmio_target_range5 {
+ u32 val;
+ struct {
+ u32 mmio_range2_size : 16;
+ u32 mmio_range3_size : 16;
+ };
+};
+
+struct io_mmio_decode_config {
+ u32 io_mmio_dc_enable;
+ union io_target_range0 range0;
+ union io_target_range1 range1;
+ union io_target_range2 range2;
+ u32 mmio_target_range0;
+ u32 mmio_target_range1;
+ u32 mmio_target_range2;
+ u32 mmio_target_range3;
+ union mmio_target_range4 mmio_range4;
+ union mmio_target_range5 mmio_range5;
+};
+
/* Function prototypes */
int amd_espi_device_create(struct amd_espi *amd_espi, struct device *dev);
void amd_espi_device_remove(struct amd_espi *amd_espi);
@@ -297,4 +383,9 @@ int amd_espi_get_channel_config(struct amd_espi *amd_espi);
int amd_espi_setup_periph_channel(struct amd_espi *amd_espi, u32 slave_caps);
int amd_espi_setup_vw_channel(struct amd_espi *amd_espi, u32 slave_caps);
void amd_espi_clr_all_intr(struct amd_espi *amd_espi);
+void amd_espi_get_io_mmio_decode_info(struct amd_espi *amd_espi,
+ struct io_mmio_decode_config *config);
+void amd_espi_set_io_mmio_decode_config(struct amd_espi *amd_espi,
+ struct io_mmio_decode_config *config);
+void amd_espi_disable_io_decode_range(struct amd_espi *amd_espi, u32 io_range);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration
2025-03-13 18:34 ` [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration Raju Rangoju
@ 2025-03-17 14:10 ` Mark Brown
2025-03-26 10:12 ` Rangoju, Raju
0 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2025-03-17 14:10 UTC (permalink / raw)
To: Raju Rangoju
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
[-- Attachment #1: Type: text/plain, Size: 464 bytes --]
On Fri, Mar 14, 2025 at 12:04:38AM +0530, Raju Rangoju wrote:
> Add support to configure the eSPI slave0 IO/MMIO address before
> initiating the peripheral channel IO/MMIO read and write operations.
> This patch introduces new IOCTLs to enable, disable and read IO/MMIO
> configurations.
This absolutely does not seem like something that should be exposed to
userspace, if there is some reason for this to be runtime configured it
needs to be clearly explained.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration
2025-03-17 14:10 ` Mark Brown
@ 2025-03-26 10:12 ` Rangoju, Raju
0 siblings, 0 replies; 21+ messages in thread
From: Rangoju, Raju @ 2025-03-26 10:12 UTC (permalink / raw)
To: Mark Brown
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
On 3/17/2025 7:40 PM, Mark Brown wrote:
> On Fri, Mar 14, 2025 at 12:04:38AM +0530, Raju Rangoju wrote:
>
>> Add support to configure the eSPI slave0 IO/MMIO address before
>> initiating the peripheral channel IO/MMIO read and write operations.
>> This patch introduces new IOCTLs to enable, disable and read IO/MMIO
>> configurations.
>
> This absolutely does not seem like something that should be exposed to
> userspace, if there is some reason for this to be runtime configured it
> needs to be clearly explained.
Hi Mark,
Thanks for reviewing this. In subsequent series we are planning to drop
the IOCTLS that are exposed to userspace
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 09/10] spi: espi_amd: Add eSPI PC channel IO read/write IOCTL commands
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (7 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 08/10] spi: espi_amd: Add support for IO/MMIO configuration Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-13 18:34 ` [PATCH 10/10] spi: espi_amd: Add eSPI PC channel MMIO " Raju Rangoju
2025-03-17 14:14 ` [PATCH 00/10] spi: Add driver to support AMD eSPI controller Mark Brown
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
Add new IOCTL commands to perform eSPI peripheral channel(PC) IO
read/write operations with peripherals connected to eSPI slave0.
The changes include validation of IO configuration before initiating
the read/write operations.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-core.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd-dev.c | 53 +++++++++++++++++++++
drivers/spi/espi-amd.h | 16 +++++++
3 files changed, 164 insertions(+)
diff --git a/drivers/spi/espi-amd-core.c b/drivers/spi/espi-amd-core.c
index 3704cbd816ae..18bfd2ca2316 100644
--- a/drivers/spi/espi-amd-core.c
+++ b/drivers/spi/espi-amd-core.c
@@ -114,6 +114,8 @@ static int amd_espi_alloc_cmd_data(struct espi_txcmd *cmd)
case GET_CONFIGURATION:
case IN_BAND_RESET:
size = 1;
+ break;
+ case PERIPHERAL_CHNL:
default:
break;
}
@@ -710,6 +712,99 @@ void amd_espi_disable_io_decode_range(struct amd_espi *amd_espi, u32 io_range)
writel(io_mmio_dc_enable, (ESPI_BASE + AMD_ESPI_SLAVE0_DECODE_EN_REG));
}
+static int is_port_address_valid(struct amd_espi *amd_espi, struct periph_io_rw *msg_io)
+{
+ struct io_mmio_decode_config io_conf;
+ u16 port_end_addr = msg_io->port + msg_io->len - 1;
+
+ amd_espi_get_io_mmio_decode_info(amd_espi, &io_conf);
+
+ if (msg_io->port >= io_conf.range0.base_addr_range0 &&
+ (port_end_addr <= ((u16)io_conf.range0.base_addr_range0 +
+ io_conf.range2.io_range0_size))) {
+ if (!(io_conf.io_mmio_dc_enable & IO_DECODE_RANGE0)) {
+ dev_err(amd_espi->dev, "IO range0 not enabled for port address: 0x%x\n",
+ msg_io->port);
+ return -EINVAL;
+ }
+ } else if ((msg_io->port >= io_conf.range0.base_addr_range1) &&
+ (port_end_addr <= ((u16)io_conf.range0.base_addr_range1 +
+ io_conf.range2.io_range1_size))) {
+ if (!(io_conf.io_mmio_dc_enable & IO_DECODE_RANGE1)) {
+ dev_err(amd_espi->dev, "IO range1 not enabled for port address: 0x%x\n",
+ msg_io->port);
+ return -EINVAL;
+ }
+ } else if ((msg_io->port >= io_conf.range1.base_addr_range2) &&
+ (port_end_addr <= ((u16)io_conf.range1.base_addr_range2 +
+ io_conf.range2.io_range2_size))) {
+ if (!(io_conf.io_mmio_dc_enable & IO_DECODE_RANGE2)) {
+ dev_err(amd_espi->dev, "IO range2 not enabled for port address: 0x%x\n",
+ msg_io->port);
+ return -EINVAL;
+ }
+ } else if ((msg_io->port >= io_conf.range1.base_addr_range3) &&
+ (port_end_addr <= ((u16)io_conf.range1.base_addr_range3 +
+ io_conf.range2.io_range3_size))) {
+ if (!(io_conf.io_mmio_dc_enable & IO_DECODE_RANGE3)) {
+ dev_err(amd_espi->dev, "IO range3 not enabled for port address: 0x%x\n",
+ msg_io->port);
+ return -EINVAL;
+ }
+ } else {
+ dev_err(amd_espi->dev, "Port address 0x%x is invalid\n", msg_io->port);
+ return -EINVAL;
+ }
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_periph_io_write(struct amd_espi *amd_espi, struct periph_io_rw *msg_io)
+{
+ if (is_port_address_valid(amd_espi, msg_io) != CB_SUCCESS)
+ return -EINVAL;
+
+ switch (msg_io->len) {
+ case 1:
+ outb(msg_io->data.data_b, msg_io->port);
+ break;
+ case 2:
+ outw(msg_io->data.data_w, msg_io->port);
+ break;
+ case 4:
+ outl(msg_io->data.data_l, msg_io->port);
+ break;
+ default:
+ dev_err(amd_espi->dev, "Length of IO packet is not valid\n");
+ return -EINVAL;
+ }
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_periph_io_read(struct amd_espi *amd_espi, struct periph_io_rw *msg_io)
+{
+ if (is_port_address_valid(amd_espi, msg_io) != CB_SUCCESS)
+ return -EINVAL;
+
+ switch (msg_io->len) {
+ case 1:
+ msg_io->data.data_b = inb(msg_io->port);
+ break;
+ case 2:
+ msg_io->data.data_w = inw(msg_io->port);
+ break;
+ case 4:
+ msg_io->data.data_l = inl(msg_io->port);
+ break;
+ default:
+ dev_err(amd_espi->dev, "Length of IO packet is not valid\n");
+ return -EINVAL;
+ }
+
+ return CB_SUCCESS;
+}
+
static int amd_espi_get_master_cap(struct amd_espi *amd_espi, struct espi_master *master)
{
u32 master_cap_reg, info;
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 31fb06f4a3ff..184ffdad4a48 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -325,6 +325,53 @@ static int amd_espi_ioctl_enable_io_decode_conf(struct amd_espi *amd_espi, unsig
return ret;
}
+static int amd_espi_ioctl_io_write(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct periph_io_rw *message_io;
+ int ret;
+
+ message_io = kzalloc(sizeof(*message_io), GFP_KERNEL);
+ if (!message_io)
+ return -ENOMEM;
+
+ if (copy_from_user(message_io, (void __user *)arg, sizeof(struct periph_io_rw))) {
+ ret = -EFAULT;
+ goto io_write_free;
+ }
+
+ ret = amd_espi_periph_io_write(amd_espi, message_io);
+
+io_write_free:
+ kfree(message_io);
+ return ret;
+}
+
+static int amd_espi_ioctl_io_read(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct periph_io_rw *message_io;
+ int ret;
+
+ message_io = kzalloc(sizeof(*message_io), GFP_KERNEL);
+ if (!message_io)
+ return -ENOMEM;
+
+ if (copy_from_user(message_io, (void __user *)arg, sizeof(struct periph_io_rw))) {
+ ret = -EFAULT;
+ goto io_read_free;
+ }
+
+ ret = amd_espi_periph_io_read(amd_espi, message_io);
+ if (ret != CB_SUCCESS)
+ goto io_read_free;
+
+ if (copy_to_user((void __user *)arg, message_io, sizeof(struct periph_io_rw)))
+ ret = -EFAULT;
+
+io_read_free:
+ kfree(message_io);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -369,6 +416,12 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
}
amd_espi_disable_io_decode_range(amd_espi, io_range);
break;
+ case ESPI_IO_WRITE:
+ ret = amd_espi_ioctl_io_write(amd_espi, arg);
+ break;
+ case ESPI_IO_READ:
+ ret = amd_espi_ioctl_io_read(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index ae76243786f0..4c67aa9f45a6 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -176,6 +176,8 @@
#define ESPI_GET_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x7, struct io_mmio_decode_config)
#define ESPI_EN_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x8, struct io_mmio_decode_config)
#define ESPI_DS_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x9, u32)
+#define ESPI_IO_WRITE _IOWR(ESPI_MAGIC_NUMBER, 0xa, struct periph_io_rw)
+#define ESPI_IO_READ _IOWR(ESPI_MAGIC_NUMBER, 0xb, struct periph_io_rw)
/*
* enum amd_espi_versions - eSPI controller versions
@@ -368,6 +370,18 @@ struct io_mmio_decode_config {
union mmio_target_range5 mmio_range5;
};
+union io_data {
+ u8 data_b;
+ u16 data_w;
+ u32 data_l;
+};
+
+struct periph_io_rw {
+ u8 len;
+ u16 port;
+ union io_data data;
+} __packed;
+
/* Function prototypes */
int amd_espi_device_create(struct amd_espi *amd_espi, struct device *dev);
void amd_espi_device_remove(struct amd_espi *amd_espi);
@@ -388,4 +402,6 @@ void amd_espi_get_io_mmio_decode_info(struct amd_espi *amd_espi,
void amd_espi_set_io_mmio_decode_config(struct amd_espi *amd_espi,
struct io_mmio_decode_config *config);
void amd_espi_disable_io_decode_range(struct amd_espi *amd_espi, u32 io_range);
+int amd_espi_periph_io_write(struct amd_espi *amd_espi, struct periph_io_rw *message_io);
+int amd_espi_periph_io_read(struct amd_espi *amd_espi, struct periph_io_rw *message_io);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 10/10] spi: espi_amd: Add eSPI PC channel MMIO read/write IOCTL commands
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (8 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 09/10] spi: espi_amd: Add eSPI PC channel IO read/write IOCTL commands Raju Rangoju
@ 2025-03-13 18:34 ` Raju Rangoju
2025-03-17 14:14 ` [PATCH 00/10] spi: Add driver to support AMD eSPI controller Mark Brown
10 siblings, 0 replies; 21+ messages in thread
From: Raju Rangoju @ 2025-03-13 18:34 UTC (permalink / raw)
To: broonie, linux-spi, linux-kernel
Cc: Raju.Rangoju, krishnamoorthi.m, akshata.mukundshetty
Add new IOCTL commands to perform eSPI peripheral channel(PC) MMIO
read/write operations with eSPI slave0. The changes include validation
of MMIO address ranges before initiating the read/write operations.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/spi/espi-amd-core.c | 80 +++++++++++++++++++++++++++++++++++++
drivers/spi/espi-amd-dev.c | 53 ++++++++++++++++++++++++
drivers/spi/espi-amd.h | 9 +++++
3 files changed, 142 insertions(+)
diff --git a/drivers/spi/espi-amd-core.c b/drivers/spi/espi-amd-core.c
index 18bfd2ca2316..31069e86c704 100644
--- a/drivers/spi/espi-amd-core.c
+++ b/drivers/spi/espi-amd-core.c
@@ -805,6 +805,86 @@ int amd_espi_periph_io_read(struct amd_espi *amd_espi, struct periph_io_rw *msg_
return CB_SUCCESS;
}
+static int is_mmio_address_valid(struct amd_espi *amd_espi, struct periph_mem_rw *mem_data)
+{
+ struct io_mmio_decode_config io_conf;
+ u32 mmio_end_addr = mem_data->addr + 3;
+
+ amd_espi_get_io_mmio_decode_info(amd_espi, &io_conf);
+ if (mem_data->addr >= io_conf.mmio_target_range0 &&
+ (mmio_end_addr <= ((u32)io_conf.mmio_target_range0 +
+ io_conf.mmio_range4.mmio_range0_size))) {
+ if (!(io_conf.io_mmio_dc_enable & MMIO_DECODE_RANGE0)) {
+ dev_err(amd_espi->dev, "MMIO range0 not enabled for address: 0x%x\n",
+ mem_data->addr);
+ return -EINVAL;
+ }
+ } else if ((mem_data->addr >= io_conf.mmio_target_range1) &&
+ (mmio_end_addr <= ((u32)io_conf.mmio_target_range1 +
+ io_conf.mmio_range4.mmio_range1_size))) {
+ if (!(io_conf.io_mmio_dc_enable & MMIO_DECODE_RANGE1)) {
+ dev_err(amd_espi->dev, "MMIO range1 not enabled for address: 0x%x\n",
+ mem_data->addr);
+ return -EINVAL;
+ }
+ } else if ((mem_data->addr >= io_conf.mmio_target_range2) &&
+ (mmio_end_addr <= ((u32)io_conf.mmio_target_range2 +
+ io_conf.mmio_range5.mmio_range2_size))) {
+ if (!(io_conf.io_mmio_dc_enable & MMIO_DECODE_RANGE2)) {
+ dev_err(amd_espi->dev, "MMIO range2 not enabled for address: 0x%x\n",
+ mem_data->addr);
+ return -EINVAL;
+ }
+ } else if ((mem_data->addr >= io_conf.mmio_target_range3) &&
+ (mmio_end_addr <= ((u32)io_conf.mmio_target_range3 +
+ io_conf.mmio_range5.mmio_range3_size))) {
+ if (!(io_conf.io_mmio_dc_enable & MMIO_DECODE_RANGE3)) {
+ dev_err(amd_espi->dev, "MMIO range3 not enabled for address: 0x%x\n",
+ mem_data->addr);
+ return -EINVAL;
+ }
+ } else {
+ dev_err(amd_espi->dev, "Address 0x%x is invalid\n", mem_data->addr);
+ return -EINVAL;
+ }
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_periph_mem_write(struct amd_espi *amd_espi, struct periph_mem_rw *mem_data)
+{
+ void __iomem *mmio_addr;
+
+ if (is_mmio_address_valid(amd_espi, mem_data) != CB_SUCCESS)
+ return -EINVAL;
+
+ mmio_addr = ioremap(mem_data->addr, 4);
+ if (!mmio_addr)
+ return -ENOMEM;
+
+ writel(mem_data->data, mmio_addr);
+ iounmap(mmio_addr);
+
+ return CB_SUCCESS;
+}
+
+int amd_espi_periph_mem_read(struct amd_espi *amd_espi, struct periph_mem_rw *mem_data)
+{
+ void __iomem *mmio_addr;
+
+ if (is_mmio_address_valid(amd_espi, mem_data) != CB_SUCCESS)
+ return -EINVAL;
+
+ mmio_addr = ioremap(mem_data->addr, 4);
+ if (!mmio_addr)
+ return -ENOMEM;
+
+ mem_data->data = readl(mmio_addr);
+ iounmap(mmio_addr);
+
+ return CB_SUCCESS;
+}
+
static int amd_espi_get_master_cap(struct amd_espi *amd_espi, struct espi_master *master)
{
u32 master_cap_reg, info;
diff --git a/drivers/spi/espi-amd-dev.c b/drivers/spi/espi-amd-dev.c
index 184ffdad4a48..7e4477dd17e5 100644
--- a/drivers/spi/espi-amd-dev.c
+++ b/drivers/spi/espi-amd-dev.c
@@ -372,6 +372,53 @@ static int amd_espi_ioctl_io_read(struct amd_espi *amd_espi, unsigned long arg)
return ret;
}
+static int amd_espi_ioctl_mem_write(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct periph_mem_rw *mem_data;
+ int ret;
+
+ mem_data = kzalloc(sizeof(*mem_data), GFP_KERNEL);
+ if (!mem_data)
+ return -ENOMEM;
+
+ if (copy_from_user(mem_data, (void __user *)arg, sizeof(struct periph_mem_rw))) {
+ ret = -EFAULT;
+ goto mem_write_free;
+ }
+
+ ret = amd_espi_periph_mem_write(amd_espi, mem_data);
+
+mem_write_free:
+ kfree(mem_data);
+ return ret;
+}
+
+static int amd_espi_ioctl_mem_read(struct amd_espi *amd_espi, unsigned long arg)
+{
+ struct periph_mem_rw *mem_data;
+ int ret;
+
+ mem_data = kzalloc(sizeof(*mem_data), GFP_KERNEL);
+ if (!mem_data)
+ return -ENOMEM;
+
+ if (copy_from_user(mem_data, (void __user *)arg, sizeof(struct periph_mem_rw))) {
+ ret = -EFAULT;
+ goto mem_read_free;
+ }
+
+ ret = amd_espi_periph_mem_read(amd_espi, mem_data);
+ if (ret != CB_SUCCESS)
+ goto mem_read_free;
+
+ if (copy_to_user((void __user *)arg, mem_data, sizeof(struct periph_mem_rw)))
+ ret = -EFAULT;
+
+mem_read_free:
+ kfree(mem_data);
+ return ret;
+}
+
static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct amd_espi *amd_espi = filp->private_data;
@@ -422,6 +469,12 @@ static long amd_espi_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
case ESPI_IO_READ:
ret = amd_espi_ioctl_io_read(amd_espi, arg);
break;
+ case ESPI_MEM_WRITE:
+ ret = amd_espi_ioctl_mem_write(amd_espi, arg);
+ break;
+ case ESPI_MEM_READ:
+ ret = amd_espi_ioctl_mem_read(amd_espi, arg);
+ break;
default:
dev_err(amd_espi->dev, "ESPI command not found, returning error\n");
ret = -EINVAL;
diff --git a/drivers/spi/espi-amd.h b/drivers/spi/espi-amd.h
index 4c67aa9f45a6..9e084bec8ff5 100644
--- a/drivers/spi/espi-amd.h
+++ b/drivers/spi/espi-amd.h
@@ -178,6 +178,8 @@
#define ESPI_DS_IODECODE_CONFIG _IOWR(ESPI_MAGIC_NUMBER, 0x9, u32)
#define ESPI_IO_WRITE _IOWR(ESPI_MAGIC_NUMBER, 0xa, struct periph_io_rw)
#define ESPI_IO_READ _IOWR(ESPI_MAGIC_NUMBER, 0xb, struct periph_io_rw)
+#define ESPI_MEM_WRITE _IOWR(ESPI_MAGIC_NUMBER, 0xc, struct periph_mem_rw)
+#define ESPI_MEM_READ _IOWR(ESPI_MAGIC_NUMBER, 0xd, struct periph_mem_rw)
/*
* enum amd_espi_versions - eSPI controller versions
@@ -382,6 +384,11 @@ struct periph_io_rw {
union io_data data;
} __packed;
+struct periph_mem_rw {
+ u32 addr;
+ u32 data;
+};
+
/* Function prototypes */
int amd_espi_device_create(struct amd_espi *amd_espi, struct device *dev);
void amd_espi_device_remove(struct amd_espi *amd_espi);
@@ -404,4 +411,6 @@ void amd_espi_set_io_mmio_decode_config(struct amd_espi *amd_espi,
void amd_espi_disable_io_decode_range(struct amd_espi *amd_espi, u32 io_range);
int amd_espi_periph_io_write(struct amd_espi *amd_espi, struct periph_io_rw *message_io);
int amd_espi_periph_io_read(struct amd_espi *amd_espi, struct periph_io_rw *message_io);
+int amd_espi_periph_mem_write(struct amd_espi *amd_espi, struct periph_mem_rw *mem_data);
+int amd_espi_periph_mem_read(struct amd_espi *amd_espi, struct periph_mem_rw *mem_data);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 00/10] spi: Add driver to support AMD eSPI controller
2025-03-13 18:34 [PATCH 00/10] spi: Add driver to support AMD eSPI controller Raju Rangoju
` (9 preceding siblings ...)
2025-03-13 18:34 ` [PATCH 10/10] spi: espi_amd: Add eSPI PC channel MMIO " Raju Rangoju
@ 2025-03-17 14:14 ` Mark Brown
2025-03-26 9:55 ` Rangoju, Raju
10 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2025-03-17 14:14 UTC (permalink / raw)
To: Raju Rangoju
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
[-- Attachment #1: Type: text/plain, Size: 646 bytes --]
On Fri, Mar 14, 2025 at 12:04:30AM +0530, Raju Rangoju wrote:
> The eSPI protocol serves as a communication interface between the main
> processor and peripheral devices in computer systems. It offers several
> advantages over the traditional LPC bus, including higher data transfer
> rates, increased scalability and improved system management capabilities.
> The eSPI protocol supports multiple channels, each serving a specific
> purpose in the communication process.
I see nothing in this series that registers a SPI controller with the
SPI core. You need to use the standard frameworks the kernel offers to
provide standard functionality.
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 00/10] spi: Add driver to support AMD eSPI controller
2025-03-17 14:14 ` [PATCH 00/10] spi: Add driver to support AMD eSPI controller Mark Brown
@ 2025-03-26 9:55 ` Rangoju, Raju
2025-03-26 11:05 ` Mark Brown
0 siblings, 1 reply; 21+ messages in thread
From: Rangoju, Raju @ 2025-03-26 9:55 UTC (permalink / raw)
To: Mark Brown
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
On 3/17/2025 7:44 PM, Mark Brown wrote:
Hi Mark,
Thanks for reviewing the patch and apologies for delayed response.
> On Fri, Mar 14, 2025 at 12:04:30AM +0530, Raju Rangoju wrote:
>> The eSPI protocol serves as a communication interface between the main
>> processor and peripheral devices in computer systems. It offers several
>> advantages over the traditional LPC bus, including higher data transfer
>> rates, increased scalability and improved system management capabilities.
>> The eSPI protocol supports multiple channels, each serving a specific
>> purpose in the communication process.
>
> I see nothing in this series that registers a SPI controller with the
> SPI core. You need to use the standard frameworks the kernel offers to
> provide standard functionality.
The AMD SPI controller hardware has only the chip select line enabled,
which is connected to the EC slave in AMD EMB platforms. Currently,
there is no support from the slave device to register as an SPI slave
device with the SPI framework and provide SPI communication.
For this reason, the AMD eSPI driver is designed to handle device
initialization itself and provide a character device file as an
interface with user space for dynamic interaction and configurations.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 00/10] spi: Add driver to support AMD eSPI controller
2025-03-26 9:55 ` Rangoju, Raju
@ 2025-03-26 11:05 ` Mark Brown
2025-04-02 11:43 ` Rangoju, Raju
0 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2025-03-26 11:05 UTC (permalink / raw)
To: Rangoju, Raju
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
[-- Attachment #1: Type: text/plain, Size: 1252 bytes --]
On Wed, Mar 26, 2025 at 03:25:21PM +0530, Rangoju, Raju wrote:
> On 3/17/2025 7:44 PM, Mark Brown wrote:
> > I see nothing in this series that registers a SPI controller with the
> > SPI core. You need to use the standard frameworks the kernel offers to
> > provide standard functionality.
> The AMD SPI controller hardware has only the chip select line enabled, which
> is connected to the EC slave in AMD EMB platforms. Currently, there is no
> support from the slave device to register as an SPI slave device with the
> SPI framework and provide SPI communication.
> For this reason, the AMD eSPI driver is designed to handle device
> initialization itself and provide a character device file as an interface
> with user space for dynamic interaction and configurations.
If you want to ignore the SPI subsystem and just write a driver for your
embedded controller then you should put the driver in the subsystem or
subsystems for that embedded controller (possibly MFD if it does a bunch
of things), not SPI. Even if there is no flexibility you may still want
to have the controller side in the SPI subsystem in order to help with
reuse with different controller/EC combinations but if you're going that
way you need to use the SPI subsystem.
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 00/10] spi: Add driver to support AMD eSPI controller
2025-03-26 11:05 ` Mark Brown
@ 2025-04-02 11:43 ` Rangoju, Raju
0 siblings, 0 replies; 21+ messages in thread
From: Rangoju, Raju @ 2025-04-02 11:43 UTC (permalink / raw)
To: Mark Brown
Cc: linux-spi, linux-kernel, krishnamoorthi.m, akshata.mukundshetty
On 3/26/2025 4:35 PM, Mark Brown wrote:
> On Wed, Mar 26, 2025 at 03:25:21PM +0530, Rangoju, Raju wrote:
>> On 3/17/2025 7:44 PM, Mark Brown wrote:
>
>>> I see nothing in this series that registers a SPI controller with the
>>> SPI core. You need to use the standard frameworks the kernel offers to
>>> provide standard functionality.
>
>> The AMD SPI controller hardware has only the chip select line enabled, which
>> is connected to the EC slave in AMD EMB platforms. Currently, there is no
>> support from the slave device to register as an SPI slave device with the
>> SPI framework and provide SPI communication.
>
>> For this reason, the AMD eSPI driver is designed to handle device
>> initialization itself and provide a character device file as an interface
>> with user space for dynamic interaction and configurations.
>
> If you want to ignore the SPI subsystem and just write a driver for your
> embedded controller then you should put the driver in the subsystem or
> subsystems for that embedded controller (possibly MFD if it does a bunch
> of things), not SPI. Even if there is no flexibility you may still want
> to have the controller side in the SPI subsystem in order to help with
> reuse with different controller/EC combinations but if you're going that
> way you need to use the SPI subsystem.
Thanks for the suggestions Mark. We will rework on this.
^ permalink raw reply [flat|nested] 21+ messages in thread