From: Andy Chiu <andybnac@gmail.com>
To: linux-riscv@lists.infradead.org, alexghiti@rivosinc.com,
palmer@dabbelt.com
Cc: "Andy Chiu" <andy.chiu@sifive.com>,
"Evgenii Shatokhin" <e.shatokhin@yadro.com>,
"Nathan Chancellor" <nathan@kernel.org>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Palmer Dabbelt" <palmer@rivosinc.com>,
"Puranjay Mohan" <puranjay@kernel.org>,
linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org,
llvm@lists.linux.dev, "Mark Rutland" <mark.rutland@arm.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Nick Desaulniers" <nick.desaulniers+lkml@gmail.com>,
"Bill Wendling" <morbo@google.com>,
"Justin Stitt" <justinstitt@google.com>,
puranjay12@gmail.com, paul.walmsley@sifive.com,
greentime.hu@sifive.com, nick.hu@sifive.com,
nylon.chen@sifive.com, eric.lin@sifive.com,
vicent.chen@sifive.com, zong.li@sifive.com,
yongxuan.wang@sifive.com, samuel.holland@sifive.com,
olivia.chu@sifive.com, c2232430@gmail.com
Subject: [PATCH v4 01/12] riscv: ftrace: support fastcc in Clang for WITH_ARGS
Date: Tue, 8 Apr 2025 02:08:25 +0800 [thread overview]
Message-ID: <20250407180838.42877-1-andybnac@gmail.com> (raw)
From: Andy Chiu <andy.chiu@sifive.com>
Some caller-saved registers which are not defined as function arguments
in the ABI can still be passed as arguments when the kernel is compiled
with Clang. As a result, we must save and restore those registers to
prevent ftrace from clobbering them.
- [1]: https://reviews.llvm.org/D68559
Reported-by: Evgenii Shatokhin <e.shatokhin@yadro.com>
Closes: https://lore.kernel.org/linux-riscv/7e7c7914-445d-426d-89a0-59a9199c45b1@yadro.com/
Fixes: 7caa9765465f ("ftrace: riscv: move from REGS to ARGS")
Acked-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
Changelogs v4:
- Add a fix tag (Björn, Evgenii)
---
arch/riscv/include/asm/ftrace.h | 7 +++++++
arch/riscv/kernel/asm-offsets.c | 7 +++++++
arch/riscv/kernel/mcount-dyn.S | 16 ++++++++++++++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
index d627f63ee289..d8b2138bd9c6 100644
--- a/arch/riscv/include/asm/ftrace.h
+++ b/arch/riscv/include/asm/ftrace.h
@@ -146,6 +146,13 @@ struct __arch_ftrace_regs {
unsigned long a5;
unsigned long a6;
unsigned long a7;
+#ifdef CONFIG_CC_IS_CLANG
+ unsigned long t2;
+ unsigned long t3;
+ unsigned long t4;
+ unsigned long t5;
+ unsigned long t6;
+#endif
};
};
};
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index 16490755304e..7c43c8e26ae7 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -501,6 +501,13 @@ void asm_offsets(void)
DEFINE(FREGS_SP, offsetof(struct __arch_ftrace_regs, sp));
DEFINE(FREGS_S0, offsetof(struct __arch_ftrace_regs, s0));
DEFINE(FREGS_T1, offsetof(struct __arch_ftrace_regs, t1));
+#ifdef CONFIG_CC_IS_CLANG
+ DEFINE(FREGS_T2, offsetof(struct __arch_ftrace_regs, t2));
+ DEFINE(FREGS_T3, offsetof(struct __arch_ftrace_regs, t3));
+ DEFINE(FREGS_T4, offsetof(struct __arch_ftrace_regs, t4));
+ DEFINE(FREGS_T5, offsetof(struct __arch_ftrace_regs, t5));
+ DEFINE(FREGS_T6, offsetof(struct __arch_ftrace_regs, t6));
+#endif
DEFINE(FREGS_A0, offsetof(struct __arch_ftrace_regs, a0));
DEFINE(FREGS_A1, offsetof(struct __arch_ftrace_regs, a1));
DEFINE(FREGS_A2, offsetof(struct __arch_ftrace_regs, a2));
diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
index 745dd4c4a69c..e988bd26b28b 100644
--- a/arch/riscv/kernel/mcount-dyn.S
+++ b/arch/riscv/kernel/mcount-dyn.S
@@ -96,7 +96,13 @@
REG_S x8, FREGS_S0(sp)
#endif
REG_S x6, FREGS_T1(sp)
-
+#ifdef CONFIG_CC_IS_CLANG
+ REG_S x7, FREGS_T2(sp)
+ REG_S x28, FREGS_T3(sp)
+ REG_S x29, FREGS_T4(sp)
+ REG_S x30, FREGS_T5(sp)
+ REG_S x31, FREGS_T6(sp)
+#endif
// save the arguments
REG_S x10, FREGS_A0(sp)
REG_S x11, FREGS_A1(sp)
@@ -115,7 +121,13 @@
REG_L x8, FREGS_S0(sp)
#endif
REG_L x6, FREGS_T1(sp)
-
+#ifdef CONFIG_CC_IS_CLANG
+ REG_L x7, FREGS_T2(sp)
+ REG_L x28, FREGS_T3(sp)
+ REG_L x29, FREGS_T4(sp)
+ REG_L x30, FREGS_T5(sp)
+ REG_L x31, FREGS_T6(sp)
+#endif
// restore the arguments
REG_L x10, FREGS_A0(sp)
REG_L x11, FREGS_A1(sp)
--
2.39.3 (Apple Git-145)
next reply other threads:[~2025-04-07 18:08 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-07 18:08 Andy Chiu [this message]
2025-04-07 18:08 ` [PATCH v4 02/12] riscv: ftrace factor out code defined by !WITH_ARG Andy Chiu
2025-04-07 18:08 ` [PATCH v4 03/12] riscv: ftrace: align patchable functions to 4 Byte boundary Andy Chiu
2025-04-07 18:08 ` [PATCH v4 04/12] kernel: ftrace: export ftrace_sync_ipi Andy Chiu
2025-04-08 22:31 ` kernel test robot
2025-04-23 8:13 ` Alexandre Ghiti
2025-04-07 18:08 ` [PATCH v4 05/12] riscv: ftrace: prepare ftrace for atomic code patching Andy Chiu
2025-04-11 13:15 ` Robbin Ehn
2025-04-23 8:22 ` Alexandre Ghiti
2025-05-05 14:06 ` Alexandre Ghiti
2025-05-07 14:18 ` Andy Chiu
2025-05-07 14:35 ` Alexandre Ghiti
2025-04-07 18:08 ` [PATCH v4 06/12] riscv: ftrace: do not use stop_machine to update code Andy Chiu
2025-04-07 18:08 ` [PATCH v4 07/12] riscv: vector: Support calling schedule() for preemptible Vector Andy Chiu
2025-04-07 18:08 ` [PATCH v4 08/12] riscv: add a data fence for CMODX in the kernel mode Andy Chiu
2025-04-07 18:08 ` [PATCH v4 09/12] riscv: ftrace: support PREEMPT Andy Chiu
2025-04-07 18:08 ` [PATCH v4 10/12] riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS Andy Chiu
2026-02-21 12:15 ` Conor Dooley
2026-02-23 15:18 ` Puranjay Mohan
2026-02-23 15:27 ` Conor Dooley
2026-02-23 15:41 ` Puranjay Mohan
2026-02-23 16:29 ` Conor Dooley
2026-02-23 17:36 ` Puranjay Mohan
2026-02-23 17:41 ` Conor Dooley
2025-04-07 18:08 ` [PATCH v4 11/12] riscv: ftrace: support direct call using call_ops Andy Chiu
2025-04-07 18:08 ` [PATCH v4 12/12] riscv: Documentation: add a description about dynamic ftrace Andy Chiu
2025-04-11 12:02 ` Robbin Ehn
2025-04-10 20:05 ` [PATCH v4 01/12] riscv: ftrace: support fastcc in Clang for WITH_ARGS Björn Töpel
2025-05-07 13:58 ` Andy Chiu
2025-06-02 22:12 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250407180838.42877-1-andybnac@gmail.com \
--to=andybnac@gmail.com \
--cc=alex@ghiti.fr \
--cc=alexghiti@rivosinc.com \
--cc=andy.chiu@sifive.com \
--cc=bjorn@rivosinc.com \
--cc=c2232430@gmail.com \
--cc=e.shatokhin@yadro.com \
--cc=eric.lin@sifive.com \
--cc=greentime.hu@sifive.com \
--cc=justinstitt@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-trace-kernel@vger.kernel.org \
--cc=llvm@lists.linux.dev \
--cc=mark.rutland@arm.com \
--cc=morbo@google.com \
--cc=nathan@kernel.org \
--cc=nick.desaulniers+lkml@gmail.com \
--cc=nick.hu@sifive.com \
--cc=nylon.chen@sifive.com \
--cc=olivia.chu@sifive.com \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=puranjay12@gmail.com \
--cc=puranjay@kernel.org \
--cc=samuel.holland@sifive.com \
--cc=vicent.chen@sifive.com \
--cc=yongxuan.wang@sifive.com \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox